CN113630494A

CN113630494A - Integrated circuit and electronic device

Info

Publication number: CN113630494A
Application number: CN202110939471.9A
Authority: CN
Inventors: G·马凯; J·韦格纳; G·迈克里奥德
Original assignee: Cirrus Logic International Semiconductor Ltd
Current assignee: Cirrus Logic International Semiconductor Ltd
Priority date: 2011-05-27
Filing date: 2012-05-25
Publication date: 2021-11-09
Also published as: GB201109012D0; GB2491262B; CN107395303B; CN111355548B; GB2491262A; GB2491261B; GB201209252D0; WO2012164272A2; GB201209255D0; CN103703751A; GB2491261A; CN111355547B; CN107395303A; CN111355547A; CN111355548A; WO2012164272A3; CN103703751B

Abstract

The invention provides an integrated circuit comprising a digital mixing kernel configurable to process a stream of audio data samples, the digital mixing kernel comprising mixing means comprising: a mixer; at least a first source data buffer and a second source data buffer; at least a first destination data buffer (Z1/Z2); the mixing means may be configured to repeatedly establish at least one signal path. The integrated circuit of the present invention is used to interconnect multiple signal sources and signal destinations in a consumer device.

Description

Integrated circuit and electronic device

The application is a divisional application of an invention patent application with an application date of 2012, 5 and 25, an application number of 2012800371674 and a name of 'digital signal routing circuit'. The present application is directed to a divisional application having an application date of 2012, 5/25/2012, an application number of 2017103017972, and a name of "digital signal routing circuit". The present application is directed to divisional applications entitled "integrated circuit and electronic device" filed on 25/5/2012, and having an application number of 2020100139556.

Technical Field

The present invention relates to signal routing circuits, and in particular to signal routing circuits that can be used as digital audio hubs for interconnecting multiple signal sources and signal destinations in consumer devices (of which smart phones are but one example).

Background

It is known to provide an integrated circuit that acts as an "audio hub" that is capable of receiving several signals from both an analog source and a digital source, converting the analog signals to digital signals, and then combining or processing the signals in the digital domain to generate an output signal. If desired, the output signal may be converted to an analog signal by an audio hub for application to an analog transducer, such as a headphone or speaker. Such a digital audio hub device may be incorporated into a consumer device (such as a smart phone or the like) allowing received signals to be processed in a predetermined manner.

It is desirable to allow consumers of such "audio hub" integrated circuits to use it to interconnect several different signal processing components within the consumer device in a flexible manner, without being restricted to a particular external device or a particular processing path.

Disclosure of Invention

According to an aspect of the invention, there is provided an integrated circuit comprising a digital mixing kernel configurable to process a stream of audio data samples, the digital mixing kernel comprising mixing means comprising:

a mixer comprising a multiply-accumulator input and a multiply-accumulator output;

at least first and second source data buffers (A1/A2 and B1/B2), each respectively configurable to repeatedly receive respective at least first and second audio data samples (A and B), and to repeatedly store the respective at least first and second audio data samples;

at least a first destination data buffer (Z1/Z2) configurable to repeatedly store respective at least third audio data samples and to repeatedly send said at least third audio data samples (Z);

the mixing means may be configured to repeatedly establish at least one signal path by:

receiving a first audio data sample within one period (T1) of one Sampling Clock (SCK) (process a);

storing the first audio data samples in a first data source buffer (A1/A2) for a remainder of the period (T1) and for an entire next period (T2) of the Sampling Clock (SCK);

receiving at least one second audio data sample within the period (T1) (process B);

storing the or each second audio data sample in a respective second data source buffer (B1/B2) for the remainder of the period (T1) and for the entire next period (T2);

-taking said stored first audio data samples during said next period (T2);

multiplying the first audio data sample by a first multiplication coefficient, thereby generating a first partial sum over the next period (T2);

-temporarily storing said first partial sum for said next period (T2);

-taking said stored at least one second audio data sample during said next period (T2);

multiplying the or each second audio data sample by a respective second multiplication coefficient, thereby generating at least one respective second partial sum over said next period (T2);

adding the first partial sum and the at least one second partial sum to generate a third audio data sample within the next period (T2); and

storing the third audio data sample in a data destination buffer (Z1/Z2) for a remainder of the next period (T2) and for a duration of a next period (T3).

An integrated circuit according to the invention further comprises at least one input having a source data buffer associated therewith.

An integrated circuit according to the invention further comprises at least one output having a destination data buffer associated therewith.

An integrated circuit according to the invention further comprises at least one signal processing block having a source data buffer and a destination data buffer associated therewith.

The integrated circuit according to the invention comprises at least one fully programmable signal processing block.

An integrated circuit according to the invention comprises at least one partially programmable signal processing block.

The integrated circuit according to the invention comprises at least one signal processing block for performing a specific function, the at least one signal processing block having at least one controllable parameter.

The integrated circuit according to the present invention further comprises:

a source selector comprising at least first and second source selector inputs and a source selector output, the at least first and second source selector inputs being connected to respective at least first and second source data buffers and the source selector output being connected to the multiply-accumulator input, the source selector being configurable to repeatedly couple any of the at least first and second source data buffers to the source selector output; and

a destination selector comprising a destination selector input and at least one destination selector output, said destination selector input being connected to said multiply-accumulator output and said at least one destination selector output being connected to a respective said at least one destination data buffer, said destination selector being configurable to repeatedly couple said destination selector input to said at least first destination data buffer.

An integrated circuit according to the invention further comprises a controller for defining the first and second data source buffers and the data destination buffer of the or each signal path.

An integrated circuit according to the invention, wherein the controller is configured to define the first multiplication factor and the second multiplication factor for the or each signal path.

An integrated circuit according to the invention, wherein the mixing means is configurable to establish a plurality of said signal paths.

An integrated circuit according to the invention, wherein the mixing means is configurable to establish a plurality of said signal paths having different respective sampling clock periods.

An integrated circuit according to the invention, wherein the mixer comprises a bypass path between the multiply accumulator input and the multiply accumulator output.

An integrated circuit according to the invention, wherein the mixing means comprises a plurality of said mixers having respective multiply-accumulator inputs, each respective multiply-accumulator input being connectable to any one of the source data buffers and each respective multiply-accumulator output being connectable to a respective subset of said destination data buffers.

An integrated circuit according to the invention, wherein the mixing means comprises a plurality of said mixers having respective multiply-accumulator inputs, each respective multiply-accumulator input being connectable to any of said source data buffers and each respective multiply-accumulator output being connectable to any of said destination data buffers.

According to another aspect of the invention, there is provided an electronic device comprising the integrated circuit described above.

According to another aspect of the invention, there is provided a communication device comprising the integrated circuit described above.

According to another aspect of the present invention, there is provided a method of processing a stream of audio data samples, the method comprising repeatedly performing the steps of:

-taking said stored first audio data samples during said next period (T2);

-temporarily storing said first partial sum for said next period (T2);

The method according to the invention further comprises repeatedly performing the steps of:

receiving a fourth audio data sample within said period (T1) of the Sampling Clock (SCK) (process C);

storing the fourth audio data samples in a third data source buffer (C1/C2) for a remainder of the period (T1) and for an entire next period (T2) of the Sampling Clock (SCK);

receiving at least one fifth audio data sample within the period (T1) (process D);

storing the or each fifth audio data sample in a respective fourth data source buffer (B1/B2) for the remainder of said period (T1) and for the whole of said next period (T2);

-taking said stored fourth audio data sample during said next period (T2);

multiplying the fourth audio data sample by a third multiplication coefficient, thereby generating a third partial sum over the next period (T2);

-temporarily storing said third partial sum for said next period (T2);

-taking said stored at least one fifth audio data sample within said next period (T2);

multiplying the or each fifth audio data sample by a respective fourth multiplication coefficient, thereby generating at least one respective fourth partial sum in said next period (T2);

adding the third partial sum to the at least one fourth partial sum to generate a sixth audio data sample within the next period (T2);

storing the sixth audio data sample in a data destination buffer (Y1/Y2) for a remainder of the next period (T2) and for a duration of the next period (T3).

According to the method of the invention, each data source buffer is associated with a respective audio input or signal processing block.

According to the method of the invention, each data destination buffer is associated with a respective audio output or signal processing block.

According to another aspect of the invention, there is provided an integrated circuit comprising:

a digital mixing kernel configurable to combine a plurality of streams of audio data samples, the digital mixing kernel comprising:

a plurality of digital signal processing blocks, wherein each of the digital signal processing blocks includes a source port and a destination port, each of the digital signal processing blocks configurable to: receiving a stream of audio data samples at a corresponding sampling clock rate at the destination port, processing the received stream of audio data samples, and transmitting the processed stream of audio data samples from the source port at the corresponding sampling clock rate;

a clock generator configurable to generate at least one data clock; and

a mixing member, the mixing member comprising:

a mixer comprising a multiply-accumulator input and a multiply-accumulator output, the mixer configurable to combine audio data samples in response to the data clock;

a source selector comprising a plurality of source selector inputs and a source selector output, the source selector output connected to the multiply-accumulator input,

a plurality of source buffers, each of the source buffers respectively connected between a source port and a source selector input, each source buffer configurable to temporarily store a respective one of the transmitted streams of audio data samples,

wherein the source selector is configurable to couple any of the respective source buffers to the multiply-accumulator input in response to a source selector control signal;

a destination selector comprising a destination selector input and a plurality of destination selector outputs, said destination selector input being connected to said multiply-accumulator output,

a plurality of destination buffers, each destination buffer respectively connected between a said destination port and a said destination selector output, each destination buffer configurable to temporarily store a respective one of said combined streams of audio data samples,

wherein the destination selector is configurable to couple any of the respective destination buffers to the multiply-accumulator output in response to a destination selector control signal; and

programmable storage circuitry configurable to store a plurality of configuration data sets, each of the plurality of configuration data sets defining a respective signal path including a data path to

Two fewer source ports and one fewer destination port; and

a controller coupled to the programmable storage circuitry, the source selector, and the destination selector, the controller configured to receive a plurality of configuration data and control the source selector with a source selector control signal, the destination selector with a destination selector control signal to establish each of a plurality of respective the defined signal paths on a time division multiplexed basis in response to the data clock within each cycle of a respective sampling clock.

In accordance with the present invention, the programmable storage circuitry is configurable to store a second plurality of configuration data sets, each of the second plurality of configuration data sets correspondingly defining a signal path that includes a source port and a destination port, and wherein when the signal path includes a source port, each destination buffer is also configurable to temporarily store a sample of a corresponding stream of output audio data samples derived from a stream of audio data samples received from the source port.

In an integrated circuit according to the invention, wherein the programmable storage circuitry is configurable such that each of said sets of configuration data identifies at least one scaling factor,

the multiplier-accumulator mixer may be configured to multiply the or each received audio data sample by a respective scaling factor.

An integrated circuit according to the invention, wherein the integrated circuit further comprises a plurality of digital input interfaces providing a further plurality of corresponding signal source ports.

An integrated circuit according to the invention, wherein the integrated circuit further comprises a plurality of digital output interfaces providing a further plurality of corresponding signal destination ports.

According to the integrated circuit of the invention, wherein the controller is configurable to define a direct signal path from one of said digital input interfaces to one of said digital output interfaces via the multiplier-accumulator.

In accordance with the present invention, an integrated circuit is provided in which the programmable storage circuitry is configurable to store a respective data sampling rate for signal paths in each of a plurality of configuration data sets, the data sampling rates of the signal paths being configurable independently of one another.

An integrated circuit according to the invention, wherein each of said plurality of configuration data sets defines a respective sampling rate.

According to the integrated circuit of the invention, the sampling rate of each signal path can be programmed independently.

An integrated circuit according to the invention, wherein the programmable storage circuitry is configurable to store data defining a sample rate for all destination ports on at least one signal processing block in a single location.

An integrated circuit according to the invention, wherein the programmable storage circuitry is configurable to store data indicative of one of a predetermined plurality of available sampling clocks.

An integrated circuit according to the invention, wherein the number of signal paths that can be established in each cycle of the respective sampling clock is much smaller than the number of signal paths required to connect all signal source ports to all signal destination ports.

An integrated circuit according to the invention, wherein the controller comprises a mixer utilization predictor for identifying each defined signal path, for determining a number of computations to be performed for each defined signal path in a specified time interval, and for setting a frequency of the data clock such that the number of computations can be performed in the specified time interval.

The integrated circuit according to the invention, wherein the controller is adapted to receive an input identifying a plurality of available data clock rates, and to select the frequency of the data clock as the lowest data clock rate of the available data clock rates enabling said number of calculations to be performed in the specified time interval.

The integrated circuit according to the invention, wherein the controller is configured such that, at successive time intervals, the signal path established by the source selector control signal and the destination selector control signal is determined on the basis of: the signal path is the signal path having the shortest time before the end of one period of one clock signal at the corresponding data sampling rate.

An integrated circuit according to the invention comprises a register for storing details of the activated signal paths, identifying the or each signal source port, identifying the signal destination port, and identifying the corresponding data sample rate for each activated signal path.

An integrated circuit according to the invention comprises a down counter associated with each available data sample rate for maintaining a count of the time remaining before the end of a period of a clock signal at the respective data sample rate, and a logic circuit for selecting the sample rate having the shortest time before the end of a period of a clock signal at the respective data sample rate.

The integrated circuit according to the invention further comprises a logic circuit for selecting one of the signal paths having the selected sampling rate.

The integrated circuit according to the present invention further comprises:

at least one additional signal processing block connected to receive a digital input signal and to provide a digital output signal without passing said signal through the mixer.

An integrated circuit according to the invention comprises down-sampling circuitry for receiving the digital input signal of the additional signal processing block in parallel with the additional signal processing block and for providing the down-sampled digital input signal at a signal source port comprised by the down-sampling circuitry.

An integrated circuit according to the invention comprises up-sampling circuitry comprising a signal destination port and arranged to provide an up-sampled digital output signal.

The integrated circuit according to the invention, wherein the additional signal processing block is connected to receive a control signal from at least one of the plurality of first signal processing blocks.

The integrated circuit according to the invention, wherein the additional signal processing block is configured to process the digital input signal with a sampling rate of at least 384k samples/sec.

The integrated circuit according to the invention, wherein said additional signal processing block comprises filter circuitry for generating a noise cancellation signal based on an input signal representing ambient noise.

An integrated circuit according to the invention, wherein the clock generator is configured to generate a plurality of clock signals at respective different frequencies; and

wherein each of the plurality of signal processing blocks requires a clock signal at a preferred frequency;

also included is selection circuitry configured such that each of the signal processing blocks receives the clock signal at the preferred frequency.

The integrated circuit according to the invention further comprises a logic circuit for receiving the control signal generated by each of the signal processing blocks and for allowing a clock signal to be distributed only if it has a preferred frequency of one or more signal processing blocks.

In accordance with the integrated circuit of the present invention, the programmable storage circuitry is further configured to store, in each of the plurality of configuration data sets, a respective scaling factor by which data samples from each source port should be multiplied before combining to form combined audio data samples.

According to another aspect of the present invention, there is provided a communication apparatus including: the integrated circuit according to the above.

The communication apparatus according to the present invention further comprises:

an application processor; and

a communication processor.

According to another aspect of the present invention, there is provided an electronic apparatus including: the integrated circuit according to the above.

a digital mixer core configurable to mix streams of audio data samples, the digital mixing core comprising:

a plurality of digital signal processing blocks, each digital signal processing block comprising:

one or more source ports configurable to send respective audio data samples at respective sampling clock rates; and

one or more destination ports configurable to receive respective audio data samples at respective sampling clock rates,

the digital mixing kernel further comprises:

a mixer comprising a multiply-accumulate block comprising an input and an output, the mixer configurable to combine audio data samples in response to a received data clock;

a clock generator configurable to generate at least the data clock;

a source selector configurable to couple the multiply-accumulate block input to any of the one or more source ports; and

a destination selector configurable to couple the multiply-accumulate block output to any of the one or more destination ports;

wherein the source selector and the destination selector are sequentially configurable, respectively, at a frequency of the data clock to sequentially establish a set of signal paths through the mixer, each signal path including any one of the one or more destination ports and one or more source ports of the one or more source ports; and

wherein the data clock has a frequency that is less than a frequency necessary to establish a signal path including each source port for each destination port within one cycle of each respective sampling clock.

The integrated circuit according to the invention further comprises a control block for configuring the source selector and the destination selector.

The integrated circuit according to the invention further comprises a control block for controlling the clock generator to generate the data clock at said frequency.

According to the integrated circuit of the invention, the data clock frequency is controlled based on the defined number of signal paths through the mixer.

According to the integrated circuit of the invention, the data clock frequency is controlled based on the respective sampling rate of the defined signal path through the mixer.

The integrated circuit according to the invention, wherein the control block further controls the supply voltage supplied to the mixer.

According to the integrated circuit of the invention, wherein the supply voltage supplied to the mixer is controlled based on the data clock frequency.

An integrated circuit according to the invention, wherein the control block comprises a mixer utilization predictor for identifying each defined signal path, for estimating a number of calculations to be performed by the mixer for each defined signal path in a specified time interval, and for setting the data clock frequency such that said number of calculations can be performed in the specified time interval.

In accordance with the invention, the control block is configured to receive an input identifying a plurality of available clock frequencies, and to select the data clock frequency supplied to the mixer as the lowest of the available data clock frequencies that is estimated such that the number of calculations can be performed in the specified time interval.

An integrated circuit according to the invention, wherein the clock generator is configurable to generate a plurality of clock signals at respective different frequencies; and

wherein the mixer is one of a plurality of functional blocks, each functional block requiring a clock signal at a preferred frequency;

wherein the integrated circuit further comprises selection circuitry associated with each functional block for receiving the plurality of clock signals and configured to transmit the clock signal at the preferred frequency to the associated functional block.

An integrated circuit according to the invention further comprises logic circuitry for receiving control signals generated by each of the signal processing blocks indicative of their respective preferred frequencies and for allowing a clock signal to be distributed only if it has the preferred frequency of one or more functional blocks.

An integrated circuit according to the invention, wherein the clock generator comprises circuitry for generating a clock signal at a first frequency and at least one frequency divider, each frequency divider for generating a respective clock signal at a frequency which is a fraction of the first frequency.

According to the invention, an integrated circuit in the form of an audio codec comprises:

at least one digital input interface to receive a digital signal from another integrated circuit, the digital input interface having one or more additional source ports configurable to send respective audio data samples at respective sampling clock rates.

at least one analog input interface for receiving an analog signal from another circuit, an

An analog-to-digital converter having one or more additional source ports configurable to send respective audio data samples at respective sampling clock rates.

at least one digital output interface for transmitting a digital signal to another integrated circuit, the digital output interface having one or more additional destination ports configurable to receive respective audio data samples at respective sampling clock rates.

at least one analog output interface for transmitting analog signals to another circuit, an

A digital-to-analog converter having one or more additional destination ports configurable to receive respective audio data samples at respective sampling clock rates.

An integrated circuit according to the invention, wherein the sampling clock rate of each signal path defined by the respective sampling rates of one of the destination ports and one or more of the source ports is the same.

An integrated circuit according to the invention, wherein the sampling clock rate of each signal path defined by the respective sampling rates of one of the destination ports and one or more of the source ports is user configurable.

According to the invention, the integrated circuit wherein the sampling clock rate of each signal path is defined by the respective sampling rate of one of said destination ports.

According to another aspect of the invention, there is provided an integrated circuit comprising a digital mixing core comprising a plurality of signal sources and signal destinations, and at least one mixer to which the signal sources and signal destinations can be connected on a time division multiplexed basis to establish signal paths,

where each signal destination requires data at a respective predetermined sample rate,

wherein the or each mixer operates at a clock frequency, and

wherein:

here:

m_jthe number of mixers running at the jth mixer clock frequency,

C_R,jis the jth mixer clock frequency in use,

S_R,iis the ith sample rate in use in the system,

N_s,iis the number of signal sources providing data at the ith sample rate, and

N_d,iis the number of signal destinations requiring data at the ith sample rate.

Drawings

For a better understanding of the present invention, and to show how it may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which:

FIG. 1 shows a mobile phone and a plurality of peripheral devices;

FIG. 2a shows components of audio processing circuitry in the mobile phone of FIG. 1;

FIG. 2b shows components of an alternative audio processing circuitry in a mobile telephone;

FIG. 3 is a first more detailed block diagram showing the form of audio hub routing circuitry in the audio processing circuitry of FIG. 2a or 2 b;

FIG. 4 is a block diagram, again in greater detail, illustrating the form of pre-conditioning circuitry in the routing circuitry of FIG. 3;

FIG. 5 is a block diagram of further yet more detailed switching circuitry in the routing circuitry of FIG. 3;

FIG. 6 is a block diagram of further yet more detailed showing an alternative form of switching circuitry in the routing circuitry of FIG. 3;

FIG. 7 is a block diagram of further yet more detailed showing the form of down-sampling circuitry in the routing circuitry of FIG. 3;

FIG. 8 is a block diagram of further yet more detailed showing the form of up-sampling circuitry in the routing circuitry of FIG. 3;

FIG. 9 is a block diagram further in greater detail, showing the form of post-conditioning circuitry in the routing circuitry of FIG. 3;

FIG. 10 is a block diagram of further yet more detailed circuitry showing the form of a digital mixing core (digital mixing core) in the routing circuitry of FIG. 3;

FIG. 11 shows a portion of one of the functional blocks in the digital mixing kernel of FIG. 10 in greater detail;

FIG. 12 shows a portion of another functional block in the digital mixing kernel of FIG. 10 in greater detail;

FIG. 13 illustrates in more detail a portion of yet another functional block in the digital mixing kernel of FIG. 10;

FIG. 14 is yet another block diagram illustrating the digital mixing kernel of FIG. 10 and showing more details of the various functional blocks;

FIG. 15 is a block diagram illustrating a different aspect of a digital mixing kernel in one embodiment;

FIG. 16 is a block diagram illustrating various aspects of a digital mixing kernel in another embodiment;

FIG. 17 is a block diagram illustrating various aspects of a digital mixing kernel in yet another embodiment;

FIG. 18 is a block diagram illustrating various aspects of a digital mixing kernel in yet another embodiment;

FIG. 19 is a block diagram illustrating various aspects of a digital mixing kernel in yet another embodiment;

FIG. 20 is a block diagram illustrating a portion of a digital mixing kernel in one embodiment;

FIG. 21 is a block diagram illustrating a portion of a digital mixing kernel in another embodiment;

FIG. 22 is a block diagram illustrating a form of a multiply-accumulate block (multiply-accumulate block) in a digital mixing kernel;

FIG. 23 is a block diagram illustrating in greater detail an alternative form of multiply-accumulate block in a digital mixing kernel;

FIG. 24 is a flowchart illustrating a process performed in the mixer;

FIG. 25 is yet another illustration of the process shown in FIG. 24;

FIG. 26 is a first timing diagram illustrating the process of FIG. 24;

FIG. 27 is a second timing diagram illustrating more details of the process of FIG. 26;

FIG. 28 is a third timing diagram illustrating yet another alternative process;

FIG. 29 is a fourth timing diagram illustrating yet another alternative process;

FIG. 30 is a flow chart illustrating a method of defining operation of switching circuitry;

FIG. 31 is a diagram of a computer screen shot illustrating a stage in the method of FIG. 30;

FIG. 32 is a block diagram showing routing in one use case (use case) defined by the process of FIG. 30;

FIG. 33 is a register map (map) illustrating an initial state of a register bank in the process of FIG. 30;

FIG. 34 is a block diagram providing an alternative illustration of routing in the use case of FIG. 32 on the digital mixing kernel of FIG. 14;

FIG. 35 is a register map illustrating a state of a register bank at yet another point in the process of FIG. 30;

FIG. 36 is a diagram of a digital mixing kernel illustrating the functional blocks involved in the use case shown in FIG. 32;

FIG. 37a shows a route in yet another use case;

FIG. 37b shows a route in yet another use case;

FIG. 38 is a timing chart illustrating a first series of calculations in a process performed in the mixer;

FIG. 39 is a timing chart illustrating a second series of calculations in a process performed in the mixer;

FIG. 40 is a timing chart illustrating a third series of calculations in a process performed in the mixer;

FIG. 41 is a timing chart illustrating a fourth series of calculations in a process performed in the mixer;

FIG. 42 is a timing chart illustrating a fifth series of calculations in a process performed in the mixer;

FIG. 43 is a block diagram illustrating a clock generator in the switching circuit;

FIG. 44 is a block diagram illustrating yet another aspect of the clock generator;

FIG. 44a is a block diagram illustrating an alternative form of the clock generator;

FIG. 44b is a block diagram illustrating yet another alternative form of the clock generator;

FIG. 44c is a block diagram illustrating yet another aspect of alternative forms of the clock generator;

FIG. 45 is a block diagram illustrating a mixer according to one embodiment;

FIG. 46 is a flow chart illustrating a first method performed in the mixer of FIG. 45;

FIG. 47 is a flow chart illustrating a second method performed by the mixer of FIG. 45;

FIG. 48 is a flow chart illustrating a third method performed by the mixer of FIG. 45;

FIG. 49 is a block diagram illustrating in greater detail the enable and clock control block of the mixer of FIG. 45;

FIG. 50 is a flow chart illustrating a method performed in the enable and clock control block of FIG. 49;

FIG. 51 is a flow chart illustrating yet another method performed in the enable and clock control block of FIG. 49;

fig. 52a is a block diagram illustrating in more detail the channel scheduler in the mixer of fig. 45;

FIG. 52b is a flow chart illustrating a method performed in the channel scheduler of FIG. 52 a;

FIG. 53 is a flow chart illustrating yet another method performed in the channel scheduler of FIG. 52 a;

FIG. 54 is a block diagram illustrating in greater detail the calculation block of the mixer of FIG. 45;

FIG. 55 is a flow chart illustrating a portion of the method performed in the channel scheduler block of FIG. 52a and the calculation block of FIG. 54;

FIG. 56 is a schematic diagram illustrating a portion of an electronic device in accordance with an aspect of the present invention;

FIG. 57 is a schematic diagram illustrating a portion of a second electronic device in accordance with an aspect of the present invention;

FIG. 58 is a schematic diagram illustrating a portion of a third electronic device in accordance with an aspect of the present invention;

FIG. 59 is a schematic diagram illustrating a portion of a fourth electronic device in accordance with an aspect of the present invention;

FIG. 60 is a schematic diagram illustrating a portion of a fifth electronic device in accordance with an aspect of the present invention; and is

FIG. 61 is a schematic diagram illustrating a portion of a sixth electronic device in accordance with an aspect of the present invention.

Detailed Description

Fig. 1 shows a consumer device, in this embodiment a mobile phone 1, more particularly in the form of a smart phone, according to an aspect of the invention. In this embodiment the mobile telephone 1 has a screen 3 and a keypad 5, although of course the invention is equally applicable to devices with a touch screen or other user interface. The mobile phone 1 also has a built-in loudspeaker 7 and a built-in main microphone 9, which are both analog transducers. The mobile phone 1 also has a plurality of microphones, in this particular embodiment four microphones 11 (which may be analog or digital microphones), allowing a plurality of ambient noise signals to be received, for example for use in a noise cancellation system.

As shown in fig. 1, the mobile phone 1 may have a jack socket (not illustrated) or similar connection means, such as a USB socket or a multi-pin connector socket, allowing a headset (headset) comprising a pair of stereo earpieces 13 and possibly a microphone 15 to be connected to the mobile phone by a wire. Alternatively, the mobile telephone 1 may be wirelessly connected, for example using the bluetooth (trade mark) communications protocol, to a wireless headset 17, the wireless headset 17 having an earpiece 19 and possibly a microphone 21. Although not illustrated, the

earplugs

13, 19 may include one or more ambient noise microphones (which may be analog or digital microphones) allowing one or more ambient noise signals to be received, for example for use in a noise cancellation system.

Alternatively or additionally, the mobile telephone 1 may have a jack or similar connection means allowing it to be connected to an external audio system 23, for example for music reproduction, which system includes one or more speakers 25. The external audio system 23 may be, for example, a desktop stereo system or an in-car audio system. The circuitry (circuitry)27 of the external audio system 23 may include a radio receiver or other audio source that may provide audio input to the mobile telephone 1 so that radio or other audio may be played through the speaker 7 or through the

earpieces

13, 19 of a selected one of the headsets. Alternatively, music stored on the phone may be played through speaker 25 of external audio system 23.

It can thus be seen that many possible audio signals can be output. For example, if the mobile phone 1 has a connector allowing it to be fitted to a docking station (docking station) in a motor vehicle and is equipped with a satellite navigation system, the mobile phone 1 may need to be able to simultaneously: (a) manipulating a mobile telephony session via a wired or wireless handset; (b) provide stereo music from its memory to the external audio system 23; and (c) providing a tone for confirming the button press and providing a navigation instruction via the built-in speaker. As a result, the switching circuitry in the mobile telephone 1 must be able to manipulate at least these three separate output audio data signals, as well as the input audio data signals for the mobile telephone conversation, in accordance with the above-described embodiments.

Fig. 2a shows the components of the audio manipulation system in the mobile phone 1. Communication with the cellular telephone network 29 is handled by a baseband processor (sometimes referred to as a communication processor) 31. The application processor 33 handles the process of rendering audio data from the memory 35 (which may be solid state or on disk, and which may be built-in or attachable, e.g. permanently in the mobile phone or on a removable memory device) or storing audio data in the memory 35, and other processes of generating audio data internally in the phone 1, among others. For example, the application processor 33 may manipulate the reproduction of stereo music digitally stored in the memory 35, may manipulate the recording of telephone conversations and other audio data into the memory 35, and will also manipulate the generation of satellite navigation commands and the generation of tones to confirm the pressing of any buttons on the keypad 5. The wireless transceiver (or wireless codec) 37 handles communications using the bluetooth (trademark) protocol or other short range communication protocol, such as with the wireless headset 17.

The baseband processor 31, applications processor 33 and wireless transceiver 37 all transmit audio data to and receive audio data from switching circuitry in the form of an audio hub 39. The audio hub 39 takes the form of an integrated circuit in this described embodiment. In the above embodiment, the audio signals between the audio hub 39 and the baseband processor 31, the application processor 33 and the wireless transceiver 37 are all digital, and some of them may be stereo, including left and right data streams. Additionally, at least in case of communication with the application processor 33, further data streams may be multiplexed (multiplexed) into these audio signals, for example to enable the application processor 33 to provide stereo music while also providing other audio signals, such as key press confirmation tones.

The audio hub 39 communicates with the baseband processor 31, the application processor 33 and the wireless transceiver 37 via respective audio data links (i.e.

buses

38b, 38a, 38c), and the audio hub 39 has respective

digital interfaces

40b, 40a, 40c for these data links.

The audio hub 39 also provides audio signals to and receives audio signals from the built-in analog audio transducer of the mobile telephone 1. As shown in fig. 2, the audio hub 39 provides output audio signals to the speaker 7 and receives input audio signals from the

microphones

9, 11.

The audio hub 39 may also be connected to other output transducers 43, the output transducers 43 may be analog or digital transducers, and may be built into the mobile phone 1 (e.g. in case of tactile output transducers) or a device external to the mobile phone 1 (e.g. the earpiece 13 of a wired headset shown in fig. 1). The audio hub 39 may also be connected to other input transducers 45, the input transducers 45 may also be analog or digital transducers, and may also be built into the mobile phone 1 (e.g. an ultrasound microphone) or a device external to the mobile phone 1 (e.g. the microphone 15 of the wired headset).

The audio hub 39 may also be required to receive signals from other sources, such as an FM radio receiver 41, which may be in the external audio system 23 or may be provided on a separate IC in the mobile telephone 1, and may generate analog or digital signals.

It should be appreciated that fig. 2 illustrates only one possible use of the audio hub 39, but that an audio hub integrated circuit according to the present invention may be used in a wide variety of electronic devices, including industrial, professional, or consumer devices, such as video cameras (DSCs and/or video recorders), portable media players, PDAs, game consoles, satellite navigation devices, tablets, notebook computers, televisions, or the like.

The audio hub integrated circuit may be optimized for one specific category of a wide variety of industrial, professional, or consumer devices. For example, although fig. 1 shows one particular form of smartphone 1, it will be appreciated that other smartphone models will have different levels of functionality and therefore will have different audio handling requirements, and that the audio hub integrated circuit may be designed to be able to handle such a wide variety of requirements. As described below, the audio hub 39 is optimized for use in a smart phone, but can also be used in a wide variety of smart phones having different audio operating requirements.

In any case, even if the audio hub integrated circuit has been optimized for use in a class of consumer devices (such as smart phones), it will likely be available in a range of types of consumer devices, since it is unknown what the individual signals represent. The number and type of interfaces and the number and type of signal processing blocks provided in the audio hub integrated circuit will determine the range of types of consumer devices that it will be available for, and the manufacturer may choose whether to manufacture an audio hub integrated circuit that may be cheaper to produce (because it has limited functionality but is well designed for a particular purpose), or whether to manufacture an audio hub integrated circuit that has greater functionality and therefore can be used for many different purposes.

Figure 2b shows an alternative audio manipulation system component in a mobile phone. Again, communication with the cellular telephone network 29 is handled by a baseband processor (or communication processor) 31, and the application processor 33 handles the process of reproducing audio data from the memory 35 or storing audio data in the memory 35, as well as other processes of internally generating audio data in the telephone 1. For example, the application processor 33 may manipulate the reproduction of stereo music digitally stored in the memory 35, may manipulate the recording of telephone conversations and other audio data into the memory 35, and will also manipulate the generation of satellite navigation commands and manipulate the generation of tones to confirm the pressing of any buttons on the keypad 5. In this alternative mobile phone, no wireless codec is present. As a result, the audio hub 39a need only have a first digital audio interface 40a and a second digital audio interface 40b, the application processor 33 may be connected to the first digital audio interface 40a, and the communication processor 31 may be connected to the second digital audio interface 40 b. An audio hub 39 as shown in fig. 2 can easily be used in this alternative mobile phone. However, it is sufficient that the audio hub 39a has only two digital audio interfaces, and may be smaller and less expensive than an audio hub having three digital audio interfaces.

Although reference is made herein to an "audio signal," the electrical signal manipulated by the "audio hub" integrated circuit may represent any physical phenomenon. For example, the term "audio signal" may mean not only a signal representing sound audible to the human ear (e.g. in the frequency range of 20Hz to 20 kHz), but also input and/or output signals from and/or to the tactile transducer (typically frequencies below 20Hz or at least below 300 Hz), and/or input and/or output signals from and/or to the ultrasonic transducer (e.g. in the frequency range of 20kHz to 300 kHz), and input and/or output signals from and/or to the secondary transducer (typically frequencies below 20 Hz). It is possible that the "audio hub" may not receive any audio signals in the audible range of the human ear, e.g. a dedicated "audio hub" in the design or in a specific use case may only receive "audio signals" related to tactile or ultrasonic signals.

Fig. 3 is a block diagram showing in more detail the form of the audio hub or routing circuit 39. In this case the audio hub or routing circuit is optimised for use in a device such as a smartphone and will be described accordingly, but it will be appreciated that this illustrated circuit is only one embodiment of a routing circuit according to the invention and that the use described in a smartphone is only one possible use of the illustrated circuit. Thus, the audio hub has the functionality of an audio codec, accepting audio data in one format and processing it, if required, into a different format.

The audio hub routing circuit 39 acts as an audio codec and is based on an audio processing engine (audio processing engine) in the form of a digital mixing kernel 50, for example, for providing signal routing between multiple inputs and outputs of the audio hub routing circuit 39, including mixing audio signals from multiple inputs into a single output, and for providing signal processing functions. These signal processing functions may include some or all of the following: speaker enhancements such as multi-band compression (multi-band compression), virtual surround sound (stereo extension), or non-linearities that compensate for speaker or device performance; speech (voice) path enhancement such as adaptive ambient noise cancellation, speech (speech) intelligibility enhancement, transmit noise cancellation, echo cancellation or side tone (sidetone) and wind noise filtering; or digital mixing functions such as, for example, fully flexible signal routing, volume control and soft noise suppression, equalization, dynamic range control, programmable filtering, and sample rate conversion.

The audio hub routing circuit 39 has several digital audio interfaces 52.1, … …, 52.N which are intended to be connected to other circuits within the apparatus and to supply signals to or from the digital mixing core 50. The number of digital audio interfaces may be selected during the design of the audio hub based on its intended range of use. In this embodiment of the invention, optimized for a device such as a smartphone, there are: a first digital audio interface, which is primarily intended for connection to the application processor 33; a second digital audio interface, which is primarily intended for connection to the baseband processor 31; and a third digital audio interface, which is primarily intended for connection to the wireless transceiver 37. The digital audio interfaces 52.1, … …, 52.N may be interchangeable, but one interface may advantageously be made significantly wider than the other interfaces so that it can be connected to one of the processors that is expected to need maximum simultaneous access to the routing circuit.

In one embodiment of the invention, optimized for use with devices such as digital cameras (digital still cameras), there may be only one digital audio interface; in an embodiment of the invention optimized for devices such as simple phones (simplex phones), where the radio transceiver function may not be required, or may be performed by, for example, a baseband processor, there may be only two digital audio interfaces (as shown in fig. 2 b). An embodiment may also lack a digital audio interface. In contrast, in one embodiment of the invention intended for a home cinema surround sound apparatus, there may be, for example, six or more digital audio interfaces. The term "audio interface" should also be understood to cover, for example, interfaces for carrying other similar data streams, such as ultrasound or haptic data.

The audio hub routing circuit 39 also has preconditioning circuitry 54 for receiving an analog input signal, for example from an analog input transducer (such as a microphone) 56, and an analog FM radio receiver 58. For these digital interfaces, the number of analog inputs may be selected during design of the audio hub based on the intended range of use of routing circuitry, and one embodiment may not have an analog interface.

One or more analog input transducers may be in the form of a touch screen which may receive inputs, for example from a user of the device, and communicate those inputs to a processor of the device via one of the digital audio interfaces so that the processor may generate control signals for one or more operating characteristics of the device.

Signals from the preconditioning circuitry 54 are communicated to switching circuitry 60, and the switching circuitry 60 also receives digital input signals, for example from a digital input transducer (such as a digital microphone) 62.

Switching circuitry 60 is connected to downsampling circuitry 64, and the downsampled signal from downsampling circuitry 64 is supplied to digital mixing kernel 50, which digital mixing kernel 50 is described in more detail below.

The output signals from digital mixing kernel 50 are passed to up-sampling circuitry 66 and some of the up-sampled signals are passed to post-conditioning circuitry 68, which post-conditioning circuitry 68 is connected to output terminals to which an analog output transducer (such as a loudspeaker) 70 may be connected.

Other signals extracted from the up-sampling circuitry 66 are also passed to a digital output formatting block 72 for connection to a suitable transducer 74, such as a digital input amplifier connected to a remote loudspeaker. For example, the digital output formatting block 72 may be capable of converting these signals into a Stereo Pulse Density Modulation (SPDM) format.

As before, the number of analog and/or digital outputs may be designed based on the intended range of use of the routing circuit, and one embodiment may not have an analog or digital output interface. These analog outputs may be paired for stereo output or may be used individually. Different analog outputs are optimized for different purposes, such as for the load of a speaker used in a headphone or in a speaker box (speaker box), and for e.g. a grounded or differential (H-bridge) speaker load.

The audio hub routing circuit 39 of this particular embodiment also includes a low latency processing block 90 connected to receive the digital signal directly from the output of the switching circuitry 60 and to pass the output signal from the up-sampling circuitry 66 to the output line via adders 92.1, … … 92. P. Low-latency processing block 90 may be adapted to provide specific signal processing functions for signals that should not be subject to any unnecessary delay (i.e., any additional delay caused by digital mixing core 50, no matter how small the delay is). In this illustrated embodiment, the low-latency processing block 90 contains digital filters, which may be adaptive, for use in a feed-forward noise cancellation system. In this embodiment, since the input signals are extracted before the downsampling block, the sampling rate of the data stream and the associated signal processing is done at a much higher sampling rate than the signal processing in the digital mixer core (e.g., 8 times or even 64 times the typical 48kHz sampling rate, i.e., 384kHz or 3.072MHz), so that low latency can be more easily achieved.

That is, one or more microphones may be used to generate a signal representative of ambient noise in the area of the device (e.g., in a handset or in a headset). These signals are filtered to generate output signals that can be transmitted to one or more speakers (typically in the same handset or headset) so that these signals produce sound equal in amplitude but opposite in phase (and thus have a canceling effect) to the ambient noise. For this type of system to work optimally, the time taken for the signal processing should be substantially equal to the time taken for the sound waves to travel through the device, so it can be seen that any latency in the signal processing will have an effect on how optimally the system works.

In this embodiment, there is a connection between digital mixing kernel 50 and low-latency processing block 90, for example, such that the adaptive filter in low-latency processing block 90 (e.g., for use in a feed-forward noise cancellation system) can be controlled from digital mixing kernel 50, based on the results of the signal processing by digital mixing kernel 50.

The audio hub routing circuit 39 also contains a control interface 100 for receiving control signals, for example, from a processor integrated circuit (typically the application processor 33) located in the device. These control signals may, for example, inform the routing circuit 39 of the operational status of the device as a whole, e.g. which functions are active.

The audio hub routing circuit 39 also includes a clock generator 80 for receiving a master clock signal and generating a system clock, as described in more detail below. In this illustrated embodiment, clock generator 80 receives a Q master clock signal and generates an R system clock. For example, in the case of a smart phone, a master clock signal at a frequency of 13MHz may be available whenever circuitry associated with the phone is activated, but when circuitry associated with the phone is not activated (as in, for example, a "flight safety mode"), the 13MHz clock may be unavailable and the only available clock may be a 32kHz crystal.

The digital signals output from the upsampling circuitry 66 are also passed to a multiplexer 84, which multiplexer 84 may select one or more of these output signals to be fed back as inputs to the digital mixing kernel 50. The fed back signal may be used for echo cancellation, for example.

Fig. 4 is a more detailed block diagram of the preconditioning circuitry 54 in the audio hub routing circuit 39 of this embodiment.

As described above, the preconditioning circuitry 54 has several inputs for receiving analog input signals, such as from an analog input transducer 56, fm receiver circuitry 58, or the like. Each of these inputs is connected to a respective preconditioning block 138, including an amplifier 140, wherein the resulting amplified signal is passed to a respective analog-to-digital converter (ADC) 142. The analog-to-digital converter 142 in this illustrated embodiment is an over-sampling ADC, such as a delta-sigma ADC. The gain of each amplifier 140 can be independently controlled by writing the appropriate values to the registers on the chip.

Fig. 5 is a more detailed block diagram of the switching circuitry 60 of the audio hub routing circuit 39 of this embodiment. The switching circuitry receives preconditioned signals, which are digitized versions of the analog input signals, from preconditioning circuitry 54. Each preconditioned signal is delivered to a first input of a multiplexer 160, and a second input of each multiplexer 160 is connected to receive a respective digital input signal received from the digital input transducer 62.

External components are then typically connected to the routing circuitry 39 so that, for use in a given device, or at least at any one time, each multiplexer receives signals from only one of the analog inputs or from one of the digital inputs, but preferably not both. Depending on whether the input signal to the audio hub routing circuit 39 is analog or digital or a mixture of the two, the multiplexer 160 may be controlled so that the appropriate signal is selected as the switched digital output signal.

Fig. 5 shows an embodiment in which the number of connections for the digital input transducer 62 is the same as the number of connections for the analog input signals (e.g., M), so there are M multiplexers 160, each multiplexer 160 receiving a signal from one of the analog inputs and a signal from one of the digital inputs.

Fig. 6 is a more detailed block diagram showing an alternative form of switching circuitry 60 in the audio hub routing circuit 39. As in fig. 5, each digitized version of these analog input signals is passed to a first input of a respective multiplexer 160.

In this case, the combined digital input signal, which is M-bit wide, is passed to a number of M-bit multiplexers 164, the output of a respective one of said multiplexers 164 being connected to a second input of each switch 160. Multiplexers 164 are controlled so that they select a respective one of the bits of the combined digital input signal, and switches 160 are controlled as described above to select either the digitized version of the analog input signal or the digital input signal as the output signal of switching circuitry 60.

Although illustrated as a single wired data stream, the input digital or digitized data stream may be multi-bit, either as a parallel bus or a serial multi-bit data stream, and may be time-multiplexed (time-multiplexed) on a single bus with subsequent adjustment to the structure of the multiplexer blocks.

Fig. 7 is a more detailed block diagram showing one possible form of down-sampling circuitry 64 in the audio hub routing circuit 39.

Each signal output from switching circuitry 60 is passed to a respective down sampler 170 to generate a respective down sampled signal. The down sampler 170 may, for example, include a digital filter, such as an FIR filter or an IIR filter having different input and output sample rates.

Here, as described above, analog-to-digital converter 142 is an oversampling ADC and down-sampler 170 may convert these digital signals to a lower sampling rate that may be conveniently processed by signal processing circuitry in digital mixing kernel 50, albeit with a larger bit width for avoiding increased quantization noise.

Fig. 8 is a more detailed block diagram showing one possible form of upsampling circuitry 66 in the audio hub routing circuit 39.

Each signal output from the digital mixing kernel 50 is passed to a respective upsampler 180 to generate a respective upsampled signal. The upsampler 180 may, for example, take the form of a digital filter, such as an FIR filter or an IIR filter.

Fig. 9 is a more detailed block diagram of the post-conditioning circuitry 68 in the audio hub routing circuit 39.

The post conditioning circuitry 68 has several inputs, each for one of the up sampled signals generated by the up sampling circuitry 66, and each input is connected to a respective post conditioning block 188.

Each post-conditioning block 188 includes a respective digital-to-analog converter 190, and the resulting analog signal is passed to a corresponding amplifier 192, and the resulting amplified signal is the output. The amplifiers 192 may provide single-ended (single-ended) outputs (as shown in fig. 9) or differential outputs, and they may be any convenient type of amplifier, such as a class a/B, class D or class G amplifiers, high power amplifiers, or high voltage amplifiers.

Fig. 10 is yet another schematic diagram of the audio hub routing circuit 39, in this case showing the first and nth digital audio interfaces 52.1, 52.N, but only showing the pre-conditioning circuitry 54, switching circuitry 60, down-sampling circuitry 64, up-sampling circuitry 66, post-conditioning circuitry 68, and digital output formatting block 72 in general, and showing more detail of the digital mixing kernel 50.

Specifically, digital mixing core 50 contains a plurality of digital signal processing blocks, of which a first digital signal processing block (DSP1)102 and an Nth digital signal processing block (DSPN)112 are shown. The digital signal processing blocks 102, 112 may be programmed in a first instance (isolation) or by downloading DSP code stored on-chip or off-chip to perform a wide variety of signal processing functions, but they may be optimized for performing specific functions. For example, each programmable digital signal processing block may have many or many types of memory or dedicated computing hardware that allow it to perform specific functions, or may have a particular set of instructions optimized for the intended function. The number of such programmable digital signal processing blocks and their specific characteristics may be selected depending on the intended range of use of audio hub 39. In one embodiment, one possible intended use of the audio hub routing circuit 39 is in a smart phone, a first programmable digital signal processing block may be used to process voice signals in the transmit path of the phone, a second programmable digital signal processing block may be used to process voice signals in the receive path of the phone, and a third programmable digital signal processing block may be used to process non-voice signals.

In addition, signal processing blocks optimized for a more limited range of functions may be provided. In this illustrated embodiment, digital mixing core 50 also includes fully programmable five-band equalizers, of which two

such equalizers

118, 120 are shown, and digital mixing core 50 also includes filters that are fully programmable so that they may have high-pass and/or low-pass functionality, and one of such filters 134 is shown in FIG. 10.

The digital mixing kernel 50 also includes a Dynamic Range Compression (DRC) block 150. Also shown in fig. 10 is another functional block 154 that may have some other signal processing functionality.

In addition, the audio processing engine 50 includes an upsampling block 162 and a downsampling block 164 for moving between domains having signals at different sample rates. For example, the upsampling block 162 and the downsampling block 164 comprise: a respective Sample Rate Conversion (SRC) block for converting between a speech processing domain having a sample rate of 8kHz or 16kHz and a more general audio processing domain of 48 kHz; and an SRC block for converting between other integer ratios; and an additional SRC block for converting between asynchronous sample rates.

Although not shown in fig. 10, one possibility is to provide a functional block in the form of a tone generator that outputs an audio or tactile signal having predetermined characteristics, without requiring any input audio signal. Similarly, although not shown in fig. 10, yet another possibility is to provide a functional block requiring an audio input but not providing an audio output, e.g. a block containing a rarely updated asynchronous control signal for use by another block, such as a signal level threshold detection signal for noise suppressing other audio paths or for disabling ambient noise cancellation when there is little ambient noise.

A plurality of functional blocks in digital mixing kernel 50 are thus provided, as well as signal inputs to digital mixing kernel 50 and signal outputs from digital mixing kernel 50. These are interconnected by a mixing fabric of the digital mixing core 50, as described in more detail below.

From the perspective of the mixing means, each signal input to digital mixing core 50, and each output from one of these functional blocks, represents a signal source port. In fig. 10, each of these signal source ports is represented by a solid black circle.

Also, from the perspective of the mixing means, each signal output from digital mixing core 50, and each input to one of these functional blocks, represents a signal destination port. In fig. 10, each of these signal destination ports is represented by a solid black diamond.

Thus, it can be seen in FIG. 10 that some function blocks have one input, while other function blocks have multiple inputs. For example, the equalizer 120 has one input 122, while the DSP 1102 has at least four

inputs

104, 106, 108, 110. This means that the DSP1 is capable of processing at least four separate input data streams.

Although described as a single port, these source ports and these destination ports may be multi-bit, handle parallel (e.g., 16-bit or 24-bit) or serial multi-bit data streams, and may be time multiplexed over a single connection.

Furthermore, the mixing means is such that each signal destination port (i.e. an input for any functional block or a signal output from the digital mixing core 50) is associated with a mixing "channel" comprising a predetermined number of "selector ports", each of which may be configured to receive signal data from a selectable signal source port. The channel or mixer elements are illustrated in fig. 11-13 as interfacing with respective signal destination ports, with each of the selector ports represented by a solid black square.

Some channels may simply pass unchanged data to respective destination ports, but the mixing means is such that at least some of the channel output data signal streams may be derived from a mix of signals from signal sources (which may have been scaled by different respective scaling factors). This mixing operation performed by a given channel may be different in different applications or different use cases of the audio hub.

Fig. 11-13 illustrate embodiments of channels or mixer elements of the mixing means (shown shaded) attached to signal destinations on a plurality of functional blocks. Each mixer element includes one or more selector ports, each of which may be attached to a single selected signal source as described below.

Fig. 11 shows the case where the function block 170 has one input (destination port from the perspective of the mixing means) 171. Fig. 11(a) shows that this input 171 may receive signals from one signal source on one selector port 172, and fig. 11(b) shows a more detailed view of the same channel structure, where the signal from the one signal source may be scaled before being applied to input 171.

Fig. 12 shows the case where the function block 174 has two

inputs

175, 176 and two corresponding channel or mixer elements. Fig. 12(a) shows that input 175 may receive signals from two signal sources on

selector ports

177, 178, respectively, and input 176 may receive signals from two signal sources on

selector ports

179, 180, respectively, and fig. 12(b) shows a more detailed view of the same channel structure, where the signals from the two

selector ports

177, 178 may be scaled and added together before being applied to input 175, and the signals from the two

selector ports

179, 180 may be scaled and added together before being applied to input 176.

Fig. 13 shows a situation where the function block 181 has one input 182. Fig. 13(a) shows that the input 182 may receive signals from four

signal sources

183, 184, 185, 186, and fig. 13(b) shows a more detailed view of the same channel structure, where the signals from these four

signal sources

183, 184, 185, 186 may be scaled and added together before being applied to the input 182.

Thus, fig. 14 is a somewhat more detailed version of fig. 10, showing a channel having multiple selector ports docked at respective destination ports (block inputs) of each signal destination (i.e., function block and signal output from the mixing kernel).

For example, the input 122 of the equalizer 120 can receive signals from four signal sources on

respective selector ports

188, 189, 190, 191; and the input 104 of the DSP 1102 is capable of receiving signals from three signal sources on

respective selector ports

192, 193, 194; the input 106 of the DSP 1102 is capable of receiving signals from two signal sources on

respective selector ports

195, 196; the input 108 of the DSP 1102 is capable of receiving a signal from a signal source on the selector port 197; and the input 110 of the DSP 1102 can receive a signal from a signal source on the selector port 198.

As mentioned above, the mixing means allows signals from any selected signal source to be routed to these signal destinations, but combined where a single signal destination is required to receive a mix of signals from multiple signal sources. That is, the mixing means allows a user to select which signal sources are to be connected to which signal destinations based on any one of the criteria imposed by the user's selection, without the limitations imposed by the mixing means itself.

The mixing means as shown in fig. 14 may be physically implemented using separate adders and multipliers for each signal destination on each functional block as shown. However, in terms of silicon real estate, power and control function convergence, it is highly advantageous to implement the mixing means as a single mixer circuit (or possibly, for more complex systems, as several such mixer circuits, where the number of mixer circuits is still much smaller than the number of signal destinations), and time-multiplex this circuit between the multiple destinations such that it in turn serves the requirements of each required signal destination within each audio signal sampling period.

Whereby the mixing means comprises a mixer (or mixers) which is shared between the signal sources and destinations on a time division multiplex basis. That is, the same mixer can route data from many signal sources (or groups of signal sources) to corresponding signal destinations within one data sample period. However, the clock frequency of the mixer block is less than the clock frequency required to be able to establish a signal path between each signal source and each signal destination during one data sampling period. Thus, the mixing block does not simply cycle through all possible signal paths. When present at a particular mixer clock frequency C_RA single mixer operating and present as a group availableSampling rate S of_R,iA number of signal sources N operating at the ith sampling rate_s,iAnd signal destination N_d,iWhen, C_RMuch smaller than the product S obtained over all values of i_R,i·N_d,i·N_s,iThe sum of (a) and (b). When there are m such mixer clock frequencies C_RRunning mixer, product m.C_RMuch smaller than the product S obtained over all values of i_R,i·N_d,i·N_s,iThe sum of (a) and (b). When there are multiple mixer clock frequencies C_R,jAnd m_jAt the jth mixer clock frequency C_R,jProduct m obtained at all values of j for a running mixer_j·C_R,jIs much smaller than the product S obtained over all values of i_R,i·N_d,i·N_s,iThe sum of (a) and (b). The routing may be configurable by a user of the audio hub circuit and may furthermore be reconfigurable in use to provide different functionality in different situations.

Fig. 15 is a block diagram illustrating the general form of the digital mixing kernel 50 of the audio codec 39 of fig. 3, emphasizing the mixing means rather than the functional blocks.

Fig. 15 shows a single block 200, generally representative of a set of multiple functional blocks, i.e., signal processing blocks 200.1, … …, 200.N in digital mixing kernel 50. Fig. 15 also shows an input 214 at which the signal is introduced into mixing kernel 50, and an output 216 at which the signal is extracted from mixing kernel 39. (it will be appreciated from the description of FIG. 10 above that a typical circuit will contain multiple inputs and outputs, so that for ease of illustration, inputs 214 and outputs 216 represent those multiple inputs and outputs.)

Thus, functional block 200 may serve as a signal source providing a signal source port and input 214 may also serve as a signal source providing a signal source port, while functional block 200 may also serve as a signal destination providing a signal destination port and output 216 may also serve as a signal destination providing a signal destination port. The signal processing block serves as a signal destination when receiving a signal to be processed and as a signal source when transmitting the processed signal to an output or subsequent functional block.

Each signal source port associated with one of these functional blocks has a respective source buffer 202.1, … …, 202.N associated therewith, and the signal source port associated with the input 214 has a source buffer 202.P associated therewith. Each of these source buffers 202.1, … …, 202.N, 202.P is connected to a mixer 206 through a source selector block. In this illustrated embodiment, the source selector block takes the form of a bus 204, the bus 204 allowing the mixer 206 to extract data from respective source buffers associated with any of these signal sources.

The output data from the mixer 206 passes through the destination selector block and is transferred to a respective destination buffer 210.1, … …, 210.N, 210.Q associated with a respective one of the signal destination ports. In particular, each destination buffer 210.1, … …, 210.N is associated with a respective signal destination port on one of the functional blocks 200.1, … …. N, and the destination buffer 210.Q is associated with a signal destination port on the output 216. In this illustrated embodiment, the destination selector block takes the form of a bus 208, the bus 208 allowing the mixer 206 to transfer data to the respective destination buffers associated with any of these signal destination ports.

The source buffers 202.1, … …, 202.N and the destination buffers 210.1, … …, 210.N may be physically located adjacent to the respective functional blocks 200, or adjacent to the mixer 206, or at any convenient location, as determined during the design of the routing circuit 39. Similarly, the buffer 202.P may be located close to the signal input of interest or close to the mixer 206, and the buffer 210.Q may be located close to the signal output of interest or close to the mixer 206.

Furthermore, the design of the circuitry connected to input 214 or output 216 may mean that no buffers need to be provided within digital mixing core 50. For example, the output register of a down-sampler connected to input 214, or the input register of an up-sampler connected to output 216 may already provide suitable buffering. In other words, some source buffers or destination buffers may be provided outside the digital mixing kernel.

In this illustrated embodiment, the

buses

204, 208 are separate, allowing the mixer to read data from one of the buffers 202.1, … …, 202.N, 202.P and simultaneously write data to one of the buffers 210.1, … …, 210.N, 210. Q. In an alternative embodiment, a single bus may be used for this purpose, with a bus arbitration scheme to ensure that the mixer 206 does not attempt to read data from one of the buffers 202.1, … …, 202.N, 202.P and write data to one of the buffers 210.1, … …, 210.N, 210.Q at exactly the same time. However, the separation of the input bus and the output bus is advantageous in the following respects: making it easier to avoid timing conflicts between inputs and outputs and to avoid having to share the bandwidth of the bus.

In this illustrated embodiment, there is a single mixer 206 that serves all of these signal destinations.

Fig. 16 is a block diagram illustrating an alternative general form of digital mixing kernel 50 in routing circuit 39 of fig. 3.

As in fig. 15, fig. 16 shows a single block 200, generally representative of a plurality of functional blocks, i.e., signal processing blocks 200.1, … …, 200.N in digital mixing kernel 50. Fig. 16 also shows an input 214 at which the signal is introduced into mixing kernel 50 and an output 216 at which the signal is extracted from mixing kernel 39.

As in fig. 15, each functional block capable of acting as a signal source has a respective buffer 202.1, … …, 202.N, 202.P associated therewith. In this embodiment, the source selector includes a first source bus 220 and a second source bus 222. Each of the first source bus 220 and the second source bus 222 is connected to each of the buffers 202.1, … …, 202.N, 202.P so that it can receive signals therefrom. The first source bus 220 is connected to a first mixer 224 and the second source bus 222 is connected to a second mixer 226. Thus, the first source bus 220 allows the first mixer 224 to extract data from the respective buffers associated with any of these signal sources, and the second source bus 222 similarly allows the second mixer 226 to extract data from the respective buffers associated with any of these signal sources.

The output data from each

mixer

224, 226 is transferred through the destination selector to a respective buffer 210.1, … …, 210.N, 210.Q, wherein each buffer 210.1, … …, 210.N, 210.Q is associated with a respective one of the signal destinations. In this embodiment, the destination selector block includes a multiplexer 228 and a bus 230. Multiplexer 228 determines which of first mixer 224 and second mixer 226 can transfer output data to bus 230 at any one time for transfer to the respective buffers associated with any of these signal destinations based on applied control signals (not shown). A simple possibility is to have the control signal allow mixer a 224 and mixer B226 to talk to the bus 230 in alternate cycles of a fast processor clock.

Thus, in this embodiment, two

mixers

224, 226 are provided. In fact, any number of mixers may be present to provide the required or desired signal throughput. Typically, a mixer member will have more input signals to be mixed than the destination is to serve, so the input buses will saturate first, so two or more input buses (or any number of input buses less than the number of destinations) and associated multiple mixers can provide a useful increase in mixer member bandwidth, if required.

Fig. 17 is a block diagram illustrating the general form of an alternative digital mixing kernel 50 in routing circuit 39 of fig. 3.

As in fig. 15, fig. 17 shows a single block 200, generally representative of a plurality of functional blocks, namely signal processing blocks 200.1, … …, 200.N in digital mixing kernel 50. Fig. 17 also shows an input 214 at which the signal is introduced into mixing kernel 50 and an output 216 at which the signal is extracted from mixing kernel 39.

Each of the functional blocks capable of acting as signal sources has a respective buffer 202.1, … …, 202.N, 202.P associated therewith. Each of these buffers 202.1, … …, 202.N, 202.P is connected to the mixer 206 via a first source selector. In this illustrated embodiment, the source selector takes the form of a multiplexer 240, which multiplexer 240 may be controlled to allow mixer 206 to extract data from respective buffers associated with any of these signal sources.

The output data from the mixer 206 is passed through the destination selector to a respective buffer 210.1, … …, 210.N, 210. Q. Each buffer 210.1, … …, 210.N, 210.Q is associated with a respective one of the signal destinations. In this illustrated embodiment, the destination selector takes the form of a multiplexer 242, the multiplexer 242 allowing the mixer 206 to transfer data to the respective buffers associated with any of these signal destinations.

Again, in this illustrated embodiment, there is a single mixer 206 that serves all of these signal destinations.

Fig. 18 is a block diagram illustrating yet another alternative overall form of digital mixing kernel 50 in routing circuit 39 of fig. 3.

As before, fig. 18 shows a single block 200, generally representative of a plurality of functional blocks, namely signal processing blocks 200.1, … …, 200.N in digital mixing kernel 50. Fig. 18 also shows an input 214 at which the signal is introduced into mixing kernel 50 and an output 216 at which the signal is extracted from mixing kernel 39.

Each of the functional blocks capable of acting as signal sources has a respective buffer 202.1, … …, 202.N, 202.P associated therewith. Each of these buffers 202.1, … …, 202.N, 202.P is connected to a first source selector.

In this embodiment, the source selector comprises a first multiplexer 248 and a second multiplexer 250, the first multiplexer 248 being connected to a first mixer 252 and the second multiplexer 250 being connected to a second mixer 254. Each

multiplexer

248, 250 is connected to all of the buffers 202.1, … …, 202.N, 202.P, so that the source selector allows each of the

mixers

252, 254 to extract data from the respective buffer associated with any of the signal sources.

The output data from the

mixers

252, 254 is passed through the destination selectors to a respective buffer 210.1, … …, 210.N, 210.Q, each buffer 210.1, … …, 210.N, 210.Q being associated with a respective one of the signal destinations. In this embodiment, the destination selector takes the form of a multiplexer 256 that determines which of the first 252 and second 254 mixers is capable of transmitting output data at any one time, and which of the buffers 210.1, … …, 210.N, 210.Q associated with the signal destinations can receive the data, based on an applied control signal (not shown).

Thus, in this embodiment, two

mixers

252, 254 are provided, and either of them can provide data to any of these signal destinations. In fact, any number of mixers may be present to provide the required or desired signal throughput.

Fig. 19 is a block diagram illustrating yet another alternative overall form of digital mixing kernel 50 in routing circuit 39 of fig. 3. The digital mixing kernel 50 shown in fig. 19 is the same as that shown in fig. 18, except that the destination selector associates each signal destination with one of the

mixers

252, 254.

Thus, the signal destinations are divided into two groups, for example on the basis of: each group will be expected to use an approximately equal share of the total available mixer resources. As shown in fig. 19, one set of destinations contains the output 216 and function blocks 200.1, … …, 200.J, while another set of destinations contains function blocks 200.K, … …, 200. N.

The destination selector then comprises two

multiplexers

256a, 256b, multiplexer 256a being associated with mixer 252 and multiplexer 256b being associated with mixer 254. The output data from the mixer 252 is passed through the multiplexer 256a to a respective buffer 210.1, … …, 210.J, 210.Q, wherein each buffer 210.1, … …, 210.J, 210.Q is associated with a respective one of the signal destinations in the first group. The output data from the mixer 254 is transferred through the multiplexer 256b to a respective buffer 210.K, … …, 210.N, wherein each buffer 210.K, … …, 210.N is associated with a respective one of the signal destinations in the second set.

Fig. 20 is a block diagram showing the form of mixers and buffers and source and destination selectors in the digital mixing kernel 50. In fig. 20, there is one mixer as in fig. 15 and 17. When there is more than one mixer as in fig. 16, 18 and 19, some or all of the mixer structure is replicated.

In fig. 20, the mixer 290 is shown connected to receive input data from buffers 202.1, … …, 202.N, 202.P associated with respective signal sources and to transmit output data to buffers 210.1, … …, 210.N, 210.Q associated with these signal destinations.

The mixer 290 is based on a multiply-accumulate block (MAC)292, the structure of which multiply-accumulate block 292 is described in more detail below. The multiply-accumulate block 292 is time multiplexed between different sources and destinations, again as described below.

The source selector block 294 determines which of these data sources serves as the first data source (MAC input 1) for the multiply-accumulate block 292 at any given moment, and the destination selector block 296 determines which of these data destinations serves as the destination for the data output from the multiply-accumulate block 292 at any given moment.

Based on source input selection signals received from controller 300, and based on information received from register bank 298, source selector block 294 selects a source. Destination selector block 296 selects a destination based on output destination selection signals received from controller 300, and also based on information received from register bank 298. As mentioned above, the source selector block 294 and the destination selector block 296 may take any convenient form, for example they may be in the form of suitably controlled buses or multiplexers.

Register bank 298 also serves as a second data source (MAC input 2) for multiply accumulate block 292. MAC input 2 provides the scaling factor to be applied to the selected data being processed.

Fig. 21 is a block diagram illustrating an alternative form of mixer and associated buffer and selector blocks in digital mixing core 50.

In this embodiment, the mixer 310 includes a multiply-accumulate block 292 and is connected to a source selector block 294 and a destination selector block 296, which are identical to the source selector block 294 and the destination selector block 296 shown in FIG. 15.

In the embodiment shown in fig. 21, the register bank 312 and the controller 314 have substantially the same function as the corresponding components of the mixer 290 shown in fig. 20, but are not considered part of the mixer. Instead, a memory 316 within the mixer 310 stores data received from the register bank 312 and, based on the data received from the register bank 312, supplies source input selection signals to the source selector bank 294 and output destination selection signals to the destination selector bank 296.

Fig. 22 is a block diagram illustrating one possible form of multiply-accumulate block in the mixer of fig. 20 or 21.

In fig. 22, a multiply-accumulate (MAC) block 292 is shown that receives data from a first source (MAC input 1) and data from a second source (MAC input 2) as inputs to multiplier 330. The output of multiplier 330 is applied as an input to adder 332 and the output of adder 332 is in turn applied to register 334, the output of adder 332 acting as a one clock period delay element based on a clock signal received by register 334. The output of the register 334 is provided as one output of the multiply accumulate block 292 and is also fed back to the second input of the adder 332.

(As an alternative, the output of adder 332 may be taken as the output of the MAC block.)

Thus, during one clock cycle, multiply-accumulate block 292 receives data from a first source (MAC IN 1), multiplies this data value by a multiplication coefficient in the form of data from a second source (MAC IN 2), and adds the result to the previously received sum value. This may be allowed to continue for several clock cycles such that the output of multiply-accumulate block 292 represents the sum of several data values received from the first source, each data value being scaled by a respective multiplication coefficient. When the desired sum value has been calculated and the output has been buffered in the intended destination buffer 210, the value stored in the register 334 may be cleared. Alternatively, the value may simply be left over and overwritten by the next partial sum value by disabling the adder for the next first received data.

Fig. 23 is a block diagram illustrating an alternative form of multiply-accumulate block in the mixer of fig. 20 or 21.

The multiply-accumulate block 292 shown in fig. 23 is the same as that shown in fig. 22, except that the output of the register 334 is transferred to one input of the controllable multiplexer 336. The other input of multiplexer 336 is connected to an input of multiply-accumulate block 292 through bypass path 338. This means that the bypass path input of multiplexer 336 can be selected and connected to the output of multiply-accumulate block 292 when the required output data is simply input data from the first source (MAC input 1) without any scaling or mixing with other data values.

Fig. 24 is a flowchart, fig. 25 is an overview, and fig. 26 is a timing chart illustrating the operation of the mixer illustrated in fig. 20 or 21.

Fig. 26 shows a relatively high speed clock DCK and a relatively low speed clock SCK. The frequency of the lower speed clock SCK is the sampling rate of the audio data stream, determining the rate at which this data needs to be processed. For example, voice processing for a telephone call may require data to be generated at a frequency of 8kHz, while other audio data processing applications may require data to be generated at a frequency of 48 kHz. In this illustrated embodiment, only the leading edge (leading edge) of each clock cycle is used, so it does not matter that the SCK is not shown as having a 50% duty cycle.

This high speed clock DCK determines the speed at which the multiply-accumulate block 292 operates, i.e., the speed at which the MAC cycles through the multiple inputs. It is noted that a typical value of the data clock DCK may be e.g. 48MHz, which may be e.g. 1000 times the sample rate clock SCK for typical processing. Thus, fig. 26 is not to scale, but illustrates the required processing.

Fig. 24, 25 and 26 illustrate the operation of the mixer 290 in the case where data from two sources is to be mixed together and applied to the output. During a first cycle of the sampling clock signal SCK, or during a first time interval T1 (or any earlier time interval), a first process (process a) is performed by one of the functional blocks 200.a (or equivalently, data is received at the input of the digital mixing kernel), and this produces a first data value (step 450 in fig. 24) which is available, i.e. stored, in the data source buffer 202.a associated with that data source within the first time interval T1. The first data value is stored in the data source buffer 202.a (step 452 in fig. 24) so that it is available to the mixer 290 throughout the next sampling clock cycle (or second time interval) T2.

Fig. 25 and 26 show the partitioning of the buffer 202.a, such that data is written to the first half 202.a1 of the buffer 202.a at some time in the first time interval T1, and data is transferred to the second half 202.a2 of the buffer 202.a at the end of the first time interval T1, such that data can be accessed by the mixer 290 from the second half 202.a2 of the buffer 202.a at any time throughout the second time interval T2.

During the same first time interval T1 (or any earlier time interval), a second process (process B) is performed by one of the functional blocks 200.B (or equivalently, data is received at the input of the digital mixing kernel) and this produces a second data value (step 454 in fig. 24) which is available in the data source buffer 202.B associated with that data source. The second data value is stored in the data source buffer 202.B (step 456 in fig. 24) so that it is available to the mixer 290 over the next sampling clock period T2. Fig. 25 and 26 show the partitioning (partioning) of the buffer 202.B in the same way as the buffer 202.a described above.

At a point in time T2a during the sampling clock period T2, the multiply-accumulate block 292 is caused to obtain data from the buffer 202.a2 at the first input (MAC input 1), so it obtains a first data sample at the rising edge (rising edge) of the data clock DCK (step 458 in fig. 24). (the data transform may be timed to occur on the falling edge of the data clock DCK as appropriate.) during the clock period of the data clock DCK between periods t2a and t2b, this first data sample is scaled (represented by "x" 350) by being multiplied in multiplier 350 by the multiplication coefficient obtained at the second input (MAC input 2) (step 460 in fig. 24). The result of this scaling is stored in register 334 of fig. 22.

At a point in time t2B after that clock period between t2a and t2B of the data clock DCK, the multiply-accumulate block 292 is caused to obtain data from the buffer 202.B2 at the first input (MAC input 1), so it samples the second data value (step 462 in fig. 24). During the clock period of the data clock DCK between periods t2b and t2c, the data values of the second sample are scaled (represented by "x" 352) by being multiplied in the same multiplier 350 by a second scaling factor (step 464 in fig. 24) obtained at the second input (MAC input 2). The result of this scaling is added (represented by "+" 354) to the scaled result of the first data sample (step 466 in fig. 24).

The result of this addition is stored in the first half 210.Z1 of the output buffer 210.Z associated with the data destination intended to receive the output data, i.e., the functional block (or the output of the digital mixing kernel) 200.Z (step 468 in fig. 24). As before, fig. 25 and 26 show the division of the buffer 210.Z such that data is written to the first half 210.Z1 of the buffer 210.Z during a second time interval T2, and then transferred to the second half 210.Z2 of the buffer 210.Z, where data retention is available until the end of the next sampling clock period T3.

At any time T3a during the sampling clock period T3, the output data is sampled by functional block 200.Z, which serves as the data destination (step 470 in fig. 24), which may then be processed by functional block 200.Z in subsequent processing (step 472 in fig. 24). Of course, if the data destination is the output of the digital mixing kernel, the resulting data may be output during sampling period T3 (step 474 in fig. 24).

Thus, multiply-accumulate block 292 generates the required data such that this required data is available to the block intended to receive it at the required time, regardless of the audio sample period. This greatly simplifies the timing considerations required in configuring the digital mixer core. That is, the arrangement of the source buffer and destination buffer means that, knowing that the data demanded by multiply-accumulate block 292 from a data source will be available over one sample period, the operation of multiply-accumulate block 292 may be scheduled (such that the scheduling need not take into account the exact point in time that the data will become available within that sample period), and knowing that the data supplied by multiply-accumulate block 292 to a data destination will be available over another sample period, the operation of multiply-accumulate block 292 may be scheduled (such that the scheduling need not take into account the exact point in time that the data will be demanded within that sample period).

In other words, data presented at the source port at the beginning of one sample period will be available for destination block processing over the next entire sample period. The latency of each stage in the signal processing chain is thus a fixed two sample period, one for the mixer and one for the processing, provided that the destination block can complete its run in the next sample period. This greatly simplifies the latency calculation for the signal chain.

This latency is also independent of the clock used to clock the mixer (and clock the functional blocks), which makes any clock frequency scaling invisible to the audio signal path.

If additional latency is required in some paths, for example to match the latency introduced by the extended processing in the parallel path, the mixer output may be fed back to its input via a signal processing block comprising simple registers, repeatedly if necessary.

As described above, fig. 26 is an exemplary timing diagram (not to scale) showing one data sample from a first data source (process a) being combined with one data sample from a second data source (process B) to generate one result sample, which is provided to a data destination (process Z).

Of course, most of the real processes require this operation to be repeatedly performed once every sampling period, and fig. 27 is still another timing chart showing this repetition.

Thus, in fig. 27, as in fig. 26:

in the sampling clock period T1,

data from process a (e.g. functional block 200.a) is stored in buffer 202.a1,

data from process B (e.g., functional block 200.B) is stored in buffer 202. B1;

at the beginning of the sampling clock period T2,

the data stored in the buffer 202.a1 is transferred to the buffer 202.a2,

the data stored in the buffer 202.B1 is transferred to the buffer 202. B2;

during the sampling clock period T2,

the data from the buffers 202.A2 and 202.B2 are mixed with the results stored in the buffer 210.Z1 (hybrid 1)

At the beginning of the sampling clock period T3,

the data stored in the buffer 210.Z1 is transferred to the buffer 210.Z2

During the sampling clock period T3,

the data destination (e.g., function block 200.Z) is made available to the data from buffer 210. Z2.

This process is repeated after one sampling clock cycle. Namely:

in the sampling clock period T2,

data from process a (e.g. functional block 200.a) is stored in buffer 202.a1,

data from process B (e.g., functional block 200.B) is stored in buffer 202. B1;

at the beginning of the sampling clock period T3,

the data stored in the buffer 202.a1 is transferred to the buffer 202.a2,

the data stored in the buffer 202.B1 is transferred to the buffer 202. B2;

during the sampling clock period T3,

data from buffers 202.a2 and 202.B2 are mixed with the results stored in buffer 210.Z1 (mix 2);

at the beginning of the sampling clock period T4,

the data stored in the buffer 210.Z1 is transferred to the buffer 210.Z2

During the sampling clock period T4,

Thus, the process is repeated in each sampling clock cycle and the data destination is enabled to obtain output data samples at the required sampling rate.

As described above, fig. 27 is an exemplary timing diagram (not to scale) showing that in each sample period, one data sample from the first data source (process a) is combined with one data sample from the second data source (process B) to generate one result sample, which is provided to the data destination (process Z).

An aspect of the embodiments described in fig. 26 and 27 is that the mixer time-multiplexes between multiple data destinations, and fig. 28 is yet another exemplary timing diagram (not to scale) showing this time-multiplexing aspect.

Thus, in fig. 28, as in fig. 26:

in the sampling clock period T1,

data from process a (e.g. functional block 200.a) is stored in buffer 202.a1,

data from process B (e.g., functional block 200.B) is stored in buffer 202. B1;

at the beginning of the sampling clock period T2,

the data stored in the buffer 202.a1 is transferred to the buffer 202.a2,

the data stored in the buffer 202.B1 is transferred to the buffer 202. B2;

during the sampling clock period T2,

at time t2a, the MAC 292 extracts the data from the buffer 202.a2, and scales the data if required,

at time t2B, the MAC 292 extracts the data from the buffer 202.B2, and scales the data if required,

at time t2c, the scaled data are added and the result is stored in buffer 210. Z1.

At the beginning of the sampling clock period T3,

the data stored in the buffer 210.Z1 is transferred to the buffer 210.Z2

During the sampling clock period T3,

at time t3a, the data destination (e.g., function block 200.Z) is made available to the data from buffer 210. Z2.

Time division multiplexing of the mixer means that another process can occur in parallel with this process as long as the operation of the MAC 292 is scheduled to avoid overlap (overlap) between them.

Thus, fig. 28 also shows this parallel operation:

in the sampling clock period T1,

data from process C (e.g. functional block 200.C) is stored in buffer 202.C1,

data from process D (e.g., functional block 200.D) is stored in buffer 202. D1;

at the beginning of the sampling clock period T2,

the data stored in the buffer 202.C1 is transferred to the buffer 202.C2,

the data stored in the buffer 202.D1 is transferred to the buffer 202. D2;

during the sampling clock period T2,

at time t2d, the MAC 292 extracts the data from the buffer 202.C2, and scales the data if required,

at time t2e, the MAC 292 extracts the data from the buffer 202.D2, and scales the data if required,

at time t2f, the scaled data are added and the result is stored in buffer 210. Y1.

At the beginning of the sampling clock period T3,

the data stored in the buffer 210.Y1 is transferred to the buffer 210.Y2

During the sampling clock period T3,

at time t3b, the data destination (e.g., function block 200.Y) is made available for data from buffer 210. Y2.

Where one or more of the data destinations 200.Z, 200.Y shown in fig. 28 are functional blocks in the form of signal processing blocks which will in turn provide data source ports in yet another processing.

26-28 show a system in which each buffer is divided such that data is written to a first portion of the buffer, then transferred to a second portion of the buffer at the beginning of a new sampling clock cycle, and then read from the second portion of the buffer during the new sampling clock cycle. It is also feasible to use a "ping pong" buffer, which is then divided so that data is never transmitted between the two parts of the buffer; alternatively, data may be written to the first portion of the buffer and read from the second portion of the buffer during odd-numbered sampling clock cycles, and may be read from the first portion of the buffer and written to the second portion of the buffer during even-numbered sampling clock cycles.

Fig. 29 is a timing diagram illustrating the use of ping-pong buffers.

Thus, in fig. 29:

in the sampling clock period T1,

data from process a (e.g. functional block 200.a) is written to a first portion of the corresponding buffer 202.a3,

data from process B (e.g., functional block 200.B) is written to a first portion of the corresponding buffer 202. B3;

during the sampling clock period T2,

data is read from the first portion of the buffer 202.A3, and scaled data is read from the first portion of the buffer 202.B3 if required, and scaled if required

The scaled data from 202.A3 and 202.B3 are mixed (mix 1) and the result is stored in the first portion of the buffer 210.Z3

Data from process A (e.g., functional block 200.A) is written to a second portion of the corresponding buffer 202.A4

Data from process B (e.g., functional block 200.B) is written to a second portion of the corresponding buffer 202. B4;

during the sampling clock period T3,

making the data destination (e.g., function block 200.Z) available the data from the first portion of the buffer 210.Z3

Data is read from the second portion of the buffer 202.A4, and scaled data is read from the second portion of the buffer 202.B4 if required, and scaled if required

The scaled data from 202.A4 and 202.B4 are mixed (mix 2), the result being stored in the second portion of the buffer 210.Z4

During the sampling clock period T4,

the data destination (e.g., function block 200.Z) is made available to the data from the second portion of the buffer 210. Z4.

This process is repeated so that the data destination can obtain output data samples at the required sampling rate.

Fig. 30 is a flowchart illustrating a process by which a user can configure a switch circuit according to the present invention. Aspects of the operation of the switching circuit may be configured during the design of the integrated circuit containing the switching circuit and/or during the development of the electronic device containing the integrated circuit containing the switching circuit and/or by the end user who purchased the electronic device. Aspects of the operation that have been configured by the developer of the electronic device may be protected so that the end user cannot change that configuration, or may be left so that the end user can change that configuration. In the following description it is assumed that the user of the invention is the designer of a consumer device in which a plurality of audio signals are to be processed in parallel. In this illustrated embodiment, this configuration process is made as intuitive as possible to the user by allowing the user to define the required functionality of the device. In this illustrated embodiment, this processing is performed when the end product, such as a smart phone, game player, portable media player, or the like, is designed. In this illustrated embodiment, the end product is a smart phone.

In step 500 of the process shown in fig. 30, the user defines the required signal processing by the switching circuit. For example, as shown in fig. 32, the user may be able to generally describe which input signals are available and which output signals he wishes to generate based on which processes these input signals pass through.

Thus, fig. 32 shows that a user wishes to extract input signals 520, 522 from an analog voice microphone at 48k samples/second, down sample each input signal to 8k samples/second, then pass both to the DSP to perform acoustic echo cancellation, and generate an ambient noise cancellation signal for the transmit path. Thus, the signals detected by the microphone in the smartphone are processed before being transmitted via the telephone network.

The processed output signal 524 is applied with gain and the resulting signal 526 is passed to the baseband processor of the smartphone.

The processed output signal 524 will also be up-sampled to 48k samples/second and gain will be applied to the up-sampled signal 528.

Fig. 32 also shows that the user wishes to be able to extract a signal 530 at 8k samples/second (which represents the received voice call sound) and up-sample it from 8k samples/second to 48k samples/second. The user wishes to apply gain to the up-sampled signal 531 and pass the resulting signal 532 to the equalizer function to attenuate the signal at 217Hz and harmonics at multiples thereof. The user then wishes to apply gain to this filtered signal 534 and perform multi-band compression (multi-band compression) on the resulting gain signal 536.

The user then wishes to apply gain to the compressed signal 538 and transmit the resulting signal 540 to the smartphone's microphone via the DAC. Thus, the received voice signal is processed before being played back to the user of the smartphone.

In addition, the user of the present invention, i.e., the designer of the smart phone device, may wish to provide a function whereby both parties to a phone call are recorded. Thus, it may be desirable to apply a (possibly different) gain to the two

signals

528, 538, and in one use case add the two

signals

528, 538 together and pass the resulting signal 542 to the application processor of the smartphone, so that the resulting signal 542 may be recorded in local memory, for example, within the device, or on a storage device that can be inserted into the device.

Returning to FIG. 30, in step 502, these processing operations are mapped to functional blocks available in the digital mixing kernel. For example, in this embodiment, one of the DSPs in the digital mixing kernel, such as DSP # 1102, may be optimized for performing acoustic echo cancellation, while another such as DSP # N112 may be optimized for performing multi-band compression, so these operations are all distributed to the respective DSPs. In addition, one equalizer may be optimized for removing harmonics at multiples of 217Hz, so that operation may be assigned to that particular equalizer 120. If no function block is optimized for the particular function that the user wishes to implement, the relevant operation may be assigned to one of these filters or equalizers or DSPs, which may then be programmed to perform that function.

The overall signal routing is then split into a plurality of component signal paths, each path involving one or more signal sources and one signal destination, and each path requiring access to the mixer components of the digital mixing core.

These operations are then defined to be storable in a register bank 298 associated with the mixer and accessible to the controller 300 (see fig. 20) to cause the operations to be performed as required.

Fig. 33 shows one possible form of the register bank before any operations are defined. Thus, there are a plurality of channel identifiers (identifiers), i.e., channel IDs, each associated with a respective signal destination port in the digital mixing core. As described previously, the functional blocks in the digital mixing core may provide signal destinations (in essence, one more complex functional block, such as a fully programmable digital signal processing block, may provide several independent signal destination ports), and each output from the digital mixing core is a signal destination port.

Each channel ID, i.e. destination port, has a predetermined number of selector ports associated with it. As described above with reference to fig. 11-13, the number of selector ports represents the number of signal sources that may be connected to the signal destination associated with that channel ID during any one sampling clock cycle. Thus, fig. 33 shows that the signal destinations represented by channel IDs (represented by hexadecimal addresses) 0Dh, 0Eh, and 27h each have four selectors associated therewith,

channel IDs

14h and 15h each have one selector associated therewith, and channel ID 57h has two selectors associated therewith, and so on.

In another embodiment, the number of selector ports (i.e., the maximum number of sources) associated with any given channel ID may be fully programmable by a user (i.e., by a designer of a consumer product containing the switch circuit).

Returning to the process shown in fig. 30, it was mentioned above that the required signal routing is split into multiple signal paths, each path involving one or more signal sources and one signal destination, and each path requiring access to the mixer components of the digital mixing core. For each of these signal paths, the relevant signal destination port (and associated channel ID) is identified in step 504. Then, in step 506, one of the selector ports associated with that destination port is selected.

In step 508, the signal source for that selector is identified, and in step 510, a gain value is specified such that the signal from the identified source is scaled (either amplified or reduced) to a desired degree before being transmitted to the signal destination.

In step 512, the source ID and the gain value are stored in the relevant row of the register bank (i.e., the corresponding register address shown in fig. 33), corresponding to the selected selector associated with the signal destination having the appropriate channel ID.

Each channel ID must also have a sampling clock rate associated with it. The sampling clock rate is the rate at which the functional block expects to receive data for processing. For example, operations associated with manipulating voice signals will typically be manipulated with an 8kHz clock, or 16kHz in the case of HD audio, but operations associated with manipulating recorder music will typically be manipulated with a 48kHz clock.

In the embodiment of fig. 33, a single storage location is used to define the sampling clock independently for each channel ID. Other methods of associating a sampling clock with each channel ID are possible and may be preferred in some embodiments. For example, for regularity in the register mapping, at the expense of memory space, it may be preferable to define the sampling clock for each selector port for each channel ID with a separate memory location, but in use, all the sampling clocks for the selectors for each channel ID would have to be the same.

Alternatively, it may be preferable to use a single memory location for all channel IDs (i.e., destination ports) associated with a given signal processing block. In many cases, the internal signal processing in the signal processing block will be adapted to data at only a single sample rate, at least in blocks without sample rate conversion capability.

The sampling rate may be represented by its nominal value, e.g. 8K, 16K or 48K. However, it is more convenient and desirableLess storage may be to define a fixed set of, say, eight sampling clocks and to assign one 3-bit (i.e., 2) to each sampling clock³8) identification codes, such as 000 to 111, and associates a desired sampling clock to each channel ID by storing the appropriate identification code. This may also allow more than one sampling clock to be defined with the same nominal sampling rate. In some applications there may be, for example, two nominal 48kHz clocks, where each clock is derived from a different clock source, for example, from different attached devices. These clocks will always have slightly different frequencies and phases in reality and may require sample rate conversion before combining or other processing.

The minimum information that must be provided in order to define a signal path is thus the or each signal source port, the signal destination port, and the corresponding data sample rate. In this embodiment, a corresponding scaling factor to be applied to the data from the or each signal source port of the signal path may also be stored.

A more specific example will now be given by way of illustration.

Fig. 32 illustrates a series of operations recognized by a user of the present invention, such as a designer of a communication device.

Fig. 34 corresponds to fig. 14 described above, but shows how this signal routing for the desired chain of operations can be split into multiple discrete paths. In fig. 34, each signal source is represented by a solid black circle, each signal destination is represented by a solid black diamond, and each selector associated with one of the signal destinations is associated with a solid black square.

If the microphone in the smartphone handset is connected to the

analog inputs

550, 552 of the audio hub, each of these inputs will receive signals representing the voice of the user of the smartphone, and these signals will pass through the preconditioning circuitry 54, switching circuitry 60, and down-sampling circuitry 64 to the

inputs

554, 556 of the digital mixing kernel.

A path 558 is then defined from the input 554 of the digital mixing kernel to a selector associated with one of the inputs 560 of the downsampling block 164. A second path 562 is defined from the output 564 of the downsampling block 164 to a selector associated with one of the inputs 108 of the first DSP 102, which is selected for this purpose because it can be programmed to perform the required Acoustic Echo Cancellation (AEC) and to send directional Ambient Noise Cancellation (ANC) processing operations on the received speech signal.

Similarly, path 568 is defined from the input 556 of the digital mixing kernel to the downsampling block 164, and path 570 is defined from a corresponding output of the downsampling block 164 to another one of the inputs 110 of the first DSP 102.

A path 572 is defined from the output of the DSP 102 to the nth digital audio interface 52. N. The connection to this particular digital audio interface is because the baseband processor is intended to be connected to this interface.

Voice signals received via the cellular telephone connection are manipulated by the baseband processor such that they are received by the digital mixing core 50 at the nth digital audio interface 52.N and it is first desired to pass these signals through the upsampling block 162 as shown by path 574.

The up-sampled signal is passed to an equalizer 120, the equalizer 120 being configured as a notch filter (notch filter) to remove the residual noise (caused by the characteristics of the GSM cellular system) at 217Hz and its harmonics, as shown by path 576.

This filtered signal is passed to the Nth DSP 112, as shown by path 578. The NDSP 112 may be programmed to provide multi-band compression (MBC). The resulting signal may then be passed to one of the outputs of the digital mixing kernel to which the smartphone speaker is to be connected, as shown by path 580.

To provide the call recording function described with reference to fig. 32 for voice signals in the transmit path of a telephone call, the output of DSP1 is passed to the upsampling block 162 as shown by path 582, and the upsampled signal is passed to a selector 584 associated with one of the signal destinations 586 on the first digital audio interface 52.1 as shown by path segment 588. The connection to this particular digital audio interface is because the application processor (which handles the call recording function and others) is intended to be connected to this interface.

To provide a call recording function for voice signals in the receive path of a telephone call, the output of the Nth DSP 112 is passed to a different selector 590 associated with the same signal destination 586 of the first digital audio interface 52.1, as shown by path segment 592.

Note that the signal path associated with destination port 586 is actually comprised of two path segments, 588 and 592. In general, when multiple signals are routed into one channel, the corresponding signal path will include multiple path segments that converge within the mixed channel. When only one selector is used, the signal path will comprise only one path segment.

It should be appreciated that a user may need to interpret a large number of such use cases. For example, there are standard use cases for manipulating the transmission and reception of speech signals as described above, and use cases in which there is music from a recorded music source, or sound from an associated radio receiver; and there are also use cases where ring tone tones need to be mixed with voice signals, use cases where a wired or wireless handset is connected to a smartphone and the output sound signal needs to be properly directed, among others.

Fig. 35 shows how the paths (or more strictly, path segments) illustrated in fig. 34 are defined in the register map. Note that the reference map for the path segment in fig. 34 is contained in this table for convenience, but does not form part of the register map. Fig. 36 is a schematic representation of a digital mixing kernel in which the components are rearranged to show, on the left hand side of fig. 36, signal sources (i.e. functional blocks of the digital mixing kernel, and signal inputs to the digital mixing kernel), each signal source having one associated input buffer (as indicated by reference numeral 202.x in fig. 15), and each signal destination (i.e. functional blocks of the digital mixing kernel, and signal outputs from the digital mixing kernel) having one associated output buffer (as indicated by reference numeral 210.y in fig. 15). Fig. 36 shows hexadecimal bus addresses of these buffers, and fig. 35 shows channel IDs, the number of selectors, sampling rates, source IDs, and gains for each path described above with reference to fig. 34.

FIG. 35 illustrates the state of a register map at a particular time based on operations required at a time during which the operations as depicted in FIG. 32 need to be performed in a consumer device that includes an audio hub. Typically, these will represent only a small fraction of the total operations that will have been defined by the user (i.e., the designer of the product that includes the audio hub) to take into account all possible uses and states of the product. For example, operations will be defined for when a voice call is active, when music is required to be played, when a key of a keyboard is pressed, and more.

Configuration information for these operations is preferably stored in the memory of the product, said configuration information being accessible when the device is running. For example, the configuration information may be stored in the ROM of the product and downloaded to the audio hub by the application processor when the product is started and the state of the product changes later. This is generally more efficient than storing all this information in the audio hub itself and marking the alternative for an active operation, because it can use a more efficient memory type, and because it means that the audio hub does not need to contain enough memory to store configuration information for an unknown number of use cases. Furthermore, the amount of data to be downloaded when the status of the product changes is relatively small.

The configuration of the routing circuit described above can be simplified for the user by using a suitable graphical configuration program. To enable a user to define a signal path, the user is presented with a functional block diagram 1200 of the switching circuitry, or a functional block diagram 1200 of a mixing kernel as shown in FIG. 31. This may be presented to the user, for example, on a screen 1210 associated with the computer on which the configuration process is running, for example, allowing the user to provide user input using a mouse and/or keyboard or the like to indicate all required use cases. This may include the configuration of other portions of the switching circuit 39, such as any gain applied in the pre-conditioning block or the post-conditioning block. The configuration process may interact with the actual switching circuitry in the application (e.g. in the actual prototype device) or may interact with the emulation of the signal processing to aid debugging (debug).

The screen also contains an area 1220 showing the functional blocks that are available. Thus, FIG. 31 shows a situation where a user has dragged and dropped one representation 1222 of a DSP block into the work area 1200, and area 1220 shows that one of the three available DSP blocks has been dropped. Similarly, equalizer 1224 has been placed and region 1220 shows that one of eight available equalizers has been placed.

The user requests that data from the second digital audio interface 1226 be passed to the equalizer 1224, then to the DSP block 1222, and then to the output 1228.

However, the user interface is also able to recognize that each signal path between functional blocks must have a consistent sampling rate.

However, it is specified that the second digital audio interface 1226 produces data having a sampling rate of 8k samples/second, while the equalizer 1224 operates at 48k samples/second. Thus, the sample rate converter 1230 needs to be included between the second audio interface 1226 and the equalizer 1224. Thus, there are four required paths through the mixer, namely: from the second digital audio interface 1226 to the sample rate converter 1230 at 8k samples/sec; from sample rate converter 1230 to equalizer 1224 at 48k samples/second; from the equalizer 1224 to the DSP block 1222 at 48k samples/second; and 48k samples/second from DSP block 1222 to output 1228.

The sample rate converter 1230 may be added manually by the user, possibly followed by a software check for a consistent sample rate. Alternatively, the configuration software may be intelligent enough to immediately recognize the need for the sample rate converter and automatically insert it once the user attempts to extract the trace from the second interface to the equalizer.

As described herein, the sample rate of the functional blocks and interfaces is specified by the user, thereby allowing the need for sample rate conversion to be inferred by the interfacing software. Reciprocally, these sample rate converters may also be placed by the user, allowing the sample rate of these functional blocks to be inferred by the interface software.

All required use cases can be specified in the same way.

Fig. 32, 34, 35 and 36 above illustrate one use case in which a call recording function is provided.

FIG. 37a illustrates an alternative use case in which Local Voice Mail (Local Voice Mail) is provided^TM) And (4) performing functions. The local voicemail function may be activated if: when a phone user presses a button to convey an incoming voice call to local voicemail; or when the phone user has set the phone so that an incoming voice call is communicated to local voicemail, either automatically upon receipt of the call or when the call remains unanswered after a predetermined number of rings. In either of these events, this use case is activated.

In this use case, the caller is prompted to leave a voice message for the telephone user, and the voice message is stored in the telephone itself, allowing the telephone user to retrieve the message even if no network coverage is available.

In particular, the received voice message is received in the baseband processor of the phone, which in this case is connected to the nth digital audio interface 52. N. A signal path is established through the mixer to the first digital audio interface 52.1, to which the application processor is connected 52.1. Thus, the voice message may be stored in memory that is controlled and accessed by the application processor. Alternatively, a signal path may be established through the mixer to the first digital audio interface 52.1, and a wireless transceiver (i.e. wireless codec) may be connected to the first digital audio interface 52.1. Thus, the voice message may be stored in memory that is controlled and accessed by another device that is wirelessly connected to receive data (i.e., voice messages) from the wireless transceiver.

The signal path through the mixer need not contain any sample rate conversion, since data representing the voice message can be received at the digital audio interface 52.N and transmitted to the digital audio interface 52.1 without any sample rate change from its original sample rate (e.g. 8k samples/sec), even if there is other processing that is manipulated simultaneously at a higher sample rate, for example if a recorded audio signal of a sample rate of 48k samples/sec is passed through the mixer. The signal path through the mixer need not be scaled in any way.

The Local Voicemail (LVM)^TM) The functionality may be provided by an application (i.e., software, commonly referred to as an "app") that is downloadable via the internet for which a user pays a licensing fee.

Alternatively, the digital audio hub may already contain the local voicemail function, i.e., the local voicemail function is already embedded in the digital audio hub at the time of factory shipment, but is in a disabled state. To enable use of the embedded local voicemail, a "key" will be required to unlock the lock that disables the local voicemail. In such a case, the key (i.e. the code in the form of software) is downloaded via the internet where the user pays a license fee.

It is clear that when developing software for local voicemail, the device and the environment in which the local voicemail will be required to function need to be considered. Such considerations are common practice in the prior art for developers of so-called software drivers.

Once installed or enabled, Local Voicemail (LVM)^TM) Activation of (c) may be controlled by the user via a keyboard or touch screen of the device running the local voicemail: such devices are for example mobile phones, smart phones, tablets.

How the local voicemail is activated may be implemented by, for example, selecting a scenario from a drop down menu. Alternatively, the selection may be by means of an icon. The local voicemail menu or icon may represent, for example, that the incoming call is: automatically stored without the phone ringing; after a certain number of rings, if the user does not answer the call, it is stored; or not stored in the local voicemail. Additionally, a menu or icon may represent sending a prerecorded message to the caller prompting the caller to leave a voice message for the telephone user.

When a new local voicemail message is stored in memory, the device may indicate this fact in much the same way as a new non-local voicemail message is indicated to the user by means of an on-screen icon.

The stored local voicemails may be accessed via a menu or icon. In addition, a password may also be required to be entered before the stored local voicemail can be retrieved. The password may be in the form of a sequence of numbers and/or letters, and/or in the case of a touch screen a pattern.

Advantages of local voicemail include: the phone user can get the message in case no network coverage is available; there is no cost (other than a license fee) to the user participating in retrieving the local voicemail message; and reducing traffic of the network associated with retrieving the non-native voice message.

Another advantage of local voicemail is that it is less vulnerable to telephone hacking. A potential "hacker" would need to physically access the device and then, if the device is password protected, the password would need to be obtained to access the stored local voicemail.

There are other use cases where the ability to transfer data from one interface to another without any scaling or sample rate conversion is important to maintain data integrity, especially when the data is encoded in some way. For example, fig. 37b shows the following case: encoded data (which may be compressed or companded) data) received from one processor and intended to be expanded or decompressed (i.e. decoded) by another processor, where any sample rate conversion or scaling of the data would risk changing the content of the encoded data after expansion. Somewhat similarly, data may be received in one protocol format at one interface and passed through the mixer on the direct path to another interface where it may be converted to a different protocol format without sample rate conversion or scaling. Again, the data may be transferred from one interface to another without any sample rate conversion, even when the data is transmitted at a different sample rate on other signal paths.

As mentioned above, on a time division multiplexed basis, the mixer is shared between all active paths at any time. In order to ensure the correct functioning of the plant, it is necessary to properly sequence the operations performed by the mixers.

Assuming Ns signal source ports and Nd signal destination ports, one possibility to order the required connections would be for the destination selector to cycle through the destination ports for Nd DCLK cycles, and for the source selector to cycle through the source ports during each of these sets of Ns DCLK cycles. This takes a total of [ ns.nd ] DCLK cycles. For simplicity, this may be an acceptable implementation for routing circuits with only a small number (e.g., less than 10) of sources and destinations, but is very inefficient for more typical routing circuits with, for example, 50 sources and 50 destinations (which may require 2500 DCLK clock cycles per SCLK period, even when only a few path segments are required to carry a signal).

For arrangements using Nm multiple mixers, such as shown in fig. 19, this can be reduced to [ ns.nd/Nm ], but this is still inefficient in DCLK cycles for small Nm and inefficient in silicon area (silicon area) and power consumption for large Nm. It is unusual for the destination to require a mix of data streams from even four signal source ports, so even cycling through all 50 destinations and allowing up to four selector ports for each channel, the number of DCLK cycles required is greatly reduced (to 4 x 5-200). In the routing circuit shown in fig. 14, many purposes are shown as having only one or two selector ports per channel, which has proven to be efficient. Also, in most use cases, only a few destinations can be used, which further reduces the number of DCLK cycles needed.

Thus, it is advantageous to use control circuitry for the selector that selects only the path segments to be used (as defined in, for example, a register map).

The number of routing operations that can be performed in a fixed period of time depends on the number of mixers and on the ratio of the data clock rate to the data sample rate. The number of routing operations that can theoretically be required depends on the number of source ports and the number of destination ports, and on the sampling rate of the data. In embodiments herein, as described above, the multiplexing of the mixers is such that the number of routing operations that can be performed in a fixed period of time is much less than the number of routing operations that can theoretically be required. For example, the number of routing operations that may be performed in a fixed period of time may be less than a quarter, a tenth, a forty-one, or a one-hundred of the number of routing operations that theoretically may be required.

Fig. 38 is a timing chart illustrating a first possible way of ordering the required series of operations resulting from the use cases described above with reference to fig. 32, 34, 35, and 36.

Thus, there are twelve data routing operations (i.e., path segments), each of which needs to be scheduled regularly, seven of them having a sampling rate of 48k samples/second and the other five having a sampling rate of 8k samples/second. These operations are identified in fig. 38 by their register address, channel ID and source ID, and sample rate.

The clock cycles of data clock DCK are numbered at the top of the table and during each of these clock cycles indicate whether each operation has a pending (pending) calculation or whether that operation has been selected for calculation.

FIG. 38 shows a relatively simple case where the operation with the pending calculation and with the lowest register address is selected for calculation. Thus, by data clock cycle 1, all operations have pending computations, and during data clock cycle 1, the operation at register address 010h is selected for computation. During data clock cycle 2, the operation at register address 010h no longer has pending computations, and the operation at register address 014h is selected for computation, and so on.

The data clock rate needs to be set high enough so that the scheduling method causes the data to be calculated at the required rate for each operation.

This is illustrated with reference to the following figures.

Fig. 39, which is composed of fig. 39(a) and 39(b) on different pages, is a second timing chart illustrating a second possible way of ordering the required series of operations derived from the use examples described above with reference to fig. 32, 34, 35, and 36.

Thus, as in fig. 38, there are the same twelve data routing operations, each of which needs to be scheduled regularly, seven of them having a sampling rate of 48kbps and the other five having a sampling rate of 8 kbps. These operations are identified in fig. 39 by their register address, channel ID and source ID, and sample rate, but in fig. 39, the operations with the same sample rate are combined into groups and they are listed in order of their channel ID within each group.

The clock cycles of data clock DCK are numbered at the top of the table and during each of these clock cycles indicate whether each operation has a pending calculation or whether that operation has been selected for calculation.

Fig. 39 also shows "time to deadline" for each operation, although it is not used by the scheduling method of fig. 39. Thus, each operation must be performed once during each of its corresponding SCK cycles, and the start of fig. 39 is the start of the 8kHz sampling clock and the start of the 48kHz sampling clock. The data clock DCK rate is set such that there are 72 DCK cycles during each cycle of the 8kHz SCK, and thus there must be 12 DCK cycles during each cycle of the 48kHz SCK. (i.e., the data clock rate is set to 576 kHz).

Thus, the "time to deadline" during any given data clock cycle is the number of data clock cycles remaining before the end of that sampling clock cycle (i.e., before the "deadline" at which the data routing operation must be performed). That is, for example, after six DCK cycles, six DCK cycles remain before the end of the 48kHz SCK cycle, and 66 DCK cycles remain before the end of the 8kHz SCK cycle.

FIG. 39 illustrates a scheduling method in which the operation with the pending calculation and with the highest sample rate is selected for the calculation. When there are two or more operations with pending calculations and with the same highest sampling rate, the operation with the lowest channel ID is selected for calculation. When there are two or more operations having the same lowest channel ID, the operation having the lowest source ID is selected for calculation.

Thus, by data clock cycle 1, all operations have pending computations, and during data clock cycle 1, the operation at register address 014h is selected for computation. (it is the one of the seven operations with the highest sampling rate and it has the lowest source ID in the two of the seven operations with the lowest channel ID.)

During data clock cycle 2, the operation at register address 014h no longer has pending calculations, and the operation at register address 016h is selected for calculation (it is the one of the six operations with pending calculations that has the highest sample rate, and it has the lowest channel ID of those operations). During data clock cycle 3, the operation at register address 058h is selected for computation because it is the one with the highest sample rate of the five operations with pending computations, and it has the lowest channel ID of these operations, and so on.

Thus, after seven operations with a sampling rate of 48k samples/second have been performed during data clock cycles 1-7, five operations with a sampling rate of 8k samples/second are performed during data clock cycles 8-12 because the seven operations with a sampling rate of 48k samples/second have no pending calculations during data clock cycles 8-12.

The next calculations for the seven operations with a sampling rate of 48k samples/second are then performed during data clock cycles 13-19, but no operations are performed during data clock cycles 20-24 because no operations have pending calculations.

Fig. 39 shows slightly more than one full calculation cycle of this process.

Thus, FIG. 39 shows that using a data clock rate of 576kHz is in fact somewhat inefficient because no calculations can be scheduled during certain data clock cycles.

Fig. 40, which is composed of fig. 40(a) and 40(b) on different pages, is a third timing chart illustrating a third possible way of ordering the required series of operations derived from the use examples described above with reference to fig. 32, 34, 35, and 36.

Thus, as in fig. 38 and 39, there are again twelve data routing operations, each of which needs to be scheduled regularly, seven of them having a sampling rate of 48kbps and the other five having a sampling rate of 8 kbps. These operations are identified in fig. 40 by their register address, channel ID and source ID, and sample rate, but in fig. 40, the operations with the same sample rate are combined into groups as in fig. 39, and they are listed in order of their channel ID within each group.

FIG. 40 also shows "time to deadline" for each operation, although it is not used by the scheduling method of FIG. 40.

The data clock DCK rate is set such that there are 48 DCK cycles during each cycle of 8kHz SCK, so that there must be 8 DCK cycles during each cycle of 48kHz SCK. (i.e., the data clock rate is set to 384 kHz).

Fig. 40 also illustrates the same scheduling method as fig. 39, where the operation with the pending calculation and with the highest sampling rate is selected for the calculation. When there are two or more operations with pending calculations and with the same highest sampling rate, the operation with the lowest channel ID is selected for calculation. When there are two or more operations having the same lowest channel ID, the operation having the lowest source ID is selected for calculation. (channel IDs need to be prioritized over source IDs when selecting operations to compute to ensure that all source IDs of data sources that serve as a single data destination are selected one by one.)

Thus, by data clock cycle 1, all operations have pending computations, and during clock cycle 1, the operation at register address 014h is selected for computation. (it is the one with the highest sampling rate of the seven operations and it has the lowest source ID of the two operations with the lowest channel ID of the seven operations.)

During clock cycle 2, the operation at register address 014h no longer has pending calculations, and the operation at register address 016h is selected for calculation (it is the one of the six operations with pending calculations that has the highest sample rate, and it has the lowest channel ID of those operations). During data clock cycle 3, the operation at register address 058h is selected for computation because it is the one with the highest sample rate of the five operations with pending computations, and it has the lowest channel ID of these operations, and so on.

Thus, five operations with a sampling rate of 8k samples/second have pending calculations after seven operations with a sampling rate of 48k samples/second have been performed during data clock cycles 1-7, but seven operations with a sampling rate of 48k samples/second have no pending calculations.

During data clock cycle 8, the operation at register address 010h is selected for computation (five operations with pending computations all have the same sample rate, and it has the lowest channel ID among those operations).

During data clock cycle 9, a new SCK cycle of 48kHz SCK begins, so seven operations with a sampling rate of 48k samples/second now have pending calculations again. Thus, seven operations with a sampling rate of 48k samples/second are performed during data clock cycles 9-15, in the same order as before. After data clock cycle 15, the seven operations with a sampling rate of 48k samples/second have no pending calculations, nor the operation at register address 010 h. Thus, during data clock cycle 16, the operation at register address 06Eh is selected for computation (four operations with pending computations all have the same sample rate, and it has the lowest channel ID among those operations).

This process repeats, with five operations having a sampling rate of 8k samples/second being performed during data clock cycles 8, 16, 24, 32, and 40. Fig. 40 shows slightly more than one full calculation cycle, and from this it can be seen that using a data clock rate of 384kHz is sufficient to allow all required calculations to be scheduled. In fact, no calculations are performed during the data clock cycle 48 because no operations have pending calculations.

Fig. 41, which is composed of fig. 41(a) and fig. 41(b) on different pages, is a fourth timing chart illustrating a fourth feasible manner of ordering a series of operations required.

In the embodiment illustrated in fig. 41, there are the same twelve data routing operations, each of which needs to be scheduled regularly, but in this case the seven operations of the higher data rate have a sampling rate of 44.1k samples/second and the other five have a sampling rate of 8k samples/second. These operations are identified in fig. 41 by their register address, channel ID and source ID and sampling rate, and in fig. 41, the operations having the same sampling rate are combined into groups as in fig. 39 and fig. 40, and they are listed in order of their channel ID within each group.

The clock cycles of data clock DCK are numbered at the top of the table and during each of these clock cycles it is indicated whether each operation has a pending calculation or whether that operation has been selected for calculation.

FIG. 41 also shows "time to deadline" for each operation, although it is not used by the scheduling method of FIG. 41.

The data clock DCK rate is set such that there are 8 DCK cycles during each cycle of 44.1kHz SCK. That is, the data clock rate is set to 352.8 kHz. The 8kHz rate is synchronized to this data clock rate so an 8kHz cycle may contain 44 or 45 DCK cycles. In the illustrated embodiment, a worst case scenario is assumed, as it cannot be predicted which cycles will contain 44 DCK cycles and which cycles will contain 45 DCK cycles. Thus, it is assumed that each 8kHz cycle contains 44 DCK cycles.

It is also feasible to use "sandbagging" in all of these illustrative cases, especially when the exact sampling clock rate is not known a priori. For example, if the sample rate of data having a nominal sampling clock rate of 44.1kHz is actually independent of the DCK, it may actually be less than 44kHz in some cases, so for safety it may be assumed that each 8kHz cycle contains only 43 DCK cycles.

It is also possible to include a "learning cycle" before the calculation phase, in which the actual sampling clock rate is determined. Thus, during the initial period, the sampling clock rate of these signals is measured, and the measured sampling clock rate is used as a basis for subsequent scheduling.

Fig. 41 illustrates the same scheduling method as fig. 39 and 40, where the operation with the pending calculation and with the highest sampling rate is selected for the calculation. When there are two or more operations with pending calculations and with the same highest sampling rate, the operation with the lowest channel ID is selected for calculation. When there are two or more operations having the same lowest channel ID, the operation having the lowest source ID is selected for calculation.

Thus, at the beginning of data clock cycle 1, all operations have pending computations, and during clock cycle 1, the operation at register address 014h is selected for computation. (it is the one with the highest sampling rate of the seven operations and it has the lowest source ID of the two operations with the lowest channel ID of the seven operations.)

Thus, five operations with a sampling rate of 8k samples/second have pending calculations after seven operations with a sampling rate of 44.1k samples/second have been performed during data clock cycles 1-7, but seven operations with a sampling rate of 44.1k samples/second have no pending calculations.

During data clock cycle 9, a new SCK cycle of 44.1kHz SCK begins, so seven operations with a sampling rate of 44.1 kSAMPLE/sec now have pending calculations again. Thus, seven operations with a sampling rate of 44.1 kSAMPLE/sec were performed during data clock cycles 9-15, in the same order as before. After data clock cycle 15, seven operations with a sample rate of 44.1 kSAMPLE/sec did not have any pending calculations, nor did the operation at register address 010 h. Thus, during data clock cycle 16, the operation at register address 06Eh is selected for computation (the four operations with pending computations all have the same sample rate, and it has the lowest channel ID among the operations).

This process repeats, with five operations having a sampling rate of 8k samples/second being performed during data clock cycles 8, 16, 24, 32, and 40.

Because the data clock illustrated in FIG. 41 runs slightly slower than the data clock illustrated in FIG. 40, the SCK period of the 8kHz SCK ends at data clock period 44, and thus five operations with a sampling rate of 8kbps have pending calculations from data clock DCK period 45 onward.

This means that during data clock cycle 48, the operation at register address 010h can be selected for calculation.

FIG. 42 is yet another timing diagram illustrating yet another possible way of ordering the required series of operations. To illustrate the difference of this ordering method from the ordering method described above, there are now fourteen data routing operations, each of which needs to be scheduled regularly, seven of them having a sampling rate of 48k samples/second and the other seven having a sampling rate of 32k samples/second. These operations are identified in FIG. 42 by their register address, channel ID and source ID, and sample rate. In fig. 42, operations having the same sampling rate are combined into groups, and they are listed in order of their channel IDs within each group.

Each operation must be performed once during each of its corresponding SCK cycles, and the start of fig. 42 is the start of the 32kHz sampling clock and the start of the 48kHz sampling clock. The data clock DCK rate is set such that there are 18 DCK cycles during each period of 32kHz SCK, and thus there must be 12 DCK cycles during each period of 48kHz SCK. (i.e., the data clock rate is set to 576 kHz).

FIG. 42 also shows "time to deadline" for each operation. Thus, the "time to deadline" during any given data clock cycle is the number of data clock cycles remaining before the end of that sampling clock cycle (i.e., before the "deadline" at which the data routing operation must be performed). That is, for example, after six DCK periods from the start point of fig. 42, six DCK periods remain before the end of the 48kHz SCK period, and twelve DCK periods remain before the end of the 32kHz SCK period.

FIG. 42 illustrates a scheduling method in which the operation with the pending calculation and with the shortest "time to deadline" is selected for calculation. When there are two or more operations with pending calculations and the same shortest "time to deadline", the operation with the highest sampling rate is selected for calculation. When there are two or more operations with pending calculations and with the same shortest "time to deadline" and the same highest sampling rate, the operation with the lowest channel ID is selected for calculation. When there are two or more operations having the same lowest channel ID, the operation having the lowest source ID is selected for calculation.

Thus, all operations have pending computations before data clock cycle 1, and during data clock cycle 1, the operation at register address 014h is selected to be computed. (it is one of the seven operations that has the same shortest "time to deadline" and highest sampling rate, and it has the lowest source ID of the two of the seven operations that have the lowest channel ID.)

During data clock cycle 2, the operation at register address 014h no longer has pending calculations, and the operation at register address 016h is selected for calculation (which is the one of the six operations with pending calculations that has the shortest "time to deadline" and the highest sample rate, and which has the lowest channel ID among these operations). During data clock cycle 3, the operation at register address 058h is selected for computation because it is the one of the five operations with pending computations that has the shortest "time to deadline" and the highest sample rate, and it has the lowest channel ID of these operations, and so on.

Thus, after seven operations with a sampling rate of 48k samples/second have been performed during data clock cycles 1-7, only seven operations with a sampling rate of 32k samples/second have pending calculations, and thus five of these seven operations (i.e., the five operations with the lowest channel IDs) are performed during data clock cycles 8-12.

Before data clock cycle 13, a new SCK cycle of the 48kHz sampling clock cycle begins, so seven operations with a sampling rate of 48k samples/second, and the remaining two of the seven operations with a sampling rate of 32k samples/second, have pending calculations.

During data clock cycle 13, the operation at register address 064h is selected for computation (both operations with pending computations having the shortest "time to deadline" have the same sample rate, which has the lower channel ID among them). Similarly, during data clock cycle 14, the operation at register address 065h is selected for computation (it is now the only operation with pending computations having the shortest "time to deadline").

It should be noted that this scheduling method therefore yields different results than the scheduling method described above, in which two of the operations having a higher sampling rate of 48k samples/second would otherwise be selected for calculation during data clock cycles 13 and 14. In fact, the other scheduling methods described above are inherently unable to schedule all required operations without increasing the data clock rate.

During data clock cycles 15-18, operations with a sampling rate of 32k samples/second have the shortest "time to deadline," but none of them have pending calculations, so the first four of the operations with a sampling rate of 48k samples/second are selected for calculation.

A new SCK period of the 32kHz sampling clock starts before the data clock period 19, so seven operations with a sampling rate of 32k samples/second have pending calculations. However, the operation with a sampling rate of 48kbps now has the shortest "time to deadline", so the last three of the operations with a sampling rate of 48k samples/second are selected for calculation during the data clock cycles 19-21.

During data clock cycles 22-24, operations with a sampling rate of 48k samples/second have the shortest "time to deadline," but none of them have pending calculations, so the first three of the operations with a sampling rate of 32k samples/second are selected for calculation.

Before data clock cycle 25, a new SCK cycle of the 48kHz sampling clock begins, so seven operations with a sampling rate of 48k samples/second, and the remaining four operations with a sampling rate of 32k samples/second, all have pending calculations.

Furthermore, all operations with pending calculations now have the same "time to deadline", so this sampling rate is used as the basis for selection, and seven operations with a sampling rate of 48k samples/second during data clock cycles 25-31 are selected for calculation, which means that the remaining four operations with a sampling rate of 32k samples/second are not selected for calculation until data clock cycles 32-35. In data clock cycle 36, there are no pending calculations for the operation.

Fig. 43 shows the clock generation circuit 80 shown in fig. 3 in more detail. The clock generation circuit 80 includes a Frequency Locked Loop (FLL)1100 for generating a clock signal at a first clock frequency (C) from an input clock signal_F1) The first clock signal. In the illustrated embodiment, the FLL 1100 is capable of receiving a first master clock signal and a second master clock signal. For example, the first master clock signal and the second master clock signal may be generated on the audio hub integrated circuit itself, or may be received from an off-chip source (such as a crystal oscillator used for other purposes in a device containing the audio hub, or a USB clock source). FLL 1100 also receives a control signal for controlling the FLL so that the first clock signal is generated at a desired frequency, regardless of which master clock signal is available at that time. In the illustrated embodiment, the first clock frequency is 49.152MHz, i.e., 1024 × 48kHz, as is commonly used in audio systems and applications.

The first clock signal is passed to a first divider 1102, and the first divider 1102 divides the first clock frequency by 2 to generate a clock signal at a second clock frequency (C)_F2) Of the first clock signal. Thus, in the illustrated embodiment, the second clock frequency is 24.576 MHz. The second clock signal is transmitted toA second frequency divider 1104, the second frequency divider 1104 dividing the second clock frequency by 2 to generate a clock signal at a third clock frequency (C)_F3) The third clock signal of (1). Thus, in the illustrated embodiment, the third clock frequency is 12.288 MHz. The third clock signal is passed to a third frequency divider 1106, which third frequency divider 1106 divides the third clock frequency by 2 to generate a clock signal at a fourth clock frequency (C)_F4) The fourth clock signal of (1). Thus, in the illustrated embodiment, the fourth clock frequency is 6.144 MHz.

The first clock signal is also passed to the first switch 1108, while the second clock signal is passed to the second switch 1110, the third clock signal is passed to the third switch 1112, and the fourth clock signal is passed to the fourth switch 1114.

The chip contains a plurality of IP blocks (i.e., functional blocks) 1120, 1122, 1124, only three of which are shown in fig. 43, although it will be appreciated that in reality there will be many more such blocks. For example, the IP blocks 1120, 1122, 1124 may be programmable digital signal processing blocks, or digital signal processing blocks with fixed functionality, as described above. In particular, it is expected that one of the IP blocks 1120, 1122, 1124 should be a mixer as described above.

There is a preferred clock frequency for each of the IP blocks 1120, 1122, 1124. This preferred clock frequency may be fixed or it may vary depending on the processing load at a particular time. In particular, the preferred clock frequency of the mixers described above will vary depending on the number of signal paths that need to be processed, as described with reference to fig. 38-42.

Each of

IP blocks

1120, 1122, 1124 has associated with it a

respective multiplexer

1126, 1128, 1130. Multiplexers 1126, 1128, 1130 each receive data at the four clock frequencies C_F1、C_F2、C_F3、C_F4All four clock signals.

Each of the IP blocks 1120, 1122, 1124 passes a control signal to the corresponding

multiplexer

1126, 1128, 1130 at least at that particular moment in time, indicating the preferred clock frequency. Thus, each

multiplexer

1126, 1128, 1130 passes a clock signal at the preferred clock frequency to its associated

IP block

1120, 1122, 1124. This has the following advantages: each IP block may run at a clock frequency that is high enough to provide the required functionality, but not so high as to unnecessarily consume power.

Advantageously, while IP blocks 1120, 1122, 1124 may be physically located anywhere in the chip, the associated

multiplexers

1126, 1128, 1130 are physically close to FLL 1100 and

dividers

1102, 1104, 1106. This has the following effect: the clock signals are not distributed to IP blocks that do not require them.

Further, control signals generated by the IP blocks 1120, 1122, 1124 indicating their respective preferred clock frequencies are also communicated to the logic block 1136. This determines, for the clock frequency C_F1、C_F2、C_F3、C_F4Whether there is an IP block requiring that clock frequency.

For a clock frequency C required by at least one of the IP blocks_F1、C_F2、C_F3、C_F4Logic block 1136 ensures that the

respective switches

1108, 1110, 1112, 1114 remain closed (closed). However, if the clock frequency C_F1、C_F2、C_F3、C_F4One of which is not required by any IP block, logic block 1136 ensures that the

corresponding switch

1108, 1110, 1112, 1114 remains open (open). This has the following advantages: no power is unnecessarily consumed even when this clock signal is distributed as far as the

multiplexers

1126, 1128, 1130.

Fig. 44 shows an alternative form of the clock generation circuit 80 shown in fig. 3 in more detail.

The chip contains a plurality of blocks 1200.1, 1200.2, … …, 1200.M, only the first of which is shown in detail in fig. 44. For example, the blocks 1200.1, 1200.2, … …, 1200.M may be programmable digital signal processing blocks, or digital signal processing blocks with fixed functionality, as described above. In particular, it is expected that one of the blocks 1200.1, 1200.2, … …, 1200.M should be a mixer as described above.

Each of the blocks 1200.1, 1200.2, … …, 1200.M includes a corresponding function block 1210, an N: 1 multiplexer 1212, and control logic 1214. There is a preferred clock frequency for each of the blocks 1200.1, 1200.2, … …, 1200. M. This preferred clock frequency may be fixed or it may vary depending on the processing load at a particular time. In particular, the preferred clock frequency of the mixers described above will vary depending on the number of signal paths that need to be processed, as described above.

Clock generator 1216 is capable of generating clock signals at N frequencies, which in this embodiment are 49.152MHz, 24.576MHz, 12.288MHz, and 6.144 MHz.

Each of the IP blocks 1200.1, 1200.2, … …, 1200.M transmits an N-bit signal to the M: N or gate 1218 at least at that particular time indicating its preferred clock frequency. When an IP block 1200.1, 1200.2, … …, 1200.M wishes to change its preferred clock frequency, it signals the M: N or gate 1218 that it wishes to change to a frequency, but also indicates its current frequency until such time as the change has been effected.

The output of the or gate 1218 is therefore an N-bit signal indicating which of the available frequencies are required by any of the blocks 1200.1, 1200.2, … …, 1200. M.

Thus, the clock generator 1216 generates only clock signals at those frequencies required by one or more of the blocks 1200.1, 1200.2, … …, 1200. M.

Each generated clock signal is passed to each of the N: 1 multiplexers 1212, and the control logic 1214 in each block 1200.1, 1200.2, … …, 1200.M selects the frequency required by the corresponding functional block 1210. Preferably, the multiplexers 1212 are located close to the clock generators 1216 (although this may be relatively far away from their respective functional blocks 1210) because this reduces power losses associated with transmitting unnecessarily high frequency clock signals along long paths.

In addition, clock generator 1216 sends a control signal to power control block 1220 indicating the highest frequency it is generating. Power supply control block 1220, in turn, sends a signal to power supply 1222 that controls its output voltage, which is the voltage supplied as the power supply voltage to each of blocks 1200.1, 1200.2, … …, 1200. M.

In general, if a functional block is running at a slower clock, it may be running at a lower supply voltage (supply voltage). (thus, depending on the clock rates of the different functional blocks, it may be feasible to provide different supply voltages to the different functional blocks.) however, if the same supply voltage is provided to each functional block, a more efficient use of silicon may be achieved. Thus, in this embodiment, the same supply voltage is provided to each functional block, but this varies according to the highest clock frequency supplied to any one of the functional blocks.

Fig. 44a shows an alternative form of the clock generation circuit 80 shown in fig. 3 in more detail. The alternative clock generation circuit 80.1 comprises a Frequency Locked Loop (FLL)1100 for generating a clock signal at a first clock frequency (C) from an input clock signal_F1) The first clock signal. In the illustrated embodiment, the FLL 1100 is capable of receiving a first master clock signal and a second master clock signal. For example, the first master clock signal and the second master clock signal may be generated on the audio hub integrated circuit itself, or may be received from an off-chip source (such as a crystal oscillator used for other purposes in a device containing an audio hub, or a USB clock source). FLL 1100 also receives a control signal for controlling the FLL so that the first clock signal is generated at a desired frequency, regardless of which master clock signal is available at that time. In the illustrated embodiment, the first clock frequency is 49.152MHz, as is commonly used in audio systems and applications.

As in fig. 43, three

IP blocks

1120, 1122, 1124 are shown for illustration purposes. Each IP block has its own preferred clock frequency and control signals generated by the IP blocks 1120, 1122, 1124 indicating their respective preferred clock frequencies are also passed to the logic block 1136.1.

The clock signal generated by FLL 1100 is passed to a pulse skip block 1140 in the form of a clock gate. Pulse skipping control block 1142 contains a counter for counting pulses in the clock signal generated by FLL 1100. The control signal from the pulse skipping control block 1142 is transmitted to the multiplexer 1144 and the control distribution block 1146. In particular, in this illustrated embodiment, the pulse skipping control block generates four data signals at four available clock frequencies, namely 49.152MHz, 24.576MHz, 12.288MHz, and 6.144 MHz.

Logic block 1136.1 determines which of the four available clock frequencies is the highest clock frequency required by any of

IP blocks

1120, 1122, 1124. Based on this determination, logic block 1136.1 controls multiplexer 1144 such that the data signal at that highest frequency is passed to the control input of pulse skipping block 1140. In response, the pulse skipping block 1140 may skip a proportion of the pulses in the clock signal generated by the FLL 1100 to generate a clock signal at the highest clock frequency required by any of the IP blocks 1120, 1122, 1124. This clock signal is then communicated from the pulse skip control block 1140 to the pulse skip blocks 1148, 1150, 1152 associated with the three

IP blocks

1120, 1122, 1124, respectively. Each of the

pulse skipping blocks

1148, 1150, 1152 is controlled by a

respective multiplexer

1154, 1156, 1158.

The four data signals at the four available clock frequencies are also transmitted from the pulse skipping control block 1142 to the control distribution block 1146, which control distribution block 1146 also receives control signals from the logic block 1136.1. In particular, logic block 1136.1 determines which of the four available clock frequencies are required by one or more of

IP blocks

1120, 1122, 1124. Based on this determination, the control allocation block 1146 ensures that data signals at the or each frequency required by one or more of the IP blocks 1120, 1122, 1124 are communicated to the

multiplexers

1154, 1156, 1158. Thus, control distribution block 1146 masks data signals at frequencies not needed by any of

IP blocks

1120, 1122, 1124 such that they are not unnecessarily fanned out on the chip.

Each of the IP blocks 1120, 1122, 1124 is connected to send a control signal to its respective associated

multiplexer

1154, 1156, 1158 to cause that multiplexer to send a data signal at the frequency required by that IP block to the associated

pulse skipping block

1148, 1150, 1152. The

pulse skipping blocks

1148, 1150, 1152 in turn cause a required portion of the pulses in the clock signal from the pulse skipping block 1140 to be skipped such that the clock signal at the required frequency is communicated to the

respective IP blocks

1120, 1122, 1124.

This has the following advantages: the clock signal is distributed along a single path regardless of frequency. Although data signals at different frequencies are distributed, they do not need to be balanced so they can propagate on-chip with less concern about the length of the signal path, as timing is less of an issue for these unbalanced signals.

Fig. 44b shows yet another embodiment of the clock generation circuit 80 shown in fig. 3 in more detail. This alternative clock generation circuit 80.1 is similar to the alternative clock generation circuit 80.1 shown in fig. 44a, and features having the same function as those of fig. 44a are indicated with the same reference numerals.

In the embodiment shown in fig. 44b, each

IP block

1120, 1122, 1124 has a respective

pulse skipping controller

1160, 1162, 1164, which 1160, 1162, 1164 receives a respective signal from pulse skipping control block 1142. Based on the corresponding signal received from pulse skipping control block 1142, each

pulse skipping controller

1160, 1162, 1164 causes its respective

pulse skipping block

1148, 1150, 1152 to skip the required portion of the pulses in the clock signal from pulse skipping block 1140 so that the clock signal at the required frequency is transmitted to the corresponding

IP block

1120, 1122, 1124.

This means that only one synchronization signal is sent to each IP block instead of a larger number of pulse skipping control signals.

Fig. 44c shows an alternative to fig. 44, illustrating source voltage control in the case where clock generation is performed as shown in fig. 44a or fig. 44 b. In this case, only one clock is distributed to the IP block 1200. Again, under the control of the select control signal and pulse skipping block 1226, there is a pulse skipping control signal assigned to these IP blocks so that each IP block can select the appropriate pulse skipping rate and pulse skipping that clock to provide a clock with the desired frequency. As described previously with reference to fig. 44, the source voltage is controlled based on the required sampling clock.

Fig. 45-55 illustrate in more detail the operation of a mixer in one embodiment of the invention, such as mixer 290 shown in fig. 15. FIG. 45 is a block diagram illustrating the functional structure and other contents of the mixer; FIGS. 46, 47 and 48 are flow diagrams illustrating the operation of portions of the mixer; FIG. 49 is a block diagram illustrating the enable and clock control block in the mixer in greater detail; FIG. 50 is a flow chart illustrating a portion of the method of FIG. 48 in greater detail; FIG. 51 is a flow chart illustrating a method performed in a MAC utilization predictor in the mixer; FIG. 52 is a block diagram illustrating in more detail the channel scheduler block in the mixer; FIG. 53 is a flow chart illustrating a method performed in the channel scheduler; FIG. 54 is a block diagram illustrating a computation pipeline in the mixer; and FIG. 55 is a flow chart illustrating a method performed in the channel scheduler and the computation pipeline.

In the description of fig. 45-55, the term "channel" is used to refer to the signal destination port, which is the output from the mixer to a particular DSP function, or from the chip: one channel has a unique address so that outgoing data can be sent over the shared bus. Each output channel has one or more "selectors", each selector representing one possible connection to an input signal or signal source port: a selector has an associated register to select the input signal by its address on the input bus and optionally an associated register to apply the gain factor to that path segment.

Fig. 45 illustrates the overall functional structure of the mixer, and fig. 46 is a flowchart providing an overview of the operation of the mixer in the audio codec.

The mixer 600 shown in fig. 45 includes a register bank 602, which register bank 602 is programmed by an application processor on a control interface 650, which is then programmed by a system programmer (e.g., a user) to set the required connections in the mixer, including gain control and allocation of each channel to one of the available sampling rates. Thus, the operations corresponding to each programmed use case are stored in a memory associated with the application processor, which also monitors the status of the entire device. Operations corresponding to the active use case are then downloaded to the register file 602 based on this status. Thus, for example, when a smartphone is used to play back recorded music by means of, for example, the external system 23, the relevant operations for that use case are stored in the register bank 602. When a telephone call is initiated, use cases for handling voice calls are downloaded. When the user of the device plugs in the headset, the relevant operations for that use case are downloaded to the register bank 602, and so on.

The enable and clock control block 604 controls which input selector/output channels are enabled and disabled based on user requests through the register bank.

That is, at any given time, register bank 602 indicates to enable and clock control block 604 whether each selector is requested to be enabled, and also indicates the sampling rate for each channel and the frequency of each SCK.

When the write of data to the register bank 602 has been completed (step 680 in FIG. 46), the enable and clock control block 604 also controls clock gating so that the Data Clock (DCK) for the mixer may be scaled to the appropriate frequency. That is, it decides whether the Data Clock (DCK) is fast enough (step 682 in fig. 46) and adjusts it if it is too slow (step 684 in fig. 46). A flag (flag) indicating which selectors are active is set (set) in step 686 of fig. 46.

The channel scheduling block 620 selects the next output channel to be calculated. Fig. 47 is a flow chart illustrating a method performed in the channel scheduling block 620. Thus, when a new Data Clock (DCK) edge is detected (step 688 in fig. 47), the channel scheduling block 620 updates its monitoring of the Sampling Clock (SCK) to determine the time to deadline for each sampling clock rate, as described in more detail below.

Fig. 48 is yet another flow chart illustrating a method performed in the channel scheduling block 620 and the calculation block 630. In this embodiment, the channel scheduling block 620 selects the channel with the earliest deadline as the next channel to be calculated (step 694 in fig. 46). The selected channel is notified to the computation block 630, the computation block 630 generates an output for the selected channel (step 696 in fig. 48), and this is repeated until all computations required in that SCK cycle have been completed.

The compute pipeline block 630 controls taking data for one output sample value (output sample value) and performing the computation of that output sample value. In the compute pipeline block 630, the computation is performed over several Data Clock (DCK) cycles, as described above. Each output value may need to combine data from one or more inputs and operate under control of channel calculation control block 634. Thus, control block 634 obtains the channel ID (i.e., output address) of the next calculation to be performed from scheduler 620, and control block 634 then sends a bus control signal and a control signal for MAC 292, which iterates (iterative) these calculation steps.

Once the final step of the computation has been performed, the result is sent to the appropriate output buffer 642 via output bus (op _ all bus) 640 using the output address of the channel. As described above, the output buffers 642 are associated with respective signal destinations and each output sample is made available for the entire duration of one cycle after the cycle of the associated sampling clock at which the computation has been performed. The output may then be transmitted to the intended output at some point during that next sampling clock cycle via a corresponding output bus 644.

As mentioned above, the data clock DCK frequency may be varied and preferably kept at a minimum frequency consistent with ensuring that all required operations can be performed, to advantageously minimize power consumption. Thus, as shown in FIG. 49, and as described in more detail below, enable and clock control block 604 comprises: a selector state block 606 that indicates which operations are active at any one time; and a MAC Utilization Predictor (MUP) function 608 that determines the minimum frequency of the Data Clock (DCK) required to perform the computation for all selectors that are currently enabled or required to be enabled.

FIG. 50 is a flow chart illustrating a method performed by enable and clock control block 604.

The method of FIG. 50 begins at step 720, but the process does not begin at step 722, at which point the writing of data to the register bank 602 has been completed (as also shown at step 680 in FIG. 48).

In step 724, it is determined which of the possible selectors are desired at that particular time. As described in more detail with reference to FIG. 49, a selector is determined to be "desired" if it is requested by one of the processors at that time, and/or if it remains "current".

As shown in fig. 49, the enable and clock control block 604 contains one selector state block 606 for each possible selector input for each channel, only one such selector state block 606 being shown in fig. 49 for clarity.

Each selector state block 606 contains a multiplexer 750, and each of these multiplexers receives inputs at a rate corresponding to all available Sampling Clocks (SCK). Each multiplexer 750 receives a selection input corresponding to the SCK for the channel associated with that selector. Latch 752 is then clocked on each rising edge of that appropriate sampling clock signal.

Each selector state block 606 also receives a flag on its input line 754 that indicates whether that particular selector has been "requested", i.e., whether it has been identified by the register bank 602 as being used in one of the active use cases. The selector "requested" flag is passed to one input of AND gate 756 and also to latch 758, which latch 758 passes on to the second input of AND gate 756 only when it receives a DCK "OK" signal from clock gear control block 610, indicating that the current Data Clock (DCK) rate is acceptably fast. If the DCK clock frequency is not currently fast enough but can be accelerated, this can temporarily block this selector from being processed until the acceleration has occurred. This may permanently block the selector from becoming operational if the DCK clock frequency is at a maximum.

If the selector "requested" flag is set and is also passed by the latch 758, the AND gate 756 generates a selector "active" flag. The selector "active" flag is transferred to the latch 752, and the latch 752 continues to transfer the selector "active" flag as the selector "current" flag based on the control signal supplied from the multiplexer 750. The selector "active" flag is also communicated to the channel scheduler, as described in more detail below.

The IDs of these selectors with the selector "current" flag set are passed to channel calculation control block 634 of calculation pipeline block 630. These selectors are operative and need to be processed in the current sampling clock cycle. Thus, when a selector is requested, it will first become "active", but not become "current" until the beginning of its next SCK cycle, to prevent this from occurring just before the end of an SCK cycle when it may not be possible to schedule it.

Also, the selector "requested" signal and the selector "current" signal are passed to an OR gate 760, and the output of the corresponding OR gate in each selector state block 606 is passed as a selector "expected" bit to a MAC Utilization Processor (MUP) block 608. Thus, the selector with the "expected" flag set is taken into account when determining the required data clock rate, as described below. Thus, the "expected" flag is set for any selector that has been "requested", even if the selector has not become "active"; but also sets the "expected" flag for any selector that remains "current", even if that selector has ceased to be "requested" or "active".

The enable and clock control block 604 also contains an SCK status block 762 for each SCK. Each SCK status block controls the frequency of its corresponding SCK, particularly when it manages transitions from one frequency to another when required. In one embodiment, the number of SCK status blocks 762 may be, for example, four, meaning that four different SCKs may be available at any one time. However, these four SCKs may be selected from a larger set of SCKs that have become potentially available.

When an SCK clock at a particular frequency is required, the SCK freq [1] register is changed to a value representing the newly required frequency. The register value may be mapped to the frequency in any convenient manner. This implementation is simplest if there is some order such that in one embodiment this mapping can be chosen to match a particular industry standard for configuring the data rate. For example: 1-12 kHz; 2-24 kHz; 3-48 kHz; and the like; 9 ═ 11.025 kHz; 10-22.05 kHz; 44.1kHz, 11 ═ 44.1 kHz; 12-88.2 kHz; and the like; 16-4 kHz; 17-8 kHz; 18-16 kHz; and so on. This value represents that the new frequency is passed to latch 764 where it is latched until the change can be scheduled.

Latch 764 is controlled by or gate 766. One input to the or gate 766 is the DCK "ok" signal from the clock gear control block 610, mentioned above, which indicates that the current Data Clock (DCK) rate is acceptably fast. A second input of or gate 766 is the output of comparator 768, which determines whether the newly requested SCK frequency is less than the currently active SCK frequency. If it has been determined that the current Data Clock (DCK) rate is acceptably fast, or if it is determined that the newly requested SCK frequency is less than the currently active SCK frequency, the newly requested SCK frequency is passed through latch 764 so that it becomes the currently active SCK frequency. This frequency is then passed to a down counter in the channel scheduler, as described in more detail below.

The active frequency is also transferred to the second latch 770, which second latch 770 is controlled by the SCK clock signal. This ensures that the active frequency cannot become the "current" frequency until the start of the next SCK clock cycle. When this change occurs, a signal indicating the "current" frequency is passed to the SCK generator, which causes the signal to be generated at that frequency.

The signals indicating the "requested" SCK frequency, the "active" SCK frequency, and the "current" SCK frequency are communicated to block 772, which block 772 determines which of these frequencies is the highest. The highest of these three frequencies represents the worst case when determining whether all required SCK frequencies can be scheduled at the current DCK rate. Thus, the output of the block 772 is communicated back to the MUP 608 to allow it to determine whether the current DCK rate is appropriate, as described in more detail below.

In step 726 of the process shown in fig. 50, the MUP block 608 calculates the required minimum DCK frequency to allow all required operations to be scheduled in their respective sampling clock cycles.

Fig. 51 is a more detailed flow chart illustrating the processing performed in the MAC Utilization Processor (MUP) block 608.

The process of FIG. 51 begins at step 778 and the value stored in the accumulator is cleared at step 780.

In step 784, one of the SCKs, SCK (n), is selected, and the number of selectors (for which the MUP block 608 has received selector "desired" bits from the corresponding or gate 760) associated with that SCK is counted. The count value is incremented by a first number in step 786 to account for delays through the compute pipeline. Recognizing that a single pipeline computation takes 5 DCK cycles, this first number may be, for example, 5. The count value is incremented by a second number at step 788 to account for possible delays in the compute pipeline block when changing the SCK rate. This second number may for example be 3, i.e. one less than the maximum number of selectors per channel.

Thus, the incremented count value represents a conservative estimate of the worst case possible effect on all "expected" selectors at that SCK rate.

In step 790, an arbitrary time period is defined. For convenience, that arbitrary time period may be set to the least common multiple of the periods of the signals at the available SCK rate. For example, if the available SCK rates are 8kHz and 48kHz, their periods are 1/(8kHz) and 1/(48kHz), and the arbitrary time period can be 1/(8kHz), i.e., 125 μ s.

To allow for the requested change in frequency of sck (n), the worst case frequency of sck (n) is obtained, as determined by the output of the corresponding block 772. The worst-case (i.e., maximum possible) number of sck (n) cycles in this arbitrary time period is then calculated. In the embodiment given above, there are one cycle of the 8kHz clock and six cycles of the 48kHz clock in the arbitrary time period of 1/(8 kHz). This number of cycles is multiplied in step 790 by the count value obtained in step 788.

The product obtained in step 790 is added to an accumulator value in step 792.

Step 784-792 is then repeated for each SCK. Of course, equally, steps 784-792 may be performed in parallel for each SCK.

The final accumulator value obtained after step 792 has been performed the last time represents the number of operations that may be required in each arbitrary time period.

In step 800, one of the DCK rates, DCK (m), is selected. The number of cycles of dck (m) in any time period mentioned above is then obtained and compared to the accumulator value obtained in the last iteration of step 792. Thus, this number of cycles represents the number of operations that can be performed in each arbitrary time period. It is therefore determined in step 800 whether the accumulator value obtained in the last iteration of step 792 is less than or equal to the number of cycles of dck (m) in the arbitrary time period.

If so, this indicates that if the data clock rate DCK (m) is selected, it will be less than fully utilized, and the process proceeds to step 802, where a flag indicating whether it is acceptable (DCK (m) _ OK) is set equal to 1 (which means that it will be acceptable) and output to the clock transmission control block 610.

If it is determined in step 800 that the accumulator value obtained in the last iteration of step 792 is not less than or not equal to the number of cycles of dck (m) in any time period, indicating that if the data clock rate dck (m) is selected, it will be greater than fully utilized, and the process proceeds to step 804, where a flag indicating whether it is acceptable (dck (m) _ OK) is set equal to 0 (which means that it will be unacceptable) and output to the clock transmission control block 610.

Step 800-. Of course, equally, steps 800-806 may be performed in parallel with each DCK rate.

When all of these DCK rates have been tested in this manner, the process proceeds to step 810 and then ends.

Thus, a respective flag indicating whether each DCK rate (i.e., 6.144MHz, 12.288MHz, 24.576MHz, and 49.152MHz in FIG. 49) is acceptable is output from the MUP block 608 to the clock gear control block 610.

The output of the MAC utilization predictor 608 is used by the clock drive controller 610 to select the appropriate DCK clock frequency.

Returning to FIG. 50, having calculated the schedulability of the operations required at each possible DCK rate, the process proceeds to step 728 where the clock gear control block 610 determines whether all of the "desired" selectors can be scheduled at the current actual DCK frequency. If not, the process proceeds to step 730 where an increase in the DCK frequency is requested via a "desired clock select" signal sent to the clock generator via output 612. The clock frequency is then increased in step 732.

Once the DCK frequency has been increased and the selectors found "desired" in step 728 may all be scheduled at the current actual DCK frequency, the process proceeds to step 734.

In step 734, if the lower DCK frequency still allows all "expected" selectors to be scheduled, a request is sent to the clock generator to reduce the DCK frequency.

Thus, the mixer is caused to run on a slower clock when fewer selectors are enabled, thereby advantageously saving power, or the clock frequency can be increased when required to accommodate requests for new selectors to become enabled.

If MAC utilization predictor function 608 determines that the current clock frequency is sufficient, it will allow the "requested" selector to become "active"; otherwise, it will block any selector from becoming enabled. If blocked, this can also be detected by intercepting the signal sent to the clock generator, allowing the developer of the consumer device containing the routing circuit to use the signal as a debug signal.

In step 740, the DCK ENTER signal is sent from the clock gear control block 610 to the latch 758 to allow the "requested" selector to become "active". If a request has just been sent that the DCK frequency should be increased, the signal is not sent to the latch until the DCK frequency has been increased.

In step 742 of the process shown in FIG. 50, an edge of the relevant SCK is detected, and its step 744 is used to control the latch 752 so that the selector "active" flag becomes the selector "current" flag.

As described above, the channel scheduler 620 selects the channel for which the next computation is to be performed. The channel scheduler 620 is shown in more detail in fig. 52a, and fig. 52b is a flow chart illustrating a portion of the operation of the channel scheduler 620.

Channel pending flag block 622 in channel scheduler 620 receives the selector "active" flag from and gate 756. The channel pending flag block 622 also receives all available SCK signals and all channel-SCK allocations (channel-SCK allocations) from the register bank 602. Then, for each output channel, a channel pending flag is stored in a channel pending flags block 622 to indicate whether there are pending calculations.

Fig. 52b illustrates the updating of the channel pending flag. Each channel is considered separately and although fig. 52b shows them processed sequentially, they may likewise be processed in parallel.

In step 892, it is determined whether a rising edge of the corresponding sample rate clock SCK has been detected. If so, the process proceeds to step 894 and determines whether that channel is active. If so, the process proceeds to step 896 and the channel pending flag is set.

Thus, if a channel is enabled (i.e., if the selector "active" flag for any selector for that channel has been received), at the beginning of each sampling period assigned to that particular channel, a channel pending flag is set, as indicated by the associated sampling clock frequency (SCK).

For each sample clock, there is a corresponding SCK down counter block 830.1, … …, 830. X. For clarity, only one of these SCK down counter blocks is shown in detail in fig. 52. Based on the channel-SCK assignment supplied from the register bank 602 to the channel scheduler 620, the SCK identifies the channel with the corresponding sampling clock frequency to a channel list block (channel listing block)832 in the down counter block. The result is passed to a first input of an N-bit and gate 834. The channel ID with the channel pending flag set is passed to a second input of the N-bit and gate 834. Thus, the and gate 834 in each SCK down counter block 830 is able to identify the pending channel associated with that SCK and generate an n-bit output, each bit indicating whether the corresponding channel is the channel with the corresponding sampling clock frequency and with the pending flag set.

The multi-bit output of and gate 834 indicates which of these channels at the corresponding sampling rate (SCK) has pending calculations. This multi-bit output is passed to a nor gate 835, which generates an output signal when none of the channels at the corresponding sampling rate (SCK) have pending calculations.

Each SCK down counter block 830 also contains a look-up table (LUT)836, the look-up table 836 containing values representing the period of that SCK, measured in the period of the slowest available data clock DCK. The down counter 838 receives the pulses of the corresponding SCK signal for that SCK down counter block, and when the rising edge of that SCK signal is detected (step 870 in fig. 53), the value from the look-up table 836 is loaded into the down counter 838 (step 872 in fig. 53).

For each subsequent cycle in which the rising edge of that SCK signal is not detected, the down counter 838 then counts down from that value at a rate of one count per cycle of the slowest available DCK signal, or if necessary at a rate of a multiple of the slowest available DCK signal. Thus, the down counter 838 maintains a record of the time to deadline for that sampling clock SCK.

The output of the nor gate 835 and the output of the down counter 838 are transmitted to an or gate 837. Thus, when one or more channels at a corresponding sampling rate (SCK) have pending calculations, the down counter block 830 outputs its corresponding current down counter value (SCK1_ count, SCK2_ count, … …, sckn _ count) to the comparator 840. Down counter block 830 outputs a maximum value to comparator 840 when no calculations are pending for the channel at the corresponding sample rate (SCK).

Although the use of the down counter 838 is described herein, of course the exact same effect can be achieved by: that is, an up counter block is used to count the cycles of the DCK signal until a value representing the cycle of the corresponding SCK signal is reached to determine the remaining to-deadline time for that sampling clock SCK.

As mentioned above, comparator 840 receives the count values associated with the different SCK rates, and it then selects the SCK with the lowest count value, i.e., the SCK rate with the shortest expected time to the end of the sampling period among the SCK rates with the pending calculations.

Thus, the channel scheduler 620 first selects the highest priority sampling rate. In this illustrated embodiment, an "earliest deadline first" scheduling method is used. That is, the computation with the earliest deadline is selected first for the most favorable scheduling and the deadline for that computation is determined by the assigned sampling rate. In other embodiments, other scheduling methods may be used.

Then, from the set of channels assigned to that SCK, one channel is selected as the next channel to be calculated.

Comparator 840 outputs a signal identifying the selected sampling clock and block 842 identifies the channel assigned to that sampling clock. The result is transmitted to a first input of and gate 844, and gate 844 receiving channel pending data at its second input.

And gate 844 thereby identifies the pending channel at the selected sampling rate and the result is passed to priority encoder 846.

The priority encoder 846 selects one channel. The selected channel must be pending and assigned to the selected sampling rate, but otherwise is an arbitrary choice. In one embodiment, the channels are selected in ascending order of output address. The selected channel ID is communicated to the compute pipeline controller block 632 in compute pipeline block 630.

Once a channel has been received by the compute pipeline block 630, the flag set in the channel pending flag block 622 is cleared until the next sample period. Thus, at any time, the channel scheduler 620 has a record of the calculations that must still be performed by the end of the current sampling period.

The compute pipeline controller 632 obtains the channel ID (i.e., output address) of the next computation to be performed from the scheduler 620, and it then iterates through the computation steps, providing control signals to other blocks in the pipeline, as described in more detail below.

Once the first step of the computation is entered into the pipeline, this is communicated back to the channel pending flag block 622 so that the computation can be marked as successfully scheduled. Alternatively, the fact that the final step of the computation has been entered into the pipeline may be communicated back to the channel pending flag block 622.

Fig. 54 illustrates a form of the calculation pipeline block 630, and fig. 55 is a flowchart illustrating a method performed in the calculation pipeline block.

On a new DCK edge (step 914 in fig. 55), the compute pipeline controller block 632 selects a channel (step 916 in fig. 55) based on the channel ID received on line 940 from the priority encoder 846 of the channel scheduler 620 (indicating the next channel to be executed). In step 918 of fig. 55, the compute pipeline controller block 632 sends a signal to the channel pending flags block ("go to next channel" signal in fig. 52) to clear the channel pending flags for that channel. As described above, as an alternative, the channel pending flag may be cleared when the computation has been completed.

The compute pipeline controller block 632 also receives the "current" selector ID from the enable and clock control block 604 on line 942.

In step 920 of the process in FIG. 55, the compute pipeline controller block 632 sets the value n to 1. In step 922, the compute pipeline controller block 632 obtains a data value for the nth selector associated with the current channel. In the register map, there is a permanent association between the selector and the channel ID. Thus, compute pipeline controller block 632 sends the selector ID on line 944 to register bank 602, and register bank 602 returns the corresponding source ID on line 946. By enabling the mixer input bus, the data value at this source ID can be read and applied specifically to the first input of multiplexer 950.

The register bank 602 also returns a corresponding gain setting on line 948 (step 924 in fig. 55) and it is applied to a coefficient lookup block 952, which coefficient lookup block 952 generates the corresponding multiplication coefficient. This multiplication coefficient is applied to a second input of multiplexer 950. Thus, in step 926 of the method of FIG. 55, the data value is multiplied by a gain factor. For the first selector (when there is a signal on line 958 from the compute pipeline controller controlling accumulator portion 954), this result is stored in accumulator portion 954 of the multiply accumulate block (MAC) (step 928 in fig. 55), or for any subsequent selector, the result is added to the existing value stored in accumulator portion 954 (step 930 in fig. 55), and accumulator portion 954 performs a step of output computation.

In step 932 of fig. 55, it is determined whether any additional selectors are used for the current channel. If so, the process proceeds to step 934, where the next DCK pulse edge is waiting, and to step 938, where the value n is incremented by 1, and steps 922-932 are repeated.

When it is determined in step 932 that there are no further selectors for the current channel (when there is a signal on line 962 from the calculation pipeline controller), then the value stored in accumulator 954 represents the final result of the calculation for that channel, i.e., the sum of one or more input data values (each scaled by a corresponding gain value).

The compute pipeline controller block 632 enables the intended output address for that channel on output bus 640 (via the signal on line 964) so that the final result is stored in the mixer output buffer (i.e., the destination associated with the corresponding signal destination block).

The primary user considered above is the designer or system programmer of the end product or consumer device, but the end user of the product will also use the product and transfer data through the product. However, the ease of reprogramming the signal flow through the routing circuit enables new end-use cases to be allowed, and also makes it feasible that new use cases and/or data for use in one or more function blocks can be allowed by a skilled end-user, or an end-user without expertise with the help of free-to-download or pay-for-download real-time application software. To avoid possible damage (e.g., by over-riding the speaker protection path over-driving the speaker), there may be paths or gain settings that are guaranteed to be unalterable in the end product.

There may be a sudden change in gain or enable/disable path when transitioning from one use case to another, or when enabling or disabling a use case. To reduce audible artefacts (artifacts) during such changes, the mixing means may comprise circuitry to limit the ramp rate of any gain change to a preset or programmable ramp rate and may only allow gain changes near zero-crossing of the signal.

Thus, switching circuitry is provided which allows multiple processes to be processed at different sample rates in the mixer, thereby allowing for comprehensive and very flexible processing of audio or other signals.

Fig. 56 shows an electronic device 1000, which may be, for example, an industrial device, a professional device, or a consumer device, and which contains a switching circuit 1002 having a plurality of signal sources and signal destinations as described above, and at least one mixer to which the signal sources and signal destinations may be connected on a time division multiplexed basis to establish signal paths. The switching circuit is implemented as an integrated circuit having a first digital interface 1004. Within device 1000, a first digital interface 1004 is operatively coupled to another integrated circuit 1006 to receive and/or provide digital signals to and/or from the other integrated circuit. The other integrated circuit 1006 includes, in whole or in part, a memory device, a short-range wireless device, and/or a long-range wireless device.

Fig. 57 shows an electronic device 1010, which may be, for example, an industrial device, a professional device, or a consumer device, and which contains a switching circuit 1012 having a plurality of signal sources and signal destinations as described above, and at least one mixer to which the signal sources and signal destinations may be connected on a time division multiplexed basis to establish signal paths. The switching circuit is implemented as an integrated circuit having a first digital interface 1014 and a second digital interface 1016. Within device 1010, a first digital interface 1014 is operatively coupled to first further integrated circuit 1018 for receiving and/or providing digital signals to and/or from the first further integrated circuit. Similarly, second digital interface 1016 is operatively coupled to second further integrated circuit 1020 for receiving and/or providing digital signals to and/or from the second further integrated circuit. The first further integrated circuit 1018 and the second further integrated circuit 1020 each comprise, in whole or in part, a memory device, a short-range wireless device, and/or a long-range wireless device.

Fig. 58 shows an electronic device 1030, which may be, for example, an industrial, professional, or consumer device, and contains a switching circuit 1032 as described above having multiple signal sources and signal destinations, and at least one mixer to which the signal sources and signal destinations may be connected on a time division multiplexed basis to establish signal paths. The switching circuit is implemented as an integrated circuit having a first digital interface 1034, a second digital interface 1036, and a third digital interface 1038. Within device 1030, a first digital interface 1034 is operatively coupled to a first further integrated circuit 1040 for receiving and/or providing digital signals to and/or from the first further integrated circuit, a second digital interface 1036 is operatively coupled to a second further integrated circuit 1042 for receiving and/or providing digital signals to and/or from the second further integrated circuit, and a third digital interface 1038 is operatively coupled to a third further integrated circuit 1044 for receiving and/or providing digital signals to and/or from the third further integrated circuit. The first further integrated circuit 1040, the second further integrated circuit 1042 and the third further integrated circuit 1044 each comprise, in whole or in part, a memory device, a short-range wireless device and/or a long-range wireless device.

Fig. 59 shows a communication device 1060 that includes a switching circuit 1062 as described above with multiple signal sources and signal destinations that can be connected to the mixer on a time division multiplexed basis to establish signal paths, and at least one mixer. The switching circuit is implemented as an integrated circuit having a first digital interface 1064. Within device 1060, first digital interface 1064 is operatively coupled to another integrated circuit 1066 to receive and/or provide digital signals to and/or from the other integrated circuit. The further integrated circuit 1066 comprises, in whole or in part, one or more of the following: an application processor, a wireless codec, or a communication processor.

Fig. 60 shows a communication device 1070 that contains a switching circuit 1072 as described above having a plurality of signal sources and signal destinations that can be connected to the mixer on a time division multiplexed basis to establish signal paths, and at least one mixer. The switching circuit is implemented as an integrated circuit having a first digital interface 1074 and a second digital interface 1076. Within device 1070, a first digital interface 1074 is operatively coupled to a first further integrated circuit 1078 for receiving and/or providing digital signals to and/or from the first further integrated circuit. Similarly, second digital interface 1076 is operatively coupled to second further integrated circuit 1080 for receiving and/or providing digital signals to and/or from the second further integrated circuit. The first further integrated circuit 1078 and the second further integrated circuit 1080 each comprise, in whole or in part, one or more of the following: an application processor, a wireless codec, or a communication processor.

Fig. 61 shows a communication device 1090 that includes a switching circuit 1092 having a plurality of signal sources and signal destinations as described above, and at least one mixer to which the signal sources and signal destinations can be connected on a time division multiplexed basis to establish signal paths. The switching circuit is implemented as an integrated circuit having a first digital interface 1094, a second digital interface 1096, and a third digital interface 1098. Within device 1090, first digital interface 1094 is operatively coupled to first further integrated circuit 1100 for receiving and/or providing digital signals thereto and/or therefrom, second digital interface 1096 is operatively coupled to second further integrated circuit 1102 for receiving and/or providing digital signals thereto and/or therefrom, and third digital interface 1098 is operatively coupled to third further integrated circuit 1104 for receiving and/or providing digital signals thereto and/or therefrom. The first further integrated circuit 1100, the second further integrated circuit 1102 and the third further integrated circuit 1104 each comprise, in whole or in part, one or more of the following: an application processor, a wireless codec, or a communication processor.

In this disclosure, it should be appreciated that various components have been illustrated. While one such component is shown and described, it should be noted that it can be replaced with multiple components that provide the same overall functionality, and similarly, while the functionality is shown as being distributed among different blocks for ease of illustration, this functionality can also be provided in a single component.

Reference herein to "scaling" of signals may refer to increasing or decreasing the magnitude (magnitude) or value (value) of such signals, and does not exclude the possibility that these signals may be left unchanged.

It will be appreciated that although certain elements of the disclosure have been described in combination for clarity and ease of understanding, these elements may be used independently of each other and the features shown and described may be used separately or in any combination.

The present disclosure relates generally to circuits that may be implemented as integrated circuits, although different aspects of the circuits may be implemented in hardware, firmware, software, or any combination thereof. For example, the invention may be embodied in a hardware description language provided on a computer readable carrier.

While particular embodiments of the present invention have been shown and described, it will be obvious that various changes may be made therein without departing from the scope of the present invention.

Claims

1. An integrated circuit, comprising:

a digital mixing kernel comprising a plurality of signal sources and signal destinations; and

at least one mixer to which the signal source and the signal destination can be connected on a time division multiplexed basis to establish a signal path,

wherein the or each mixer operates at a clock frequency;

and wherein:

here:

m_jthe number of mixers running at the jth mixer clock frequency,

C_R,jis the jth mixer clock frequency in use,

S_R,iis the ith sample rate in use in the system,

N_s,iis the number of signal sources providing data at the ith sample rate, and

2. An integrated circuit according to claim 1, wherein the or each mixer clock frequency is less than a quarter of the clock frequency necessary to be able to establish a signal path between each signal source and each signal destination at the respective sampling rate during a period.

3. An integrated circuit according to claim 2, wherein the or each mixer clock frequency is less than one tenth of the clock frequency necessary to be able to establish a signal path between each signal source and each signal destination at the respective sampling rate during a period.

4. An integrated circuit according to claim 3, wherein the or each mixer clock frequency is less than forty-one times the clock frequency necessary to be able to establish a signal path between each signal source and each signal destination at the respective sampling rate during a period.

5. An integrated circuit according to claim 4, wherein the or each mixer clock frequency is less than one hundredth of the clock frequency necessary to be able to establish a signal path between each signal source and each signal destination at the respective sampling rate during a period.

6. An electronic device comprising the integrated circuit of any of claims 1-5.