CN103703751B - Data signal route circuit - Google Patents

Abstract

A kind of integrated circuit is used for data signal route.The integrated circuit has analog- and digital- input and output, comprising the digital interface for being connected to other integrated circuits.Data source is served as in input comprising digital interface.Data destination is served as in output comprising digital interface.The integrated circuit also includes signal processing blocks, and the signal processing blocks can serve as data source and data destination.Signal route realizes that this multiplies accumulating block and data are extracted from one or more data sources, and after any required scaling, generates the output data for data destination by block is multiplied accumulating.Data from data source are buffered the whole cycle up to data sampling clock, data are obtained to allow that this multiplies accumulating block any point in this period, and the output data for multiplying accumulating block is buffered the whole cycle up to the data sampling clock, to allow that the data destination any point in this period obtains the data.By user or software by being supplied to the configuration data of the equipment, multiple signal paths can be limited.This multiplies accumulating block and is run on the basis of time division multiplex, to cause that multiple signal paths can be processed in a cycle of the sampling clock.Each signal path has corresponding sampling clock rate, and the path with different sampling clock rates can multiply accumulating block and be route independently of one another on the basis of time division multiplex by this.Therefore, the voice signal in 8kHz or 16kHz can concurrently be processed with the voice data in 44.1kHz or 48kHz.

Description

Data signal route circuit

The present invention relates to signal routing circuit, can especially be used as the signal routing circuit of DAB hub, For by consumer device（Wherein smart phone is an example）In multiple signal sources and signal destination interconnection.

The integrated circuit of " audio hub " is served as in known offer, and it can receive some letters from simulation source and digital source Number, data signal is converted analog signals into, the signal is then combined or processed in the digital domain, to generate output signal.Such as Fruit requires that then the output signal can be converted into analog signal by audio hub, to be applied to simulation transducer（Such as ear Machine（headphone）Or loudspeaker（speaker））.Such DAB hub device can be included into consumer device （Such as smart phone or the like）, so as to allow the signal for receiving to be processed in a predefined manner.

Desirably, it is allowed to should the consumer of " audio hub " integrated circuit use it to consumer with flexi mode Some unlike signal processing components interconnection in equipment, and it is not only restricted to specific external equipment or particular procedure path.

The present invention is defined by the appended claims.

For a better understanding of the present invention, and in order to show how it can implement, will refer to by way of example now Accompanying drawing, wherein：

Fig. 1 shows a mobile phone and multiple ancillary equipment；

Fig. 2 a show the part of the audio frequency processing circuit system in the mobile phone of Fig. 1；

Fig. 2 b show the part of the audio frequency processing circuit system in a mobile phone for replacement；

Fig. 3 is the first more detailed block diagram, shows the audio hub in the audio frequency processing circuit system of Fig. 2 a or 2b The form of routing circuit system；

Fig. 4 is again more detailed block diagram, shows the preconditioning in the routing circuit system of Fig. 3（pre- conditioning）The form of circuit system；

Fig. 5 is further more detailed block diagram again, shows the shape of the SWITCHING CIRCUITRY in the routing circuit system of Fig. 3 Formula；

Fig. 6 is further more detailed block diagram again, shows of the SWITCHING CIRCUITRY in the routing circuit system of Fig. 3 The form of individual replacement；

Fig. 7 is further more detailed block diagram again, show in the routing circuit system of Fig. 3 to down-sampling（down- sampling）The form of circuit system；

Fig. 8 is further more detailed block diagram again, show in the routing circuit system of Fig. 3 to up-sampling（up- sampling）The form of circuit system；

Fig. 9 is further more detailed block diagram again, shows the rear regulation in the routing circuit system of Fig. 3（post- conditioning）The form of circuit system；

Figure 10 is further more detailed block diagram again, shows the digital mixed nucleus in the routing circuit system of Fig. 3 （digital mixing core）Form；

Figure 11 illustrates in greater detail a part for the One function block in the digital mixed nucleus of Figure 10；

Figure 12 illustrates in greater detail a part for another functional block in the digital mixed nucleus of Figure 10；

Figure 13 illustrates in greater detail a part for another functional block in the digital mixed nucleus of Figure 10；

Figure 14 is another block diagram, shows the digital mixed nucleus of Figure 10, and shows the more thin of multiple functional blocks Section；

Figure 15 is a block diagram, exemplified with a different aspect of the digital mixed nucleus in an embodiment；

Figure 16 is a block diagram, exemplified with another embodiment in digital mixed nucleus different aspect；

Figure 17 is a block diagram, exemplified with further embodiment in digital mixed nucleus different aspect；

Figure 18 is a block diagram, exemplified with still another embodiment in digital mixed nucleus different aspect；

Figure 19 is a block diagram, exemplified with still another embodiment in digital mixed nucleus different aspect；

Figure 20 is a block diagram, exemplified with a part for the digital mixed nucleus in an embodiment；

Figure 21 is a block diagram, exemplified with another embodiment in digital mixed nucleus a part；

Figure 22 is a block diagram, exemplified with a multiply-accumulate block in digital mixed nucleus（multiply-accumulate block）A form；

Figure 23 is a block diagram, and a form for replacement of the multiply-accumulate block in digital mixed nucleus is illustrated in more detail；

Figure 24 is a flow chart, exemplified with the treatment performed in blender；

Figure 25 is another illustration for the treatment shown in Figure 24；

Figure 26 is the first timing diagram, exemplified with the treatment of Figure 24；

Figure 27 is the second timing diagram, exemplified with the more details of the treatment of Figure 26；

Figure 28 is the 3rd timing diagram, exemplified with the treatment that another is substituted；

Figure 29 is the 4th timing diagram, exemplified with the treatment that still another is substituted；

Figure 30 is a flow chart, exemplified with a method of the operation for limiting SWITCHING CIRCUITRY；

Figure 31 is a diagram of computer screenshotss, exemplified with a stage in the method for Figure 30；

Figure 32 is a block diagram, shows the use example that the treatment of Figure 30 is limited（usecase）In route；

Figure 33 is a register mappings（map）, exemplified with the original state of the register banks in the treatment of Figure 30；

Figure 34 is a block diagram, there is provided of route in the use example of the Figure 32 on the digital mixed nucleus of Figure 14 The illustration of replacement；

Figure 35 is a register mappings, exemplified with a shape of register banks at another point in the treatment of Figure 30 State；

Figure 36 is a diagram of digital mixed nucleus, shows the functional block being related in the use example shown in Figure 32；

Figure 37 a show a route in another use example；

Figure 37 b show a route in still another use example；

Figure 38 is a timing diagram, is calculated exemplified with the First Series in the treatment performed in blender；

Figure 39 is a timing diagram, is calculated exemplified with the second series in the treatment performed in blender；

Figure 40 is a timing diagram, is calculated exemplified with the 3rd series in the treatment performed in blender；

Figure 41 is a timing diagram, is calculated exemplified with the 4th series in the treatment performed in blender；

Figure 42 is a timing diagram, is calculated exemplified with the 5th series in the treatment performed in blender；

Figure 43 is a block diagram, exemplified with on-off circuit in a clock generator；

Figure 44 is a block diagram, exemplified with the another aspect of the clock generator；

Figure 44 a are a block diagrams, exemplified with a form for replacement of the clock generator；

Figure 44 b are a block diagrams, exemplified with the form of another replacement of the clock generator；

Figure 44 c are a block diagrams, exemplified with the another aspect of multiple forms for substituting of the clock generator；

Figure 45 is a block diagram, exemplified with according to embodiment blender；

Figure 46 is a flow chart, exemplified with the first method performed in the blender of Figure 45；

Figure 47 is a flow chart, exemplified with the second method that the blender in Figure 45 is performed；

Figure 48 is a flow chart, exemplified with the third method that the blender in Figure 45 is performed；

Figure 49 is a block diagram, and the enable and clock control block of the blender of Figure 45 is illustrated in more detail；

Figure 50 is a flow chart, the method performed in the enable and clock control block exemplified with Figure 49；

Figure 51 is a flow chart, another method performed in the enable and clock control block exemplified with Figure 49；

Figure 52 a are a block diagrams, and the channel scheduler in the blender of Figure 45 is illustrated in more detail（channel scheduler）；

Figure 52 b are a flow charts, the method exemplified with being performed in the channel scheduler of Figure 52 a；

Figure 53 is a flow chart, exemplified with another method performed in the channel scheduler of Figure 52 a；

Figure 54 is a block diagram, and the calculating block of the blender of Figure 45 is illustrated in more detail；

Figure 55 is a flow chart, the method for calculating execution in block of the channel scheduler block and Figure 54 exemplified with Figure 52 a A part；

Figure 56 is a schematic diagram, exemplified with a part for electronic equipment according to an aspect of the present invention；

Figure 57 is a schematic diagram, exemplified with a part for the second electronic equipment according to an aspect of the present invention；

Figure 58 is a schematic diagram, exemplified with a part for the 3rd electronic equipment according to an aspect of the present invention；

Figure 59 is a schematic diagram, exemplified with a part for the 4th electronic equipment according to an aspect of the present invention；

Figure 60 is a schematic diagram, exemplified with a part for the 5th electronic equipment according to an aspect of the present invention；And And

Figure 61 is a schematic diagram, exemplified with a part for the 6th electronic equipment according to an aspect of the present invention.

Fig. 1 shows a consumer device according to an aspect of the present invention, is in this embodiment mobile electricity Words 1, the more specifically form with smart phone.In this embodiment, mobile phone 1 has screen 3 and keyboard 5, although Certainly the equipment present invention is equally applicable to carry touch screen or other users interface.Mobile phone 1 also has the He of boombox 7 Built-in main microphone 9, they are all simulation transducers.Mobile phone 1 also has multiple microphones, in this embodiment It is four microphones 11（They can be analog or digital microphone）, so that allow multiple ambient noise signals to be received, example As being used for being used in noise canceling system.

As shown in fig. 1, mobile phone 1 can have socket with holes（jack socket）（Do not illustrate）Or similar company Connection device, such as USB or multi-pin connector socket（multi-pin connector socket）, so as to allow head-mounted machine （headset）The mobile phone is connected by electrical wiring to, the head-mounted machine includes a pair of stereo headsets 13 and possibly wraps Include microphone 15.Alternatively, mobile phone 1 can be with --- for example use bluetooth（Trade mark）Communication protocol --- it is wirelessly connected to nothing Line head-mounted machine 17, head-mounted machine 17 that this is wireless has earplug 19 and possibly has microphone 21.Although not illustrating, earplug 13rd, 19 can include one or more environmental noise microphones（They can be analog or digital microphone）, so as to allow one Individual or multiple ambient noise signals are received, such as in noise canceling system.

Alternatively or additionally, mobile phone 1 can have socket or similar attachment means, so as to allow it to be connected To external audio system 23, such as, for music playback, the system includes one or more loudspeakers 25.External audio system 23 May, for example, be Table top type stereo component system, or in-car audio system.The circuit system of external audio system 23 （circuitry）27 can include radio receiver or other audio-sources, and it can provide audio input to mobile phone 1, To allow radio or other audios by loudspeaker 7 or earplug 13,19 playbacks by a selected head-mounted machine. Alternatively, music of the storage on the phone can be by the playback of loudspeaker 25 of external audio system 23.

It can therefore be seen that many possible audio signals can be output.If for example, mobile phone 1 has allowed It is coupled to the docking station in motor vehicles（docking station）Connector and equipped with satellite navigation system, then move Mobile phone 1 may be required to simultaneously：（a）Mobile phone session is manipulated via wired or wireless hand-held set；（b）From depositing for it Reservoir provides stereo music to external audio system 23；And（c）There is provided via boombox and pressed for ACK button Tone and navigation instruction is provided.As a result, according to above-described embodiment, the SWITCHING CIRCUITRY in mobile phone 1 is allowed for Manipulate at least these three discrete output voiceband data signals, and the input audio data letter for manipulating the mobile phone session Number.

Fig. 2 a show the part of the audio steerable system in mobile phone 1.Communication with cellular phone network 29 is by base Provided with processor（Sometimes referred to as communication processor）31 manipulate.Application processor 33 is manipulated from memory 35（It can be solid-state Or on disk, and it can be built-in or be attached, such as good and all in the mobile phone or removable Memory devices on）The middle treatment for reproducing voice data stores to the treatment in memory 35 voice data, and its He internally generates the treatment of voice data, and other treatment in phone 1.For example, application processor 33 can manipulate numeral The reproduction of stereo music of the ground storage in memory 35, can manipulate telephone conversation and other voice datas to memory 35 In record, and also will manipulate satellite navigation order generation and manipulate tone generation with confirm on keyboard 5 appoint The pressing of what button.Wireless transceiver（Or wireless coding and decoding device）37 use bluetooth（Trade mark）Agreement or other short-range communication protocols Communication is manipulated, such as with wireless head-mounted machine 17.

BBP 31, application processor 33 and wireless transceiver 37 are all to the on-off circuit of the form of audio hub 39 System sends voice data, and receives voice data from the SWITCHING CIRCUITRY of the form of audio hub 39.Audio hub Integrated circuit form is taken in 39 embodiment described by this.In the above-described embodiment, audio hub 39 and base Audio signal between provided with processor 31, application processor 33 and wireless transceiver 37 be all it is digital, and in them one Can be a bit stereosonic, including left data flow and right data flow.Additionally, at least in situation about being communicated with application processor 33 Under, other data flow can be re-used（multiplexed）To in these audio signals, such as with so that application processor 33 Stereo music can be provided, while also providing other audio signals, such as button confirms tone.

Audio hub 39 is via corresponding voice data link（That is, bus 38b, 38a, 38c）With BBP 31, Application processor 33 and wireless transceiver 37 communicate, and audio hub 39 has the corresponding number for these data link Word interface 40b, 40a, 40c.

Audio hub 39 also provides audio signal to the built-in analog audio-frequency transducer of mobile phone 1, and from movement The built-in analog audio-frequency transducer of phone 1 receives audio signal.As shown in Figure 2, audio hub 39 provides defeated to loudspeaker 7 Go out audio signal, and input audio signal is received from microphone 9,11.

Audio hub 39 can also be connected to other output transducers 43, and output transducer 43 can be simulated or number Word transducer, and mobile phone 1 can be built into（For example in the case of tactile output transducer）Or mobile phone 1 Outside equipment（The earplug 13 of the wired head-mounted machine for for example in Fig. 1 showing）.Audio hub 39 can also be connected to other Input transducer 45, input transducer 45 can also be analog or digital transducer, and can also be built into mobile phone 1 （Such as ultrasonic microphone）Or the equipment outside mobile phone 1（The microphone 15 of such as wired head-mounted machine）.

Audio hub 39 can also be required from other sources（Such as FM radio receivers 41）Signal is received, this other Source in external audio system 23, or be able to can be set on discrete IC in a mobile telephone 1, and can be generated Analog or digital signal.

It will be appreciated that Fig. 2 shows the possible purposes of the only one of audio hub 39, but audio of the invention Hub integrated circuit can be used in extremely wide in range various electronic equipments, comprising industrial equipment, professional equipment or consumption Person's equipment, such as video camera（DSC and/or video recorder）, portable media player, PDA, game machine, satellite navigation, flat board Computer, notebook, television set or the like.

Audio hub integrated circuit can be optimized for various industrial equipments, professional equipment or consumer and set A specific category in standby.For example, although fig 1 illustrate that a concrete form of smart phone 1, but it should be appreciated that other Smart phone model by the function with varying level, therefore by with different audio Control requirements, and the audio line concentration Device integrated circuit is designed to this kind of various requirements of reply.As described below, the quilt of audio hub 39 In optimizing for smart phone, but can also be used in the various smart phones with different audio operation requirements.

Under any circumstance, even if audio hub integrated circuit has been optimized for a class consumer device（Such as Smart phone）In, it also by most probably available in a series of consumer device of types because each signal represent it is assorted It is unknowable.The number and the number of type and signal processing blocks of the interface provided in the audio hub integrated circuit Can choose whether to manufacture a life with the Type Range that type will determine the consumer device that it will can be used for, and manufacturer Produce possible less expensive audio hub integrated circuit（Because it has limited function but is designed for one well Individual specific purposes）, or whether manufacture with more powerful therefore the audio hub collection of many different purposes can be used for Into circuit.

Fig. 2 b show the part of the audio steerable system in a mobile phone for replacement.Again, with cell phone The communication of network 29 is by BBP（Or communication processor）31 are manipulated, and application processor 33 is manipulated from memory 35 Middle reproduction voice data stores to the treatment in memory 35 voice data, and manipulates other inside in phone 1 Generate the treatment of voice data.For example, application processor 33 can manipulate the stereo music being digitally stored in memory 35 Reproduction, can manipulate in telephone conversation and other audio data recordings to memory 35, and will also manipulate satellite navigation The generation of order and the generation of tone is manipulated to confirm the pressing of any button on keyboard 5.In the mobile electricity that this is substituted In words, in the absence of wireless coding and decoding device.As a result, audio hub 39a needs only have the first digital audio interface 40a and second Digital audio interface 40b, application processor 33 may be connected to the first digital audio interface 40a, and communication processor 31 can be with It is connected to the second digital audio interface 40b.Audio hub 39 as shown in Figure 2 can be readily used in this replacement Mobile phone in.However, it is sufficient that audio hub 39a has only two digital audio interfaces, and may be than having The audio hub of three digital audio interfaces is smaller and less expensive.

Although herein with reference to " audio signal ", the electric signal manipulated by " audio hub " integrated circuit can generation Any physical phenomenon of table.For example, term " audio signal " can not only mean to represent the signal of the audible sound of human ear（For example In the frequency range of 20Hz to 20kHz）, and can mean from and/or go to the input and/or output of tactile transducer Signal（Generally in below 20Hz or at least in the frequency of below 300Hz）, and/or from and/or go to ultrasonic transducer Input and/or output signal（For example in the frequency range of 20kHz to 300kHz）And from/or go to infrasonic sound and change The input of energy device and/or output signal（Generally in the frequency of below 20Hz）.It is possible that " audio hub " can not be received Any audio signal in the audible scope of human ear, such as " audio collection special in the design or in specifically used example Line device " can only receive " audio signal " relevant with tactile or ultrasonic signal.

Fig. 3 is a block diagram, illustrates in greater detail the form of the audio hub or routing circuit 39.In this situation Under, the audio hub or routing circuit are optimized in the equipment of such as smart phone, and will be described accordingly, but It will be appreciated that this circuit for illustrating only is one embodiment of routing circuit of the invention, and it is described in intelligence Purposes in phone is only a possible purposes of illustrated circuit.Therefore, the audio line concentration utensil has audio coding decoding The function of device, receives in a voice data for form, and is processed, and is processed into if asked not Same form.

Audio hub routing circuit 39 serves as at audio codec, and the audio based on the form of digital mixed nucleus 50 Reason engine（audio processing engine）, such as being input into and defeated in the multiple of audio hub routing circuit 39 Signal route is provided between going out（Single output will be mixed into comprising the audio signals that will be input into from multiple）, and for providing letter Number processing function.These signal processing functions can include it is following in some or all：Loudspeaker strengthens, such as many band compressions （multi-band compression）, virtual surround sound（Stereophonic widening）Or the non-thread of compensation loudspeaker or equipment performance Property；Voice（voice）Path strengthens, and such as adaptive environment noise is eliminated, language（speech）Definition enhancing, transmitted noise Elimination, echo cancellor or sidetone（sidetone）Filtered with wind noise；Or digital mixed function, such as completely flexible Signal route, volume control and the conversion of soft noise suppressed, equilibrium, dynamic range control, programmable filtering and sample rate.

Audio hub routing circuit 39 have some digital audio interfaces 52.1 ..., 52.N, they are intended to be connected To other circuits in the equipment, and the letter of signal or supply from digital mixed nucleus 50 is supplied to digital mixed nucleus 50 Number.The number of digital audio interface can be based on its expected use scope and be chosen in the during the design of the audio hub Select.In of the invention this is optimized for the embodiment of the equipment of such as smart phone, exist：First DAB connects Mouthful, it is primarily intended for being connected to application processor 33；Second digital audio interface, it is primarily intended for being connected to base band Processor 31；And the 3rd digital audio interface, it is primarily intended for being connected to wireless transceiver 37.Digital audio interface 52.1st ..., 52.N can be interchangeable, but an interface can advantageously be made and be significantly wider than other interfaces, with So that the expection that it may be connected in multiple processors is needed to the full extent while accessing at of the routing circuit Reason device.

Such as digital camera is optimized at one of the invention（digital still camera）Equipment In embodiment, there may be only one digital audio interface；Such as simple telephone is optimized at one of the invention （simpler phone）（Wherein wireless transceiver functionality can not be required, or can be performed by such as BBP）'s In the embodiment of equipment, there may be only two digital audio interfaces（As shown in figure 2b）.One embodiment is likely to There is no digital audio interface.Compare, be intended to for home theater in the embodiment of acoustic equipment at one of the invention, There may be such as six or more digital audio interfaces.Term " COBBAIF " also should be understood to cover for example for Carry other similar data flows（Such as ultrasound or haptic data）Interface.

Audio hub routing circuit 39 also has pre-regulating circuit system 54, for receiving analog input signal, for example From simulation input transducer（Such as microphone）56 receive analog input signal, and with simulation FM radio receivers 58. For these digital interfaces, the number of simulation input can be based on the expection of routing circuit in the during the design of the audio hub It is chosen using scope, and an embodiment may be without analog interface.

One or more simulation input transducers can be touch screen form, and it for example can be received from the user of the equipment Input, and these inputs are sent to a processor of the equipment via one of digital audio interface, to cause the treatment Device can generate the control signal of one or more operation characteristics for the equipment.

Signal from pre-regulating circuit system 54 is sent to SWITCHING CIRCUITRY 60, and SWITCHING CIRCUITRY 60 is also received Digital input signals, such as from numeral input transducer（Such as digital microphone）62 receive digital input signals.

SWITCHING CIRCUITRY 60 is connected to downward sampling circuitry 64, and from downward sampling circuitry 64 Digital mixed nucleus 50 is fed into the signal of down-sampling, the digital mixed nucleus 50 is described in more detail below.

Output signal from digital mixed nucleus 50 is sent to upward sampling circuitry 66, and to the letter of up-sampling Some in number adjust circuit system 68 after being sent to, and the rear regulation circuit system 68 is connected to lead-out terminal, simulates defeated Go out transducer（Such as loudspeaker（loudspeaker））70 may be connected to these lead-out terminals.

Other signals extracted from upward sampling circuitry 66 are also sent to digital output format block 72, for even Suitable transducer 74 is connected to, the numeral input amplifier being such as connected with long-range loudspeaker.For example, digital output format block These signals can be become stereo pulse density modulated by 72（Stereo Pulse Density Modulation） （SPDM）Form.

As before, the number of analog and/or digital output can be based on the routing circuit it is expected using scope come Design, and an embodiment may not have analog or digital output interface.These simulation outputs can be used to stand in pairs Body voice output, or can be used alone.Different simulation outputs is optimized for different purposes, such as in earphone In or speaker cabinet（speaker cabinet）The load of the middle loudspeaker for using, and for being for example grounded or difference（H bridges） Loudspeaker.

The audio hub routing circuit 39 of this specific embodiment also includes low latency（latency）Process block 90, it is connected directly to receive data signal from the output of SWITCHING CIRCUITRY 60, and via adder 92.1 ... From upward sampling circuitry 66 be sent on outlet line output signal by 92.P.Low latency process block 90 may be adapted to Specific signal processing function is provided, for should not be restricted by any unnecessary delay（That is drawn by digital mixed nucleus 50 Any additional delay for rising, no matter how small the delay is）Signal.In this embodiment for illustrating, low latency Process block 90 includes digital filter, and they can be self adaptation, in feed-forward noise elimination system.In this reality In applying scheme, because these input signals were extracted before downward sampling block, so the sample rate of data flow with associate Signal transacting is with the sample rate much higher than the signal transacting in digital mixer core（E.g. common 48kHz sample rates 8 times or even 64 times, i.e. 384kHz or 3.072MHz）Carry out, such that it is able to more easily realize low latency.

That is, one or more microphones can be used to generate in the region for representing the equipment（For example in hand-held set or head In wearing machine）Ambient noise signal.These signals are filtered, and one or more loudspeakers can be sent to generate（It is logical Often in same hand-held set or head-mounted machine）Output signal, with cause these signals produce but phase equal with ambient noise amplitude Position is opposite（So as to have negative function）Sound.In order that the system optimization ground work of this type, signal transacting cost Time should be substantially equal to sound wave and be transmitted through the time that the equipment is spent, it can therefore be seen that any etc. in the signal transacting Treat how the time all will optimally work the system with influence.

In this embodiment, there is connection between digital mixed nucleus 50 and low latency process block 90, for example, make Obtain the sef-adapting filter in low latency process block 90（For example in feed-forward noise elimination system）Can be mixed from numeral Synkaryon 50 is controlled, and the result that can be based on the signal transacting of digital mixed nucleus 50 is controlled.

Audio hub routing circuit 39 also includes control interface 100, for for example from in the equipment Reason device integrated circuit（Typically application processor 33）Receive control signal.These control signals can for example to routing circuit 39 The running status of the outfit of equipment is notified, such as which function is activation.

Audio hub routing circuit 39 also includes clock generator 80, for receiving master clock（master clock）Letter Number and generate system clock, as described in more detail below.In this embodiment for illustrating, clock generator 80 connects Receive Q master clock signals and generate R system clock.For example, in the case of smart phone, whenever the circuit relevant with the phone When system is activated, the master clock signal of the frequency in 13MHz can be available, but work as the circuit relevant with the phone not It is activated（Such as in such as " flight safety pattern "）When, the 13MHz clocks can be disabled, and when unique available Clock can be 32kHz crystal oscillators.

Multiplexer 84 is also sent to from the data signal of the output of upward sampling circuitry 66, the multiplexer 84 can be selected One or more in these output signals for waiting to be fed back are selected as the input to digital mixed nucleus 50.The signal for being fed back can To be used for such as echo cancellor.

Fig. 4 is one of the pre-regulating circuit system 54 in the audio hub routing circuit 39 of this embodiment more detailed Thin block diagram.

As described above, pre-regulating circuit system 54 have some inputs, for receiving analog input signal, for example from Simulation input transducer 56, fremodyne circuit 58 or the like receive analog input signal.These input in each A corresponding presetting locking nub 138, including amplifier 140 are connected to, wherein resulting amplified signal is sent to One corresponding analogue-to-digital converters（ADC）142.This illustrate embodiment in analogue-to-digital converters 142 be Sampling（over-sampling）ADC, such as delta-sigma（delta-sigma）ADC.The gain of each amplifier 140 Can be independently controlled by writing suitable value to the register on the chip.

Fig. 5 is one of the SWITCHING CIRCUITRY 60 of the audio hub routing circuit 39 of this embodiment more detailed Block diagram.If the SWITCHING CIRCUITRY receives the preregulated signal of xeromenia from pre-regulating circuit system 54, these signals are these moulds Intend the digitized version of input signal.Each is sent to the first input of multiplexer 160 through preregulated signal, and each is answered The corresponding digital input signals received from numeral input transducer 62 are coupled to receive with the second input of device 160.

External component is then typically attached to routing circuit 39, to cause, is given in locking equipment used in one, or at least exist Any one moment, each multiplexer only from one of simulation input or from one of numeral input receive signal, but preferably not from Both of which receives signal.The input signal for depending on audio hub routing circuit 39 be simulation or numeral or The mixing of both, multiplexer 160 can be controlled such that suitable signal is selected as through switching（switched） Digital output signal.

Fig. 5 shows an implementation method, wherein the connection for numeral input transducer 62 is believed with for simulation input Number connection number it is identical（Such as M）, therefore there is M multiplexer 160, each multiplexer 160 is from these simulation inputs One of receive signal and from one of these numeral inputs receive signal.

Fig. 6 is a more detailed block diagram, shows SWITCHING CIRCUITRY 60 in audio hub routing circuit 39 One form of replacement.As in Figure 5, it is corresponding that each digitized versions of these analog input signals is sent to one First input of multiplexer 160.

In that case, M（M-bit）The digital input signals of combination wide are sent to some M bit multiplexs devices 164, the output of the corresponding multiplexer in the multiplexer 164 is connected to the second input of each switch 160.Multiplexer 164 be controlled such that they select the digital input signals of the combination these in corresponding one, and switch 160 Controlled as described above, to select the digitized version or the digital input signals of the analog input signal electric as switch The output signal of road system 60.

Although being illustrated as single cable data stream, input digital data stream or digitized data flow can be multidigits , either as parallel bus or as serial multi-bit data stream, and can be time-multiplexed on a single bus （time-multiplexed）, the follow-up adjustment with the structure to these multiplexer blocks.

Fig. 7 is a more detailed block diagram, shows the downward sampling circuitry in audio hub routing circuit 39 64 possible form.

Each signal output from SWITCHING CIRCUITRY 60 is sent to one accordingly to down-sampler 170, to generate One corresponding downsampled signal.This can for example include digital filter to down-sampler 170, such as with different inputs The FIR filter or iir filter of sample rate and output sampling rate.

Herein, as described above, analogue-to-digital converters 142 are over-sampling ADC, can be by down-sampler 170 These data signals are transformed into compared with low sampling rate, can easily by the signal transacting electricity in digital mixed nucleus 50 compared with low sampling rate Road system treatment, although be used to avoid increased quantizing noise with larger bit width.

Fig. 8 is a more detailed block diagram, shows the upward sampling circuitry in audio hub routing circuit 39 66 possible form.

Each signal output from digital mixed nucleus 50 is sent to a corresponding upsampler 180, to generate The one corresponding signal to up-sampling.Upsampler 180 can for example take the form of digital filter, such as FIR filtering Device or iir filter.

Fig. 9 is a more detailed block diagram of the rear regulation circuit system 68 in audio hub routing circuit 39.

Regulation circuit system 68 has some inputs afterwards, and each is input into for the upward of the generation of upward sampling circuitry 66 One of signal of sampling, and each input is all connected to corresponding rear regulating block 188.

Each rear regulating block 188 includes respective digital-analog convertor 190, and resulting analog signal is passed A corresponding amplifier 192 is sent to, and resulting amplified signal is output.Amplifier 192 can provide single-ended （single-ended）Output（As shown in Figure 9）Or difference output, and they can be any amplifier for facilitating type, Such as A/B classes, D classes or G class A amplifier As, high power amplifier or high-voltage amplifier.

Figure 10 is another schematic diagram of audio hub routing circuit 39, and the first digital sound is shown in that case Frequency interface 52.1 and N digital audio interface 52.N, but only generally show pre-regulating circuit system 54, SWITCHING CIRCUITRY 60th, downward sampling circuitry 64, upward sampling circuitry 66, rear regulation circuit system 68 and digital output formatting block 72, and show the more details of digital mixed nucleus 50.

Specifically, digital mixed nucleus 50 includes multiple digital signal processing blocks, illustrated therein is the first Digital Signal Processing Block（DSP1）102 and N digital signal processing blocks（DSPN）112.Digital signal processing block 102,112 can be with the first example （instantiation）It is programmed, or by downloading DSP code of the storage on chip or outside chip, it is various each to perform The signal processing function of sample, but they can be optimized for execution concrete function.For example, at each programmable data signal Reason block can have many or polytype memory or dedicated computing hardware for allowing it to perform concrete function, Huo Zheke With with the special instruction group for being optimized for expectation function.The number of such programmable digital signal process block and its specific Characteristic may rely on the expected of audio hub 39 and is chosen using scope.In one embodiment, audio hub road It is that in smart phone, the first programmable digital signal process block can be used for by a feasible plan purposes of circuit 39 The voice signal in the transmitting path of the phone is processed, the second programmable digital signal process block can be used to process the phone RX path in voice signal, and the 3rd programmable digital signal process block can be used for process non-speech audio.

Furthermore it is possible to provide the signal processing blocks of the function of being optimized for more limited range.In the implementation that this is illustrated In example, also comprising completely programmable five band balanced devices, balanced device 118,120 is shown digital mixed nucleus 50 as two of which Go out, and digital mixed nucleus 50 also includes wave filter, and these wave filters are completely programmable, to allow that they have height Such wave filter 134 is shown in which in logical and/or lowpass function, and Figure 10.

Digital mixed nucleus 50 also includes dynamic range compression（DRC）Block 150.Be also show in Figure 10 can have it is some other Another functional block 154 of signal processing function.

Additionally, audio frequency process engine 50 includes upward sampling block 162 and downward sampling block 164, for in not Moved between domain with the signal of sample rate.For example, sampling block 162 and downward sampling block 164 are included upwards：Respective sample rate Conversion（SRC）Block, for being the speech processes domain of 8kHz or 16kHz and the audio frequency process domain of more generally 48kHz in sample rate Between change；And the SRC blocks for being changed between other integer ratios；And it is attached for what is changed between asynchronous sample rate Plus SRC blocks.

Although not shown in Figure 10, another feasibility is to provide the functional block of tone generator form, it exports tool There are the audio or haptic signal of predetermined properties, without requiring any input audio signal.Similarly, although not shown in Figure 10, Another feasibility is to provide the functional block for requiring audio input but not providing audio output, such as comprising being used for another block Little renewal asynchronous control signal block, such as other audio paths of noise suppressed or for almost without ring The signal level threshold detection signal that ambient noise is eliminated is disabled during the noise of border.

Thus provide the multiple functional blocks in digital mixed nucleus 50, and to digital mixed nucleus 50 signal input and come From the signal output of digital mixed nucleus 50.These are all by the hybrid component of digital mixed nucleus 50（mixing fabric）It is mutual Even, as described in more detail below.

From in terms of the visual angle of the hybrid component, to each signal input of digital mixed nucleus 50, and from these functions Each output, all representation signal source port of one of block.In Fig. 10, each in these signal source ports is by one Filled black is circular to be represented.

And, from terms of the visual angle of the hybrid component, each signal output from digital mixed nucleus 50, and arrive these Each input, all representation signal destination port of one of functional block.In Fig. 10, it is every in these signal destination ports One is all represented by a filled black rhombus.

Thus, in fig. 10 it can be seen that some functional blocks have an input, and other functions block has multiple defeated Enter.For example, balanced device 120 has an input 122, and DSP1102 has at least four inputs 104,106,108,110.This Mean that DSP1 can process at least four single input traffics.

Although described as single port, but these source ports and these destination ports can be multidigits, manipulate simultaneously OK（Such as 16 or 24）Or serial multi-bit data stream, and can be time-multiplexed in single connection.

Additionally, the hybrid component causes each signal destination port（That is, input for any functional block or from number The signal output of word mixed nucleus 50）All associated with a mixing " channel ", the mixed channel includes " the selector end of predetermined number Mouthful ", each selector port can be configured as receiving signal data from selectable signal source port.These channels or mixing Device element is illustrated as being docked with corresponding signal destination port in Figure 11 to Figure 13, wherein in these selector ports Each selector port is by a square representative of filled black.

Data unchanged simply can be delivered to corresponding destination port by some channels, but the hybrid component makes At least some in these channel outputting data signals streams can always from the mixing of the signal of signal source（May according to not Same corresponding zoom factor is scaled）In draw.This married operation performed by the channel for giving can be in different application Or in the different use examples of the audio hub be different.

Figure 11 to Figure 13 is exemplified with the hybrid component（It is shown with shade）Channel or mixer element multiple embodiments, The hybrid component is attached to the signal destination in multiple functional blocks.Each mixer element includes one or more selector ends Mouthful, each in the selector port can have single selected signal source with as described below being attached.

Figure 11 shows that functional block 170 has an input（It is destination port from terms of the visual angle of hybrid component）171 Situation.Figure 11（a）Show that the signal source that this input 171 can be from a selector port 172 receives signal, and And Figure 11（b）A more detailed view of same channel structure is shown, wherein the signal from one signal source can It is scaled with before input 171 is applied to.

Figure 12 shows that functional block 174 has two 175,176 and two corresponding channels of input or mixer element Situation.Figure 12（a）Show that two signal sources that input 175 can be from selector port 177,178 receive signal respectively, and And input 176 can be from selector port 179,180 two signal sources receive signal, and Figure 12 respectively（b）Show One more detailed view of same channel structure, wherein can applied from two signals of selector port 177,178 It is scaled and is added together before is added to input 175, and the signal from two selector ports 179,180 can be in quilt It is scaled and is added together before is applied to input 176.

Figure 13 shows that functional block 181 has a situation for input 182.Figure 13（a）Show that input 182 can be from four Individual signal source 183,184,185,186 receives signal, and Figure 13（b）Show that of same channel structure regards in more detail Figure, wherein the signal from this four signal source 183,184,185,186 can be scaled simultaneously before input 182 is applied to And be added together.

Therefore, Figure 14 is a somewhat more detailed version of Figure 10, shows the channel with multiple selector ports It is docked at each signal destination（That is, functional block and the signal output from the mixed nucleus）Corresponding destination port（Block Input）On.

For example, the input 122 of balanced device 120 can be from four on corresponding selector port 188,189,190,191 Signal source receives signal；And the input 104 of DSP1102 can be believed from three on corresponding selector port 192,193,194 Number source receives signal；The input 106 of DSP1102 can be from corresponding selector port 195,196 two signal sources receive Signal；The input 108 of DSP1102 can receive signal from selector port 197 a signal source；And DSP1102's Input 110 can receive signal from selector port 198 a signal source.

As mentioned above, the hybrid component allows the signal from any selected signal source to be routed to these letters Number destination, and be required to receive in individual signals destination in the case of the mixing of the signal from multiple signal sources by group Close.That is, the hybrid component allows user to be based on selecting any one criterion of applying by user selecting which signal source will quilt Which signal destination is connected to, without the limitation that the hybrid component itself is forced.

Using discrete adder and multiplier for each the signal destination in each functional block as shown, can Physically implement hybrid component as shown in Figure 14.However, in silicon entity（silicon real estate）, electric power and The aspect that control function is concentrated, is very advantageously embodied as single blender circuit by the hybrid component（Or possibly, it is right In more complicated system, some such blender circuits are embodied as, the wherein number of blender circuit is still much smaller than signal mesh Ground number）, and this circuit carried out between multiple destinations it is time-multiplexed, to cause it in each audio signal The requirement of the signal destination required by each is served in sampling period in turn.

Thus the hybrid component includes a blender（Or multiple blenders）, it believes on the basis of time division multiplex at these It is shared between number source and destination.That is, in a data sampling period, same blender can be by data from many signals Source（Perhaps multigroup signal source）It is routed to corresponding signal destination.However, the clock frequency of the mixer block is less than can be Set up required by signal path between each signal source and each signal destination during one data sampling period Clock frequency.Thus, the mixed block will not simply circulate through all possible signal path.It is specific with one when existing Blender clock rate C_RThe single blender of operation, and exist with one group of available sample rate S_R,iIn ith sample rate Some signal source N of operation_s,iWith signal destination N_d,iWhen, C_RMuch smaller than the product S obtained in all i values_R,i·N_d,i· N_s,iSummation.It is such with blender clock rate C when there is m_RDuring the blender of operation, product mC_RMuch smaller than institute There is the product S obtained in i values_R,i·N_d,i·N_s,iSummation.When in the presence of multiple blender clock rate Cs_R,jAnd m_jIt is individual with jth Individual blender clock rate C_R,jDuring the blender of operation, the product m obtained in all j values_j·C_R,jSummation be much smaller than The product S obtained in all i values_R,i·N_d,i·N_s,iSummation.The route can be matched somebody with somebody by the user of the audio hub circuit Put, can be reconfigured in use in addition, to provide difference in functionality in different situations.

Figure 15 is a block diagram, exemplified with the general form of the digital mixed nucleus 50 of the audio codec 39 of Fig. 3, is emphasized The hybrid component rather than emphasize functional block.

Figure 15 shows single piece 200, totally represents one group of multiple functional block, i.e. at the signal in digital mixed nucleus 50 Reason block 200.1 ..., 200.N.Figure 15 also show input 214 and output 216, and signal is introduced into mixed nucleus in input 214 50, signal is brought out mixed nucleus 39 in output 216.（Will be appreciated that typical circuit will be comprising multiple from the description of above figure 10 Input and output, those multiple inputs and output are represented so as to for ease of illustrating, be input into 214 and export 216.）

Thus, functional block 200 can serve as signal source, there is provided signal source port, and input 214 can also serve as signal Source, there is provided signal source port, and functional block 200 can also serve as signal destination, there is provided signal destination port, and export 216 can also serve as signal destination, there is provided signal destination port.Signal processing blocks are served as when pending signal is received Signal destination, and serve as signal source when processed signal is transmitted to output or follow-up function block.

There is the corresponding source buffer being associated with each signal source port of one of these functional blocks association 202.1st ..., 202.N, and with the signal source ports that associates of input 214 with the source buffer 202.P being associated.This A little sources buffers 202.1 ..., each the source buffer in 202.N, 202.P be connected to blender by source selector block 206.In this embodiment for illustrating, the source selector block takes the form of bus 204, the permission blender 206 of bus 204 Data are extracted from the corresponding source buffer being associated with any these signal sources.

Output data from blender 206 is sent to and these signal purpose ground terminals by destination selector block A corresponding destination buffer 210.1 of corresponding signal destination port association in mouthful ..., 210.N, 210.Q. Specifically, each destination buffer 210.1 ..., 210.N and functional block 200.1 ... on one of 200.N is corresponding Signal destination port association, and destination buffer 210.Q with export 216 on signal destination port associate. In this embodiment for illustrating, the destination selector block takes the form of bus 208, and the permission blender 206 of bus 208 will Data are sent to the corresponding destination buffer associated with any these signal destination ports.

Source buffer 202.1 ..., 202.N and destination buffer 210.1 ..., 210.N can physically by Corresponding functional block 200 is positioned adjacent to, or is adjacent to blender 206, or what convenient position in office, such as in route What the during the design of circuit 39 determined.Similarly, buffer 202.P can be located proximate to relevant signal input or close Blender 206, and buffer 210.Q can be positioned adjacent to relevant signal output or close blender 206.

Additionally, being connected to the design of the circuit system of input 214 or output 216, may mean that need not be in digital mixed nucleus Buffer is provided in 50.For example, be connected to input 214 to down-sampler output register or be connected to output 216 The input register of upsampler may have been provided for suitable buffering.In other words, some source buffers or destination are slow Device is rushed to may be provided in outside the digital mixed nucleus.

In this embodiment for illustrating, bus 204,208 is discrete, so as to allow the blender from buffer 202.1st ..., one of 202.N, 202.P read data while to buffer 210.1 ..., one of 210.N, 210.Q Write-in data.In an embodiment for replacement, single bus can be used for this purpose, come with bus arbitration scheme Ensure blender 206 be not intended to the complete same time from buffer 202.1 ..., one of 202.N, 202.P read data simultaneously And to buffer 210.1 ..., one of 210.N, 210.Q write-in data.However, input bus and output bus it is discrete Following aspect is favourable：Make it easier to avoid the timing conflict between being input into and exporting, and avoid that this must be shared total The bandwidth of line.

In this embodiment for illustrating, there is single blender 206, it serves all these signal destinations.

Figure 16 is a block diagram, exemplified with a totality for replacement of the digital mixed nucleus 50 in the routing circuit 39 of Fig. 3 Form.

As in Figure 15, Figure 16 shows single piece 200, totally represents multiple functional blocks, i.e. in digital mixed nucleus 50 Signal processing blocks 200.1 ..., 200.N.Figure 16 also shows that an input 214 and an output 216, and signal is in input 214 are introduced into mixed nucleus 50, and signal is brought out mixed nucleus 39 in output 216.

As in Figure 15, each functional block for potentially acting as signal source has the corresponding buffer being associated 202.1、……、202.N、202.P.In this embodiment, source selector includes the first source bus 220 and the second source bus 222.Each in first source bus 220 and the second source bus 222 be connected to buffer 202.1 ..., 202.N, Each in 202.P, to allow that it therefrom receives signal.First source bus 220 are connected to the first blender 224, And the second source bus 222 are connected to the second blender 226.Thus, the first source bus 220 allow the first blender 224 from Data are extracted with the corresponding buffer that any these signal sources are associated, and the second source bus 222 similarly allow for second and mix Clutch 226 extracts data from the corresponding buffer that any these signal sources are associated.

Output data from each blender 224,226 is sent to a corresponding buffer by destination selector 210.1st ..., 210.N, 210.Q, wherein each buffer 210.1 ..., in 210.N, 210.Q and these signal destinations A corresponding signal destination association.In this embodiment, selector block in the destination includes multiplexer 228 and total Line 230.Multiplexer 228 is based on applied control signal（It is not shown）To determine the first blender 224 and the second blender 226 In which output data can be sent to bus 230 in any one time, so as to be delivered to and any these signal mesh Ground association corresponding buffer.One simple possibility is the control signal is allowed blender A224 and blender B226 in an alternate cycles for fast processor clock with the session of bus 230.

Thus, in this embodiment, there is provided two blenders 224,226.It is in fact possible to there is any number Blender, to provide required or desired signal throughput.Generally, compared with the signal to be serviced of destination, blender Component will treat mixed input signal with more, thus input bus will saturation first, so if if requiring, two Or more input bus（Or any number of input bus smaller than destination number）And multiple blenders of association can Think that blender component bandwidth provides useful increase.

Figure 17 is a block diagram, exemplified with the general form of the digital mixed nucleus 50 of the replacement in the routing circuit 39 of Fig. 3.

As in Figure 15, Figure 17 shows single piece 200, totally represents multiple functional blocks, i.e. in digital mixed nucleus 50 Signal processing blocks 200.1 ..., 200.N.Figure 17 is also shown for an input 214 and an output 216, and signal is defeated Enter 214 and be introduced into mixed nucleus 50, signal is brought out mixed nucleus 39 in output 216.

Potentially acting as each functional block in the functional block of signal source has the corresponding buffer being associated 202.1、……、202.N、202.P.These buffers 202.1 ..., each buffer in 202.N, 202.P is by first Source selector is connected to blender 206.In this embodiment for illustrating, the source selector takes the shape of multiplexer 240 Formula, multiplexer 240 can be controlled to allow blender 206 to be extracted from the corresponding buffer that any these signal sources are associated Data.

Output data from blender 206 is sent to a corresponding buffer by destination selector 210.1、……、210.N、210.Q.Each buffer 210.1 ..., the phase in 210.N, 210.Q and these signal destinations The signal destination answered associates.In this embodiment for illustrating, the destination selector takes the shape of multiplexer 242 Formula, multiplexer 242 allows blender 206 to transfer data to the corresponding buffer associated with any these signal destinations.

Again, in this embodiment for illustrating, there is single blender 206, it serves all these signals Destination.

Figure 18 is a block diagram, exemplified with the digital mixed nucleus 50 in the routing circuit 39 of Fig. 3 another substitute it is total Body form.

As before, Figure 18 shows single piece 200, totally represents multiple functional blocks, i.e. in digital mixed nucleus 50 Signal processing blocks 200.1 ..., 200.N.Figure 18 is also shown for an input 214 and an output 216, and signal is in input 214 are introduced into mixed nucleus 50, and signal is brought out mixed nucleus 39 in output 216.

Potentially acting as each functional block in the functional block of signal source has the corresponding buffer being associated 202.1、……、202.N、202.P.These buffers 202.1 ..., each buffer in 202.N, 202.P is all connected to First source selector.

In this embodiment, the source selector includes the first multiplexer 248 and the second multiplexer 250, the first multiplexing Device 248 is connected to the first blender 252, and the second multiplexer 250 is connected to the second blender 254.Each multiplexer 248,250 With all these buffers 202.1 ..., 202.N, 202.P be connected so that the source selector allow blender 252,254 in Each blender extract data from the corresponding buffer associated with any these signal sources.

Output data from blender 252,254 is sent to a corresponding buffer by destination selector 210.1st ..., 210.N, 210.Q, each buffer 210.1 ..., the phase in 210.N, 210.Q and these signal destinations The signal destination answered associates.In this embodiment, the destination selector takes the form of multiplexer 256, The multiplexer 256 is based on applied control signal（It is not shown）Come in determining the first blender 252 and the second blender 254 Which can transmit output data, and the buffer associated with these signal destinations in any one time 210.1st ..., which buffer in 210.N, 210.Q can receive the data.

In this embodiment, there is provided two blenders 252,254, and any of which all may be used thus, Data are provided with to any these signal destinations.It is required to provide it is in fact possible to there is any number of blender Or desired signal throughput.

Figure 19 is a block diagram, exemplified with the digital mixed nucleus 50 in the routing circuit 39 of Fig. 3 another substitute it is total Body form.The digital mixed nucleus 50 shown in Figure 19 is identical with what is shown in Figure 18, and difference is that the destination selector will be every Individual signal destination is associated with blender 252, one of 254.

Thus, signal destination is divided into two groups, such as on the basis of following：Every group will be expected to use total can use Mixer resources in approximately equalised a mixer resources.As shown in Figure 19, one group of destination includes 216 Hes of output Functional block 200.1 ..., 200.J, and another group of destination comprising functional block 200.K ..., 200.N.

Destination selector then includes two multiplexers 256a, 256b, and multiplexer 256a is associated with blender 252, is multiplexed Device 256b is associated with blender 254.It is corresponding slow that output data from blender 252 is sent to one by multiplexer 256a Rush device 210.1 ..., 210.J, 210.Q, wherein each buffer 210.1 ..., 210.J, 210.Q with first group in phase The signal destination answered associates.It is corresponding that output data from blender 254 is sent to one by multiplexer 256b Buffer 210.K ..., 210.N, wherein each buffer 210.K ..., 210.N it is corresponding with second group one letter The association of number destination.

Figure 20 is a block diagram, shows blender and buffer and source selector and purpose in digital mixed nucleus 50 The form of ground selector.In fig. 20, if Figure 15 is as in Figure 17, there is a blender.When in such as Figure 16,18 and 19 that When sample has more than one blender, some or all in the mixer structure are to replicate.

In fig. 20, blender 290 be shown as be connected with from the buffer 202.1 associated with corresponding signal source ..., 202.N, 202.P receive input data, and be connected with to the buffer 210.1 associated with these signal destinations ..., 210.N, 210.Q transmit output data.

Blender 290 is multiplying accumulating block（MAC）Based on 292, the structure for multiplying accumulating block 292 is retouched in more detail below State.This multiplies accumulating block 292 and is time-multiplexed between different source and destination, again as described below.

Source selector block 294 determine in any given time these data sources which serve as multiplying accumulating block 292 the first data source（MAC inputs 1）, and destination selector block 296 determined in these data purposes of any given time Which in ground serves as the destination from the data output for multiplying accumulating block 292.

Based on the source input select signal received from controller 300, and based on the information received from register banks 298, Source selector block 294 selects source.Based on the output destination selection signal received from controller 300, and it is equally based on from posting The information that storage storehouse 298 receives, destination selector block 296 selects destination.As mentioned above, the He of source selector block 294 Destination selector block 296 can take any convenient form, and such as their form can be suitably in check total Line or multiplexer.

Register banks 298 also function as the second data source for multiplying accumulating block 292（MAC inputs 2）.MAC inputs 2 are provided to be treated It is applied to the zoom factor of data selected being processed.

Figure 21 is a block diagram, shows blender and the buffer and selector block for associating in digital mixed nucleus 50 One form of replacement.

In this embodiment, blender 310 includes multiplying accumulating block 292, and is connected to the He of source selector block 294 Destination selector block 296, they are identical with the source selector block 294 and destination selector block 296 that are shown in Figure 15.

Figure 21 illustrates embodiment in, register banks 312 and controller 314 have and Figure 20 in the mixing that shows The roughly the same function of the corresponding component of device 290, but it is not qualified as a part for the blender.Replace, blender 310 Interior memory 316 stores the data received from register banks 312, and based on the data received from register banks 312, Xiang Yuan The supply source input select signal of selector storehouse 294 and to destination selector storehouse 296 supply output destination selection signal.

Figure 22 is a block diagram, shows the feasible form for multiplying accumulating block in the blender of Figure 20 or Figure 21.

In fig. 22, show and multiply accumulating（MAC）Block 292, it receives first source that comes from（MAC inputs 1）Data and come From the second source（MAC inputs 2）Data as the input to multiplier 330.The output of multiplier 330 is applied as addition The input of device 332, and adder 332 output by so that be applied to register 334, received based on register 334 Clock signal, the output of adder 332 is served as a single clock cycle and postpones element（oneclock period delay element）.The output of register 334 is provided as multiplying accumulating an output of block 292, and is also fed back to adder 332 the second input.

（Alternately, can using the output of adder 332 as the MAC block output.）

Thus, during a clock cycle, block 292 from the first source is multiplied accumulating（MAC inputs 1）Data are received, this is counted Multiplication coefficient is multiplied by according to value, the form of the multiplication coefficient is from the second source（MAC inputs 2）Data, and add the result to Previously received and value.This can be allowed to continue several clock cycle, with cause multiply accumulating block 292 output represent from Several data values and value that first source receives, each data value is scaled by a corresponding multiplication coefficient.When desired It has been calculated with value, and has been exported when being buffered in the destination buffer 210 of plan, has been stored in register 334 In value can be eliminated.Or, the value can simply be left, and be directed to next number being firstly received by disabling According to adder come by next part and value covering.

Figure 23 is a block diagram, shows one that the multiplies accumulating block form of replacement in the blender of Figure 20 or Figure 21.

Block 292 is identical with what is shown in Figure 22 for multiplying accumulating of being shown in Figure 23, and difference is that the output of register 334 is passed It is sent to an input of controllable multiplexer 336.Another input of multiplexer 336 is connected to by bypass path 338 Multiply accumulating the input of block 292.It means that when required output data is simply from the first source（MAC inputs 1）It is defeated Enter data, during without any scaling or mixing with other data values, the bypass path input of multiplexer 336 can be chosen Select, and be connected to the output for multiplying accumulating block 292.

Figure 24 is a flow chart, and Figure 25 is a general view, and Figure 26 is a timing diagram, exemplified with Figure 20 or Figure 21 The operation of the blender of illustration.

Figure 26 shows an a relatively high speed clock DCK and clock SCK compared with low speed.The clock compared with low speed The frequency of SCK is the sample rate of voice data stream, so that it is determined that this data needs processed speed.For example, for electricity The speech processes for talking about calling can require that data are generated with the frequency of 8kHz, and the treatment application of other voice datas can be required Data are generated with the frequency of 48kHz.In this embodiment for illustrating, using only the forward position of each dock cycles （leading edge）, so the dutycycle that SCK is not shown to have 50% is inessential.

The clock DCK of the high speed determines the speed for multiplying accumulating the operation of block 292, i.e. MAC circulates through the speed of multiple inputs Degree.It should be noted that the representative value of data clock DCK can be such as 48MHz, it can be used, for example, the sample rate of exemplary process 1000 times of clock SCK.Thus, Figure 26 is not in proportion, but exemplified with required treatment.

Figure 24, Figure 25 and Figure 26 from two data in source exemplified with will be mixed together and be applied to defeated In the case of going out, the operation of blender 290.It is during the period 1 of sampled clock signal SCK or interval in the very first time T1（Or any time interval earlier）Period, the first treatment（Treatment A）Performed by one of functional block 200.A（Or equally, Data are received in the input of the digital mixed nucleus）, and this generates the first data value（Step 450 in Figure 24）, the number Can be obtained in the data source buffer 202.A associated with that data source in very first time interval T1 according to value, that is, be stored. First data value is stored in data source buffer 202.A（Step 452 in Figure 24）, to cause to be adopted entirely ensuing The sample clock cycle（Or second time interval）The upper blenders 290 of T2 can obtain first data value.

Figure 25 and 26 shows the division of buffer 202.A so that some times of data in very first time interval T1 The first half portion 202.A1 of buffer 202.A is written into, and data are transferred to buffering at the end of very first time interval T1 The second half portion 202.A2 of device 202.A so that data can be in any time through the second time interval T2 by blender 290 It is accessed from the second half portion 202.A2 of buffer 202.A.

In interval T1 of the same very first time（Or any time interval earlier）Period, second processing（Treatment B）By function One of block 200.B is performed（Or equally, data are received in the input of digital mixed nucleus）, and this generates the second data Value（Step 454 in Figure 24）, the data value can obtain in the data source buffer 202.B associated with that data source.The Two data values are stored in data source buffer 202.B（Step 456 in Figure 24）, to cause in whole ensuing sampling Blender 290 can obtain second data value on clock cycle T2.Figure 25 and Figure 26 with buffer 202.A described above Identical mode shows the division of buffer 202.B（partitioning）.

Time point t2a during sampling clock cycle T2, makes to multiply accumulating block 292 in the first input（MAC inputs 1）Obtain Data from buffer 202.A2, so its rising edge in data clock DCK（rising edge）Obtain the first data Sample（Step 458 in Figure 24）.（Data conversion can suitably also be timed to appear under data clock DCK Drop edge.）During the clock cycle between cycle t2a and t2b of data clock DCK, this first data sample is contracted Put（Represented by "×" 350）, by being multiplied with the in the second input in multiplier 350（MAC inputs 2）The multiplication coefficient of acquisition （Step 460 in Figure 24）And be scaled.The result of this scaling is stored in the register 334 of Figure 22.

The time point t2b after that clock cycle between the t2a and t2b of data clock DCK, makes to multiply accumulating block 292 in the first input（MAC inputs 1）Obtain the data from buffer 202.B2, the second data value so it has sampled（Figure 24 In step 462）.During the clock cycle between cycle t2b and t2c of data clock DCK, the data of the second sampling Value is scaled（Represented by "×" 352）, by being multiplied with the in the second input in identical multiplier 350（MAC inputs 2）Obtain The second zoom factor（Step 464 in Figure 24）And be scaled.The result of this scaling is added（Represented by "+" 354）To The scaled results of one data sample（Step 466 in Figure 24）.

The result of this addition is stored in and is intended to receive the data destination of output data --- i.e., functional block（Or The output of the digital mixed nucleus）In the first half portion 210.Z1 of the output buffer 210.Z of 200.Z --- association（In Figure 24 Step 468）.As before, Figure 25 and Figure 26 show the division of buffer 210.Z, so as to obtain data in the second time zone Between the first half portion 210.Z1 of buffer 210.Z is written to during T2, be then transferred to second half portion of buffer 210.Z 210.Z2, it is obtainable that data keep herein, until ensuing sampling clock cycle T3 terminates.

Random time t3a during sampling clock cycle T3, the output data is as the functional block of data destination 200.Z samples（Step 470 in Figure 24）, it can be then in subsequent treatment by functional block 200.Z treatment（Step in Figure 24 Rapid 472）.Certainly, if the data destination is the output of the digital mixed nucleus, result data can be in the phase in sampling period T3 Between be output（Step 474 in Figure 24）.

Thus, multiply accumulating block 292 and generate required data, to cause the data required by this when required Though between --- in the where in audio sample cycle --- be available for be intended to receive it block obtain.Which greatly simplifies in configuration Sequential required in the digital mixer core considers.That is, the arrangement of source buffer and destination buffer is it is meant that knowing Multiply accumulating data that block 292 requires from data source will it is obtainable on a whole sampling period in the case of, multiply accumulating block 292 Operation can be scheduled（To cause that the scheduling will become obtainable true without the concern for the data within that sampling period Cut time point）, and and knowing that multiplying accumulating block 292 will sample week to the data that data destination supplies in whole another In the case of obtained by phase, the operation for multiplying accumulating block 292 can be scheduled（To cause that the scheduling is adopted without the concern at that The definite time point that the data will be required in the sample cycle）.

In other words, will be in the ensuing whole sampling period in the data for starting to be presented on source port in a sampling period On can be available for purpose plot treatment.It is assumed that the purpose plot can complete its operation within the latter sampling period, then should Therefore the stand-by period in the per stage in signal processing chain is two fixed sampling periods, and one is used for blender, a use In treatment.Which greatly simplifies the stand-by period calculating for signal chains.

This stand-by period is also independent from for giving the blender timing（And give these functional block timing）Clock, this makes Any clock frequency scaling is all invisible to the audio signal path.

If requiring the additional stand-by period in some paths, such as in order to match by the extension process in parallel route The stand-by period of introducing, then blender output can be fed back to the defeated of it via the signal processing blocks including simple register Enter, if necessary then repeatedly feed back.

As described above, Figure 26 is a timing diagram for illustration（Not to scale (NTS)）, show from the first data source（Place Reason A）A data sample by with from the second data source（Treatment B）A data sample group close, to generate a result Sample, the result sample is provided to data destination（Treatment Z）.

Certainly, most of true treatment require that this operation is repeatedly executed, and each sampling period performs once, and Figure 27 shows another timing diagram that this is repeated.

Thus, in figure 27, as in fig. 26：

In sampling clock cycle T1,

From treatment A（Such as functional block 200.A）Data be stored in buffer 202.A1,

From treatment B（Such as functional block 200.B）Data be stored in buffer 202.B1；

In the beginning of sampling clock cycle T2,

The data stored in buffer 202.A1 are transferred to buffer 202.A2,

The data stored in buffer 202.B1 are transferred to buffer 202.B2；

During sampling clock cycle T2,

Data from buffer 202.A2 and 202.B2 are mixed by the result with storage in buffer 210.Z1（Mixing 1）

In the beginning of sampling clock cycle T3,

The data stored in buffer 210.Z1 are transferred to buffer 210.Z2

During sampling clock cycle T3,

Make data destination（Such as functional block 200.Z）The data from buffer 210.Z2 can be obtained.

This treatment is repeated after a sampling clock cycle.I.e.：

In sampling clock cycle T2,

From treatment A（Such as functional block 200.A）Data be stored in buffer 202.A1,

From treatment B（Such as functional block 200.B）Data be stored in buffer 202.B1；

In the beginning of sampling clock cycle T3,

The data stored in buffer 202.A1 are transferred to buffer 202.A2,

The data stored in buffer 202.B1 are transferred to buffer 202.B2；

During sampling clock cycle T3,

Data from buffer 202.A2 and 202.B2 are mixed by the result with storage in buffer 210.Z1（Mixing 2）；

In the beginning of sampling clock cycle T4,

The data stored in buffer 210.Z1 are transferred to buffer 210.Z2

During sampling clock cycle T4,

Make data destination（Such as functional block 200.Z）The data from buffer 210.Z2 can be obtained.

Thus, the treatment is repeated in each sampling clock cycle, and makes the data destination can be with required Sample rate obtains output data sample.

As described above, Figure 27 is a timing diagram for illustration（Not to scale (NTS)）, show in each sampling period, From the first data source（Treatment A）A data sample by with from the second data source（Treatment B）A data sample group Close, to generate a result sample, the result sample is provided to data destination（Treatment Z）.

The one side of the embodiment described by Figure 26 and Figure 27 is that blender time-division between multiple data destinations answers With, and Figure 28 is the timing diagram that another is illustrated（Not to scale (NTS)）, show time division multiplex aspect.

Thus, in Figure 28, as in fig. 26：

In sampling clock cycle T1,

From treatment A（Such as functional block 200.A）Data be stored in buffer 202.A1,

From treatment B（Such as functional block 200.B）Data be stored in buffer 202.B1；

In the beginning of sampling clock cycle T2,

The data stored in buffer 202.A1 are transferred to buffer 202.A2,

The data stored in buffer 202.B1 are transferred to buffer 202.B2；

During sampling clock cycle T2,

In time t2a, MAC292 extracts data from buffer 202.A2, and scales the data if requiring,

In time t2b, MAC292 extracts data from buffer 202.B2, and scales the data if requiring,

In time t2c, the data for having scaled are added, and are as a result stored in buffer 210.Z1.

In the beginning of sampling clock cycle T3,

The data stored in buffer 210.Z1 are transferred to buffer 210.Z2

During sampling clock cycle T3,

In time t3a, make data destination（Such as functional block 200.Z）The data from buffer 210.Z2 can be obtained.

The time division multiplex of the blender can process parallel generation it is meant that another is processed with this, as long as MAC292 Operation it is scheduled avoiding being overlapped between them（overlap）.

Thus, Figure 28 is also shown for this parallel running：

In sampling clock cycle T1,

From treatment C（Such as functional block 200.C）Data be stored in buffer 202.C1,

From treatment D（Such as functional block 200.D）Data be stored in buffer 202.D1；

In the beginning of sampling clock cycle T2,

The data stored in buffer 202.C1 are transferred to buffer 202.C2,

The data stored in buffer 202.D1 are transferred to buffer 202.D2；

During sampling clock cycle T2,

In time t2d, MAC292 extracts data from buffer 202.C2, and scales the data if requiring,

In time t2e, MAC292 extracts data from buffer 202.D2, and scales the data if requiring,

In time t2f, the data for having scaled are added, and are as a result stored in buffer 210.Y1.

In the beginning of sampling clock cycle T3,

The data stored in buffer 210.Y1 are transferred to buffer 210.Y2

During sampling clock cycle T3,

In time t3b, make data destination（Such as functional block 200.Y）The data from buffer 210.Y2 can be obtained.

One or more in data destination 200.Z, 200.Y for being shown in wherein Figure 28 are signal processing blocks forms Functional block, it and then will provide data source port subsequently in another treatment.

Figure 26 to Figure 28 shows a system, and wherein each buffer is divided in order to so that data are written into the buffer Part I, the Part II of the buffer is then transferred at the beginning of a new sampling clock cycle, then Read from the Part II of the buffer during the new sampling clock cycle.Use " table tennis（ping pong）" buffering Device is also feasible, and it is then divided in order to cause that data are transmitted never between the two parts of buffer；Replace, Data can be written to the Part I of buffer and by from the second of buffer during the sampling clock cycle of odd-numbered Part is read, and can be read and be write from the Part I of buffer during the sampling clock cycle of even-numbered To the Part II of buffer.

Figure 29 is a timing diagram, shows the use of ping-pong buffers.

Thus, in Figure 29：

In sampling clock cycle T1,

From treatment A（Such as functional block 200.A）Data be written to the Part I of corresponding buffer 202.A3,

From treatment B（Such as functional block 200.B）Data be written to the Part I of corresponding buffer 202.B3；

During sampling clock cycle T2,

Data are read from the Part I of buffer 202.A3, and are scaled if requiring

Data are read from the Part I of buffer 202.B3, and are scaled if requiring

The data for having scaled from 202.A3 and 202.B3 are mixed（Mixing 1）, as a result it is stored in buffer In the Part I of 210.Z3

From treatment A（Such as functional block 200.A）Data be written to the Part II of corresponding buffer 202.A4

From treatment B（Such as functional block 200.B）Data be written to the Part II of corresponding buffer 202.B4；

During sampling clock cycle T3,

Make data destination（Such as functional block 200.Z）The data of the Part I from buffer 210.Z3 can be obtained

Data are read from the Part II of buffer 202.A4, and are scaled if requiring

Data are read from the Part II of buffer 202.B4, and are scaled if requiring

The data for having scaled from 202.A4 and 202.B4 are mixed（Mixing 2）, as a result it is stored in buffer In the Part II of 210.Z4

During sampling clock cycle T4,

Make data destination（Such as functional block 200.Z）The data of the Part II from buffer 210.Z4 can be obtained.

The treatment is repeated, so that data destination can obtain output data sample with required sample rate.

Figure 30 is a flow chart, can configure the treatment of on-off circuit by it exemplified with user of the invention. The aspect of the operation of the on-off circuit can be configured in the during the design of the integrated circuit for containing the on-off circuit, and/ Or be configured during the exploitation of the electronic equipment containing the integrated circuit for containing the on-off circuit, and/or by purchasing The end user's configuration for having bought the electronic equipment.The aspect for having been configured by the developer of the electronic equipment of the operation can be by Protection is causing end user from changing that configuration, or can be left and matched somebody with somebody with alloing that end user changes that Put.It is multiple in the consumer device in following description, it is assumed that user of the invention is the designer of consumer device Audio signal will be processed in parallel.In this embodiment for illustrating, the required equipment is limited by allowing user Function, makes this configuration treatment as far as possible be intuitively to user.In this embodiment for illustrating, this treatment is to work as Final products --- such as smart phone, game machine, portable electronic device or the like --- are performed when being designed. In this embodiment for illustrating, final products are smart phones.

Figure 30 illustrates treatment the step of 500 in, user defines the required signal by the on-off circuit Treatment.For example, as shown in Figure 32, it is obtainable which input signal user can totally describe, and he is uncommon Hope based on which output signal is these input signals generate by which treatment.

Thus, Figure 32 show user wish with 48k samples/secs from analog voice microphone extract input signal 520, 522, by each input signal to 8k samples/secs are down sampled to, both of which is then sent to DSP, returned with performing acoustics Sound is eliminated, and generates the ambient noise elimination signal for the transmitting path.Thus, the microphone detection in the smart phone To signal before being sent via telephone network be processed.

Processed output signal 524 has been applied in gain, and resulting signal 526 is sent to the smart phone BBP.

Processed output signal 524 also will be by being upsampled to 48k samples/secs, and gain will be applied to To the signal 528 of up-sampling.

Figure 32 is also shown for user and wants to extract signal 530 with 8k samples/secs（This represents received voice and exhales Cry sound）, and by it from 8k samples/secs to being upsampled to 48k samples/secs.User is wished to the signal 531 of up-sampling Apply gain, and resulting signal 532 is sent to balancer function, the signal of 217Hz is in decay and in it The harmonic wave of multiple.User then wishes to apply gain to the signal 534 that this has been filtered, and to resulting gain signal 536 perform many band compressions（multiband compression）.

User then wishes to apply gain to the signal 538 for having compressed, and resulting signal 540 is passed via DAC It is sent to the loudspeaker of the smart phone.Thus, received voice signal quilt before the user's playback to the smart phone Treatment.

In addition, the designer of user of the invention, the i.e. smart phone device, may desire to provide One function, whereby The both sides of call are recorded.Thus it may be desirable to apply to the two signals 528,538（May be different）Gain, And the two signals 528,538 are added together in a use example, and resulting signal 542 is sent to the intelligence The application processor of energy phone, is recorded in local storage with the signal 542 obtained by alloing, for example, record at this In equipment, or record is in the storage device that can be inserted into the equipment.

Figure 30 is returned to, in step 502, these treatment operations are mapped to available functional block in digital mixed nucleus.Example Such as, in this embodiment, one of DSP in digital mixed nucleus, such as DSP#1102 can be optimized for performing acoustics time Sound is eliminated, and another such as DSP#N112 can be optimized for performing many band compressions, so these operations are all assigned to Corresponding DSP.In addition, a balanced device can be optimized for the harmonic wave that removal is in the multiple of 217Hz, so that is operated The specific balanced device 120 can be assigned to.If being optimized for the concrete function that user wishes to implement without functional block, Then relevant operation can be assigned to these wave filters or one of balanced device or DSP, and it can then be programmed to perform that Function.

Total signal route is then split into multiple component signal paths, and each path is related to one or more signals Source and a signal destination, and each path requires the blender component for accessing the digital mixed nucleus.

These operations are then defined as to be stored in the register banks 298 associated with blender, and can be with Accessed by controller 300（See Figure 20）, to cause that these operations are performed as requested.

Figure 33 shows a possible form of the register banks before any operation is limited.Thus, there is multiple Channel Identifier（identifiers）, i.e. channel id, the corresponding signal destination in each channel id and digital mixed nucleus Port association.As previously described, the functional block in digital mixed nucleus can provide signal destination（In fact, one it is more complicated Functional block --- such as completely programmable digital signal processing block --- several independent signal destinations can be provided Port）, and each output from digital mixed nucleus is signal destination port.

Each channel id, i.e. destination port, the selector port with the predetermined number being associated.As explained above with Figure 11 to Figure 13 descriptions, the number of selector port represent be may be connected to during any one sampling clock cycle with The number of the signal source of the signal destination of that channel id association.Thus, Figure 33 shows, by channel id（By hexadecimal Address represents）0Dh, 0Eh and 27h represent signal destination respectively have four selectors being associated, channel id 14h and 15h respectively has a selector being associated, and channel id 57h has two selectors being associated, by that analogy.

In another embodiment, the number of the selector port for being associated with any given channel id（That is, source is most Big figure）Can be completely by user（That is, by the designer of the consumer products comprising the on-off circuit）It is programmable.

The treatment shown in Figure 30 is returned to, required signal route is mentioned above and is split into multiple signal paths, Each path is related to one or more signal sources and a signal destination, and each path requires that access numeral is mixed The blender component of synkaryon.For each signal path in these signal paths, relevant signal destination port（And close The channel id of connection）It is identified in step 504.Then, in step 506, the selector end for being associated with that destination port One of mouth is chosen.

In step 508, the signal source for that selector is identified, and in step 510, yield value is referred to It is fixed, so as to get from the signal in identified source be scaled before signal destination is sent to（Or amplify reduce）Arrive Required degree.

In step 512, source ID and the yield value are stored in the relevant row of the register banks（I.e., in fig. 33 The corresponding register address for showing）, corresponding to the selected selection associated with the signal destination with suitable channel ID Device.

Each channel id must also have the sampling clock rate being associated.The sampling clock rate is that the functional block is expected to connect Receive speed of the data for treatment.For example, the operation associated with manipulation voice signal will typically use 8kHz clock manipulations, or Person uses 16kHz clock manipulations in the case of HD audios, but the operation associated with metering of operation device music will typically use 48kHz Clock manipulation.

In the embodiment of Figure 33, single storage location is utilized for each channel id and independently limits sampling clock.Will Sampling clock is feasible with the other method that each channel id is associated, and can be in some embodiments preferred. For example, for the systematicness in register mappings, with memory space as cost, it may be preferable that with discrete storage location come The sampling clock of each the selector port for each channel id is limited, but in use, for the choosing of each channel id The all sampling clocks for selecting device must be identical.

Alternatively, it may be preferable that all channels for being used to be associated with given signal processing blocks by single storage location ID（That is, destination port）.In many cases, the internal signal treatment in signal processing blocks will be suitable for only existing in single sampling The data of rate, are such at least in the block without sample rate transfer capability.

The sample rate can represent by its nominal value, such as 8K, 16K or 48K.However, being more convenient and requiring less to deposit Storage can limit one group of fixed such as eight sampling clock, and distribute one 3 to each sampling clock（That is, 2³ =8）Identification code, such as 000 to 111, and desired sampling clock is associated with each letter by storing suitable identification code Road ID.This can also allow to limit more than one sampling clock with the nominal sample rate of identical.In some applications, Ke Yicun In such as two nominal 48kHz clocks, wherein each clock is drawn from a different clock source, e.g. from different What attachment arrangement drew.These clocks in reality will always have slightly different frequency and phase, and combination or its He can require that sample rate is changed before processing.

Thus, the minimum information that be must provide for limit signal path is, the signal source port or each signal source Port, signal destination port and corresponding data sampling rate.In this embodiment, it is also possible to store and wait to be applied in To the signal source port from signal path or a corresponding zoom factor of the data of each signal source port.

A more specifically embodiment will be by way of illustration given now.

Figure 32 is exemplified with by user of the invention（The designer of such as communication equipment）The sequence of operations of identification.

Figure 34 correspond to figure 1 described above 4, but show for desired operational chain this signal route how Multiple discrete paths can be split into.In Figure 34, each signal source is represented by a filled black is circular, each signal Destination is represented by a filled black rhombus, and each selector for being associated with one of these signal destinations and a reality Heart black square is associated.

If the microphone in the smart phone hand-held set is connected to the simulation input 550,552 of audio hub, Each input in these inputs will receive the signal of the voice of the user for representing the smart phone, and these signals will be worn Pre-regulating circuit system 54, SWITCHING CIRCUITRY 60 and downward sampling circuitry 64 are crossed, the input of the digital mixed nucleus is reached 554、556。

One path 558 is then defined as from the input 554 of digital mixed nucleus to the input with downward sampling block 164 The selector of one of 560 associations.Second path 562 be defined as from the output 564 of downward sampling block 164 to a DSP102 One of input 108 association selector, the DSP is selected for this purpose, because it can be programmed to hold The required acoustic echo of row is eliminated（AEC）, and orientation ambient noise elimination is sent on the voice signal for receiving（ANC） Treatment operation.

Similarly, path 568 is defined as from the input 556 of digital mixed nucleus to downward sampling block 164, and path 570 are defined as another input in the input 110 from the corresponding output of downward sampling block 164 to a DSP102.

Path 572 is defined as from the output of DSP102 to N digital audio interfaces 52.N.To this specific numeral sound The connection of frequency interface is because BBP is intended to be connected to this interface.

The voice signal received via cell phone is manipulated by BBP so that these voice signals are N digital audio interfaces 52.N is received by digital mixed nucleus 50, and is expected the transmission of these signals first by upward sampling block 162, as shown in path 574.

The signal of warp-wise up-sampling is sent to balanced device 120, and balanced device 120 is configured as notch filter（notch filter）, to remove the residual noise in 217Hz（Caused by the characteristic of GSM cellular systems）And its harmonic wave, such as path Shown in 576.

This signal for having filtered is sent to N DSP112, as shown in path 578.NDSP112 can be programmed To provide many band compressions（MBC）.As shown in path 580, resulting signal can then be sent to the defeated of digital mixed nucleus One of go out, smart phone loudspeaker is to be joined to the output.

The call record function of the description of reference picture 32 is provided for the voice signal given in the transmitting path of call, The output of DSP1 is sent to upward sampling block 162, as shown in path 582, and warp-wise up-sampling signal be sent to One selector 584 of one of signal destination 586 on the first digital audio interface 52.1 association, such as route segment （segment）Shown in 588.Connection to this specific digital audio interface is because the application processor（It manipulates this and exhales Cry writing function and other）It is intended to be connected to this interface.

In order to the voice signal given in the RX path of call provides call record function, the output of N DSP112 The different selector 590 associated from the same signal destination 586 of the first digital audio interface 52.1 is sent to, such as Shown in route segment 592.

Note, the signal path associated with destination port 586 actually includes two route segments, 588 and 592.It is overall On, when multiple signals are routed in a channel, corresponding signal path will be including multiple route segments, and they are focused at mixed Close in channel.When using only one selector, the signal path will be including only one route segment.

It will be appreciated that user may need to explain a large amount of such use examples.For example, in the presence of as described above for grasping The vertical standard use example for sending voice signal and receiving voice signal, and wherein exist come self-recording music source music, Or carry out the use example of the sound of the radio receiver of auto correlation；And there is also wherein ring tone needs and voice signal The use example of mixing, wherein wired or wireless hand-held set is connected to smart phone and exports voice signal needing by suitably The use example of guiding, and other.

Figure 35 shows these paths illustrated in Figure 34（Or tighter, route segment）In the register mappings how It is defined.Note, for convenience, be comprised in this form with reference to figure for the route segment in Figure 34, but do not constitute this A part for register mappings.Figure 36 is schematically showing for digital mixed nucleus, and wherein part is re-arranged, with Figure 36's Left-hand side shows signal source（That is, the functional block of digital mixed nucleus, and to the signal input of digital mixed nucleus）, each signal source With an input buffer for association（As indicated by Ref. No. 202.x in fig .15）, and each signal destination （That is, the functional block of digital mixed nucleus, and the signal output from digital mixed nucleus）With an output buffer for association （As indicated by Ref. No. 210.y in fig .15）.Figure 36 shows the hexadecimal bus address of these buffers, and Figure 35 shows channel id for each path described above with reference to Figure 34, selector number, sample rate, source ID and increasing Benefit.

The operation that Figure 35 is based on describing in such as Figure 32 needs to be performed in the consumer device including audio hub Operation required by one time of period, shows register mappings in a state for special time.Typically, these will Represent by user（That is, the designer of the product including the audio hub）Limit to consider all possible of the product Use the only a fraction of with all operationss of state.For example, operation will be defined as when audio call is activated, when will Ask when putting the music on, it is when the button of keyboard is pressed and more.

It is preferably stored in the memory of the product for these configuration informations for operating, when equipment operation when institute It is addressable to state configuration information.For example, the configuration information can be stored in the ROM of the product, and opened in the product When the state of dynamic and product changes after a while, audio hub is downloaded to by application processor.This is generally than by all letters Breath is stored in audio hub itself and the alternative solution of the operation of flag activation is more efficient, because it can make With more efficient type of memory, and as it means that audio hub need not be containing being enough to store for unknown number Use example configuration information amount of storage.Additionally, the data volume to be downloaded in the state change of the product is relatively small.

By using suitable figure configurator, the configuration of routing circuit described above can simplify to user.For Allow users to limit signal path, the Function Block Diagram 1200 of SWITCHING CIRCUITRY is presented or such as Figure 31 to user In the Function Block Diagram 1200 of mixed nucleus that shows.For example, this can with the computer association for being currently running configuration process User is presented on screen 1210, for example, allows user to provide user input using mouse and/or keyboard or the like, to refer to Show all required use examples.This can include on-off circuit 39 other parts configuration, for example presetting locking nub or after Any gain applied in regulating block.The configuration process can with application in（For example in actual prototype equipment）Actual switch electricity Road interacts, or can be with the simulation interactive of the signal transacting helping debug（debug）.

Screen also contains the region 1220 for showing available functional block.Thus, Figure 31 shows user by DSP block One represent and 1222 pull and deliver to the situation in working region 1200, region 1220 then shows three available DSP One of block has been placed.Similarly, balanced device 1224 has been placed, and region 1220 show eight available balanced devices it One has been placed.

User requires that the data from the second digital audio interface 1226 should be sent to balanced device 1224, then be sent to DSP block 1222, is then sent to output 1228.

However, the user interface can also recognize that each signal path between functional block must have consistent sampling Rate.

However, it is specified that the second digital audio interface 1226 produces the data of the sample rate with 8k samples/secs, it is and equal Weighing apparatus 1224 is run with 48k samples/secs.Thus, sampling rate converter 1230 need to be comprised in the second COBBAIF 1226 with Between balanced device 1224.Thus, there is the path required by four by the blender, i.e.,：With 8k samples/secs from the second numeral COBBAIF 1226 arrives sampling rate converter 1230；With 48k samples/secs from sampling rate converter 1230 to balanced device 1224；With 48k samples/secs are from balanced device 1224 to DSP block 1222；And with 48k samples/secs from DSP block 1222 to output 1228.

Sampling rate converter 1230 can manually be added by user, may be followed by the software inspection to consistent sample rate Look into.Alternatively, configuration software can be intelligent enough, and track of the extraction from second interface to balanced device is once attempted with user When, the needs sampling rate converter is just immediately appreciated that, and be inserted into automatically.

As described herein, the sample rate of functional block and interface is specified by user, so as to allow to push away by interface software Break the need for sample rate conversion.Reciprocally, these sampling rate converters can also be placed by user, so as to allow by connecing Mouthful software is inferred to the sample rate of these functional blocks.

Required all use examples can be designated in the same fashion.

Fig. 3 above 2, Figure 34, Figure 35 and Figure 36 which provides call record function exemplified with a use example.

Figure 37 a which provide local voice mail exemplified with a use example for replacement（Local Voice Mail^TM） Function.The local voice mail function can be activated in the case where there：When telephone subscriber presses button with to local voice When mail passes on the audio call of incoming call；Or when the phone has been arranged so that telephone subscriber the audio call of incoming call is passed When reaching local voice mail, otherwise local voice mail is communicated to automatically when calling is received, or when in predetermined number Called after purpose the tinkle of bells and be not still picked up（unanswered）When be communicated to local voice mail.In appointing for these events In one, this use example is all activated.

In this use example, caller is prompted to leave speech message for telephone subscriber, and the speech message is deposited Storage is in phone itself, even if so as to allow the telephone subscriber also to obtain the message in the case of no network coverage is available.

Specifically, received speech message is received in the BBP of phone, and the BBP is at this N digital audio interfaces 52.N is connected in the case of individual.One signal path is set up as reaching the first number by blender Word COBBAIF 52.1, application processor is connected to first digital audio interface 52.1.Therefore, the speech message can be stored In the memory of processor control and access is employed.Alternatively, a signal path can be set up as by blender Reach the first digital audio interface 52.1, wireless transceiver（That is, wireless coding and decoding device）May be connected to the first digital sound Frequency interface 52.1.Therefore, the speech message can be stored in the memory for being controlled and being accessed by another equipment, this another Equipment is wirelessly connected and receives data with from the wireless transceiver（That is, speech message）.

Need not be changed containing any sample rate by the signal path of the blender, because representing the speech message Data can be received in digital audio interface 52.N, and digital audio interface 52.1 is transferred to, without the original from it Beginning sample rate（Such as 8k samples/secs）There is any sample rate to change, even if in the presence of other to be manipulated compared with high sampling rate simultaneously Treatment, if the audio signal of the sample rate of the 48k samples/secs for for example being recorded is transmitted through blender.By blender Signal path also without being scaled by any way.

The local voice mail（LVM^TM）Function can be by applying（That is, software, commonly known as " app "）There is provided, should With being the Downloadable Internet that pays license fee via user.

Alternatively, DAB hub can contain the local voice mail function, i.e. should when loading is dispatched from the factory Local voice mail function is already embedded in DAB hub, but in disabled status.In order that the local voice that must be embedded in Mail can be used, and will require " key " to be unlocked the lock for disabling the local voice mail.In this case, should Key（That is, the code of software form）The internet that need to pay license fee via user is downloaded.

It is clear that when the software of local voice mail is developed for, it is necessary to consider the equipment and this will be required The environment that ground voice mail works.Such consideration is of the prior art for the developer of so-called software driver Convention.

Once it is mounted or is enabled, local voice mail（LVM^TM）Activation can by user via operation local voice The keyboard or touch screen of the equipment of mail is controlled：Such equipment is, for example, mobile phone, smart phone, panel computer.

Can be by for example selecting scheme to implement how the local voice mail is activated from drop-down menu.Substitute Ground, selection can be carried out by icon.The local voice mail menu or icon can be represented, for example, the calling of incoming call is：Nothing Need telephone rings and be stored automatically；After the tinkle of bells of certain amount, if user does not answer the calling, stored；Or Person is not stored in local voice mail.Additionally, menu or icon can be represented, and pre-recorded disappearing is sent to caller Breath, so as to point out caller to leave speech message for telephone subscriber.

When new local voice-mail message is stored in memory, the equipment can by the icon on screen, By with indicate to the user that new non-native speech email message be substantially the same in the way of to indicate the fact that.

Stored local voice mail can be accessed via menu or icon.Additionally, in the local voice postal for being stored Before part can be obtained, it is also possible to it is required that input password.The form of the password can be numeral and/or alphabetical sequence, and/or It is pattern in the case of touch screen.

The advantage of local voice mail is included：Just in case available without the network coverage, telephone subscriber can also obtain message；It is right The user that participation obtains local voice-mail message does not have cost（In addition to license fee）；And reduce and obtain non-local The flow of the network of speech message association.

Local voice mail another advantage is that, it is less susceptible to be attacked by phracker.Potentially " hacker " can need Want physics to access the equipment, then, if the equipment is subject to password protection, need to obtain the password to access stored sheet Ground voice mail.

In the presence of other use examples, wherein data from interface are sent to another interface without any scaling or The ability of sample rate conversion is important to maintaining data integrity, especially when data are encoded in certain mode.For example, figure 37b shows following situation：From the coded data that a processor is received（It can be compression（compressed）Or companding 's（companded）Data）, and be intended to be launched or solved by another processor companding（That is, decode）, wherein appointing to the data What sample rate conversion or scaling can all have the risk of the content for changing coded data after the expansion.It is somewhat like, Data can be received in an interface with a protocol format, and the blender is transmitted through in directapath to separately Without carrying out sample rate conversion or scaling, data can be converted into different associations to one interface described in another interface View form.Again, the data can be sent to another interface without carrying out any sample rate conversion from an interface, i.e., Make when data are transmitted on other signal paths with different sample rates.

As mentioned above, on the basis of time division multiplex, blender is at any time between the path of all activities It is shared.In order to ensure the correct operation of equipment, it is necessary to the operation that the blender that suitably sorts is performed.

It is assumed that Ns signal source port and Nd signal destination port, by a possibility of required connection sequence Can be that selector circulation in destination is up to Nd DCLK cycle by these destination ports in turn, and source selector is at this Circulated during every group in a little groups of Ns DCLK cycles and pass through these source ports in turn.This can spend total [Ns.Nd] individual DCLK cycle.In order to simple, for only having peanut（Such as it is less than 10）The routing circuit of source and destination, this may It is an acceptable implementation method, but for more typically having such as 50 sources and 50 routing circuits of destination（It 2500 DCLK dock cycles of every SCLK period are may require that, even if when only several route segments are required to carry signal）, this is then It is very poorly efficient.

For using many arrangements of blender of Nm, all this can be lowered to [Ns.Nd/Nm] as shown in Figure 19, But this is still poorly efficient in the DCLK circulations for small Nm, and for big Nm in silicon area（silicon area）And electric power Consumption aspect is poorly efficient.Mixing of the destinations from even four data flows of signal source port is uncommon, institute Even if to circulate through all 50 destinations and allow up to four selector ports for each channel, can also subtract significantly The number of few required DCLK cycle（To 4 × 5=200）.Figure 14 illustrates routing circuit in, many destinations are shown It is that every channel has only one or two selector ports to go out, and this is proved to be efficient.And, in most of use examples, Only several destinations can be used, This further reduces the number of required DCLK cycle.

Thus, it is advantageous that be selector using only selecting route segment to be used（As limited in such as register mappings Fixed）Control circuit system.

When one is fixed, the number of the interim routing operations that can be performed depends on the number of blender, and according to Rely the ratio in data clock rate and data sampling rate.The number of the routing operations that can be required in theory depends on source port The number of number and destination port, and depend on the sample rate of data.In embodiment herein, as described above , the multiplexing of blender causes the number of the interim routing operations that can be performed when is fixed much smaller than in theory may be used The number of the routing operations to be required.For example, the number of the interim routing operations that can be performed can when one fixed With the percentage of a quarter of the number less than the routing operations that can be required in theory, 1/10th, 1/40th or One of.

Figure 38 is a timing diagram, exemplified with to being obtained from the use example described above with reference to Figure 32, Figure 34, Figure 35 and Figure 36 The first feasible pattern that the required sequence of maneuvers for going out is ranked up.

Thus, there are 12 data routing operations（That is, route segment）, each data routing operations needs are by regularly Scheduling, seven in them sample rates with 48k samples/secs, and other five sample rates with 8k samples/secs.This Operate a bit and identified by their register address, channel id and source ID and sample rate in Figure 38.

The clock cycle of data clock DCK is numbered at the top of the form, and these clock cycle each Period, whether each operation is indicated with pending（pending）Calculate, or whether that operation has been selected to meter Calculate.

Figure 38 shows a relatively simple situation, wherein with pending calculating and with minimum register address Operation is selected to calculate.Thus, to data clock cycle 1, all operations all have pending calculating, and in data clock week During phase 1, the operation in register address 010h is selected to calculate.During data clock cycle 2, in register ground The operation of location 010h no longer has pending calculating, and the operation in register address 014h is selected to calculate, with such Push away.

The data clock rate need to be set to it is sufficiently high, to cause that dispatching method makes data be wanted with for each operation The speed asked is calculated.

This is exemplified with reference to ensuing figure.

By the Figure 39 on the different pages（a）And Figure 39（b）Figure 39 of composition is the second timing diagram, exemplified with to required The second feasible pattern that sequence of maneuvers is ranked up, the sequence of maneuvers is retouched from above with reference to Figure 32, Figure 34, Figure 35 and Figure 36 What the use example stated drew.

Thus, as in Figure 38, there are 12 data routing operations of identical, each data routing operations needs Regularly dispatched, seven in them have the sample rate of 48kbps, and other five sample rates with 8kbps. These operations are identified in Figure 39 by their register address, channel id and source ID and sample rate, but in Figure 39, are had The operation of identical sample rate is merged in groups, and they are listed in each group according to their channel id order.

The clock cycle of data clock DCK is numbered at the top of the form, and these clock cycle each Period, indicate whether each operation has pending calculating, or whether that operation has been selected to calculate.

Figure 39 is also shown for for each operation " to the time of limit absolutely（time to deadline）", although it does not have Used by the dispatching method of Figure 39.Thus, must be performed during each each of operation in its corresponding SCK cycle Once, and the starting point of Figure 39 is the starting point of 8kHz sampling clocks and the starting point of 48kHz sampling clocks.Data clock DCK rates There are 72 DCK cycles during each cycle for being provided so that the 8kHz SCK, so as in each cycle of 48kHz SCK Period certainly exists 12 DCK cycles.（That is, the data clock rate is set to 576kHz）.

Therefore, " to the time of exhausted limit " during any given data clock cycle is in that sampling clock cycle knot Before beam（That is, " limited absolutely what the data routing operations must be performed（deadline）" before）Remaining data clock cycle Number.That is, for example, after six DCK cycles, remaining six DCK cycles before 48kHz SCK end cycles, and Remaining 66 DCK cycles before 8kHz SCK end cycles.

Figure 39 is exemplified with a dispatching method, wherein the operation with pending calculating and with highest sample rate is chosen To calculate.When there is pending calculating in the presence of two or more operations and with identical highest sample rate, with minimum The operation of channel id is selected to calculate.When there are two or more operations with identical lowest channel ID, with most The operation of low source ID is selected to calculate.

Thus, to data clock cycle 1, all operations all have pending calculating, and during data clock cycle 1, Operation in register address 014h is selected to calculate.（It is that have one of highest sample rate in seven operations, and It has minimum source ID in this seven with lowest channel ID two operations of operation.）

During data clock cycle 2, the operation in register address 014h no longer has pending calculating, and is in The operation of register address 016h is selected to calculate（It is that have highest sample rate in six with pending calculating operations One, and it has lowest channel ID in these operations）.During data clock cycle 3, in register address 058h Operation be selected to calculate because it is in five with pending calculating operations with highest sample rate, and It has lowest channel ID in these operations, by that analogy.

Thus, seven operations in the sample rate with 48k samples/secs are held during data clock cycle 1-7 After row, five operations with 8k samples/sec sample rates are performed during data clock cycle 8-12, because having Seven operations of the sample rate of 48k samples/secs do not have any pending calculating during data clock cycle 8-12.

For seven of the sample rate with the 48k samples/secs ensuing calculating of operation then in data clock cycle It is performed during 13-19, but is not operate in being performed during data clock cycle 20-24, because do not operate has Pending calculating.

Figure 39 shows the calculating completely for being slightly more than one circulation of this treatment.

Thus, Figure 39 shows that the data clock rate of use 576kHz is actually somewhat poorly efficient, because in some data Not having calculating during the clock cycle can be scheduled.

By the Figure 40 on the different pages（a）And Figure 40（b）Figure 40 of composition is the 3rd timing diagram, exemplified with to required The 3rd feasible pattern that sequence of maneuvers is ranked up, this sequence of maneuvers is from above with reference to Figure 32, Figure 34, Figure 35 and Figure 36 description Use example draw.

Thus, as in Figure 39, equally existed 12 data routing operations in Figure 38, each data routing operations It is required for regularly being dispatched, seven in them have the sample rate of 48kbps, and other five have adopting for 8kbps Sample rate.These operations are identified in Figure 40 by their register address, channel id and source ID and sample rate, but in Figure 40 In, as in Figure 39, the operation with identical sample rate is merged in groups, and they in each group according to they Channel id order is listed.

The clock cycle of data clock DCK is numbered at the top of the form, and these clock cycle each Period, indicate whether each operation has pending calculating, or whether that operation has been selected to calculate.

Figure 40 is also shown for " to the time of limit absolutely " for each operation, although it is not made by the dispatching method of Figure 40 With.

Data clock DCK rates are provided so that there are 48 DCK cycles during each cycle of 8kHz SCK, so that 8 DCK cycles are certainly existed during each cycle of 48kHz SCK.（That is, the data clock rate is arranged to 384kHz）.

Figure 40 also exemplified with Figure 39 identical dispatching methods, wherein with it is pending calculating and with highest sample rate Operation is selected to calculate.There is pending calculating and with identical highest sample rate when there are two or more operations When, the operation with lowest channel ID is selected to calculate.There is identical lowest channel when there are two or more operations During ID, the operation with minimum source ID is selected to calculate.（When selection operation is to calculate, channel id is needed prior to source ID, All selected one by one with the active ID of institute for ensuring the data source for serving as individual data destination.）

Thus, to data clock cycle 1, all operations all have pending calculating, and during the clock cycle 1, are in The operation of register address 014h is selected to calculate.（It is that have one of highest sample rate in seven operations, and it Have two of lowest channel ID in this seven operations has minimum source ID in operating.）

During the clock cycle 2, the operation in register address 014h no longer has pending calculating, and in deposit The operation of device address 016h is selected to calculate（It is with highest sample rate one in six operations with pending calculating It is individual, and it has lowest channel ID in these operations）.During data clock cycle 3, in register address 058h's Operation is selected to calculate, because it is one with highest sample rate in five operations with pending calculating, and it There is lowest channel ID in these operations, by that analogy.

Thus, seven operations in the sample rate with 48k samples/secs are held during data clock cycle 1-7 After row, five of the sample rate with 8k samples/secs operations still have pending calculating, but the sample rate with 48k samples/secs Seven operations are without any pending calculating.

During data clock cycle 8, the operation in register address 010h is selected to calculate（With pending calculating Five operations have an identical sample rate, and it has lowest channel ID in these operations）.

During data clock cycle 9, the new SCK cycle of 48kHz SCK, so having 48k samples/secs Seven operations of sample rate have pending calculating again now.Thus, seven behaviour of the sample rate with 48k samples/secs Work is performed during data clock cycle 9-15, with order as before.After data clock cycle 15, have Without any pending calculating, the operation in register address 010h is not also appointed for seven operations of the sample rate of 48k samples/secs What pending calculating.Therefore, during data clock cycle 16, the operation in register address 06Eh is selected to calculate（Tool Four operations for having pending calculating have identical sample rate, and it has lowest channel ID in these operations）.

This treatment is repeated, wherein five of the sample rate with 8k samples/secs operations data clock cycle 8,16, 24th, it is performed during 32 and 40.Figure 40 shows the circulation of calculating completely of slightly more than, can see from here, uses The data clock rate of 384kHz is enough to allow all required calculating to be scheduled.In fact, during data clock cycle 48 There is no calculating to be performed, because not operating with pending calculating.

By the Figure 41 on the different pages（a）And Figure 41（b）Figure 41 of composition is the 4th timing diagram, exemplified with to required The 4th feasible pattern that sequence of operations is ranked up.

In Figure 41 embodiments illustrated, there are 12 data routing operations of identical, each data routing operations is needed Regularly to be dispatched, but in that case, seven sample rates of the operation with 44.1k samples/secs of higher data, And other five sample rates with 8k samples/secs.These operation in Figure 41 by their register address, channel id and Source ID and sample rate are identified, and in Figure 41, as in Figure 39, as in Figure 40, the operation with identical sample rate is closed And in groups, and they are listed in each group according to their channel id order.

The clock cycle of data clock DCK is numbered at the top of the form, and in each phase of these clock cycle Between, indicate whether each operation has pending calculating, or whether that operation has been selected to calculate.

Figure 41 is also shown for " to the time of limit absolutely " for each operation, although it is not made by the dispatching method of Figure 41 With.

Data clock DCK rates are provided so that there are 8 DCK cycles during each cycle of 44.1kHz SCK. That is, the data clock rate is set to 352.8kHz.The 8kHz speed is synchronous with this data clock rate, thus one 8kHz weeks Phase can contain 44 or 45 DCK cycles.In illustrated implementation method, it is assumed that the worst situation, because can not predict Which will will contain 45 DCK cycles in cycle in cycle containing 44 DCK cycles and which.It follows that each 8kHz cycle All contain 44 DCK cycles.

" heap sandbag method is all used in the case of all these illustrations（sandbagging）" be also it is feasible, especially When definite sampling clock rate is unaware of in advance.If for example, the data of the nominal sampling clock rate with 44.1kHz are adopted Sample rate is substantially independent of the DCK, then actually it can be less than 44kHz in some cases, so in order to safety can be with vacation Fixed each 8kHz cycle contains only 43 DCK cycles.

" study circulation was included before calculation stages（learning cycle）" it is also feasible, in study circulation really Fixed actual sampling clock rate.Thus, during the initial period, the sampling clock rate of these signals is measured and measured Sampling clock rate be used as the basis of follow-up scheduling.

Figure 41 exemplified with Figure 39 and Figure 40 identical dispatching methods, wherein with it is pending calculating and with highest sampling The operation of rate is selected to calculate.There is pending calculating and with the sampling of identical highest when there are two or more operations During rate, the operation with lowest channel ID is selected to calculate.There is the minimum letter of identical when there are two or more operations During road ID, the operation with minimum source ID is selected to calculate.

Thus, in the beginning of data clock cycle 1, all operations all have pending calculating, and in phase clock cycle 1 Between, the operation in register address 014h is selected to calculate.（It is that have one of highest sample rate in seven operations, And it has minimum source ID in having two operations of lowest channel ID in being operated at this seven.）

During data clock cycle 2, the operation in register address 014h no longer has pending calculating, and is in The operation of register address 016h is selected to calculate（It is that have highest sample rate in six with pending calculating operations One, and it has lowest channel ID in these operations）.During data clock cycle 3, in register address 058h Operation be selected to calculate because it is in five with pending calculating operations with highest sample rate, and It has lowest channel ID in these operations, by that analogy.

Thus, seven in the sample rate with 44.1k samples/secs operate the quilt during data clock cycle 1-7 After execution, five operations of the sample rate with 8k samples/secs still have pending calculating, but with the sampling of 44.1k samples/secs Seven operations of rate are without any pending calculating.

During data clock cycle 8, the operation in register address 010h is selected to calculate（With pending calculating Five operations have an identical sample rate, and it has lowest channel ID in these operations）.

During data clock cycle 9, the new SCK cycle of 44.1kHz SCK, so having 44.1k samples Seven operations of the sample rate of sheet/second have pending calculating again now.Thus, sample rate with 44.1k samples/secs Seven operations are performed during data clock cycle 9-15, with order as before.After data clock cycle 15, Seven operations of the sample rate with 44.1k samples/secs are without any pending calculating, the operation in register address 010h There is no any pending calculating.Therefore, during data clock cycle 16, the operation in register address 06Eh is selected to meter Calculate（This four operations with pending calculating have identical sample rate, and it has lowest channel ID in these operations）.

This treatment is repeated, wherein five of the sample rate with 8k samples/secs operations data clock cycle 8,16, 24th, it is performed during 32 and 40.

Because the data clock illustrated in Figure 41 runs somewhat slower than the data clock illustrated in Figure 40, the 8kHz The SCK cycles of SCK terminate at data clock cycle 44, and five therefore with 8kbps sample rates are operated from data clock The DCK cycles 45 have pending calculating backward.

It means that during data clock cycle 48, the operation in register address 010h can be selected to meter Calculate.

Figure 42 is another timing diagram, exemplified with another feasible pattern being ranked up to required sequence of maneuvers. In order to illustrate the difference of this sort method and sort method described above, there are 14 data routing operations now, often Individual data routing operations are required for regularly being dispatched, seven in them sample rate of the operation with 48k samples/secs, and And other seven sample rates with 32k samples/secs.These operation in Figure 42 by their register address, channel id and Source ID and sample rate are identified.In Figure 42, the operation with identical sample rate is merged in groups, and they are in each group Channel id order according to them is listed.

The clock cycle of data clock DCK is numbered at the top of the form, and in each phase of these clock cycle Between, indicate whether each operation has pending calculating, or whether that operation has been selected to calculate.

Must be executed once during each each in its corresponding SCK cycle of operation, and Figure 42 starting point It is the starting point of 32kHz sampling clocks and the starting point of 48kHz sampling clocks.Data clock DCK rates are provided so that 32kHz There are 18 DCK cycles during each cycle of SCK, so as to certainly exist 12 during each cycle of 48kHz SCK DCK weeks Phase.（That is, the data clock rate is arranged to 576kHz）.

Figure 42 is also shown for " to the time of limit absolutely " for each operation.Therefore, any given data clock cycle " to the time of exhausted limit " of period is before that sampling clock cycle terminates（That is, must be held in the data routing operations Before capable " limit absolutely "）The number of remaining data clock cycle.That is, for example, in six counted from the starting point of Figure 42 DCK weeks After phase, remaining six DCK cycles before 48kHz SCK end cycles, and it is remaining before 32kHzSCK end cycles 12 DCK cycles.

Figure 42 is exemplified with a dispatching method, wherein being calculated and with the behaviour of most short " to the time of limit absolutely " with pending It is selected to calculate.It is with pending calculating and most short " to limit absolutely with identical when there are two or more operations Time " when, the operation with highest sample rate be selected to calculate.There is pending calculating when there are two or more operations And with identical most short " to the time of limit absolutely " and during identical highest sample rate, the operation with lowest channel ID It is selected to calculate.When there are two or more operations with identical lowest channel ID, the operation with minimum source ID It is selected to calculate.

Thus, before data clock cycle 1, all operations all have pending calculating, and in the phase of data clock cycle 1 Between, the operation in register address 014h is selected to calculate.（It is seven operation in have identical it is most short " to absolutely limit Time " and one of highest sample rate, and have in it is operated at this seven in two operations of lowest channel ID and have Minimum source ID.）

During data clock cycle 2, the operation in register address 014h no longer has pending calculating, and is in The operation of register address 016h is selected to calculate（It is have in six with pending calculating operations it is most short " to limit absolutely Time " and one of highest sample rate, and it has lowest channel ID in these operations）.In data clock cycle 3 Period, the operation in register address 058h is selected to calculate, because it is five operations with pending calculating In there is most short " to the time of limit absolutely " and one of highest sample rate, and it has lowest channel in these operations ID, by that analogy.

Thus, seven operations in the sample rate with 48k samples/secs are held during data clock cycle 1-7 After row, seven operations of the sample rate only with 32k samples/secs have pending calculating, and therefore five in this seven operations （That is, five operations with lowest channel ID）It is performed during data clock cycle 8-12.

Before data clock cycle 13, a new SCK cycle of 48kHz sampling clock cycles, therefore have Seven operations of the sample rate of 48k samples/secs, and in seven operations of the sample rate with 32k samples/secs remaining two It is individual, with pending calculating.

During data clock cycle 13, the operation in register address 064h is selected to calculate（" arrived with most short With pending calculating two operations of the time for limiting absolutely " have identical sample rate, and it has relatively low channel id among this）. Similarly, during data clock cycle 14, the operation in register address 065h is selected to calculate（It has now The sole operation with pending calculating of most short " to the time of limit absolutely "）.

It should be noted that therefore this dispatching method generates the results different from dispatching method described above, retouched above In the dispatching method stated, during data clock cycle 13 and 14, in the operation of the sample rate with 48k samples/secs higher Two scripts can be selected to calculate.In fact, other dispatching methods described above can not improve data originally All required operations are dispatched in the case of clock rate.

During data clock cycle 15-18, the operation of the sample rate with 32k samples/secs " arrives what is limited absolutely with most short Time ", but they are all without pending calculating, therefore preceding four operations in the operation of the sample rate with 48k samples/secs are selected Select to calculate.

Before data clock cycle 19, a new SCK cycle of 32kHz sampling clocks, so having 32k samples Seven operations of the sample rate of sheet/second have pending calculating.However, the operation with 48kbps sample rates is now with most short " to the time of limit absolutely ", therefore during data clock cycle 19-21, in the operation of the sample rate with 48k samples/secs after Three operations are selected to calculate.

During data clock cycle 22-24, the operation of the sample rate with 48k samples/secs " arrives what is limited absolutely with most short Time ", but they are all without pending calculating, therefore first three operation in the operation of the sample rate with 32k samples/secs is chosen Select to calculate.

Before data clock cycle 25, a new SCK cycle of 48kHz sampling clocks, therefore with 48k samples Seven operations of the sample rate of sheet/second, and the residue four of the sample rate with 32k samples/secs is operated, and is had not definitely Calculate.

Additionally, all operations with pending calculating have identical " to the time of limit absolutely ", therefore the sample rate now It is used as selection basis, and there are seven operation quilts of the sample rate of 48k samples/secs during data clock cycle 25-31 Select to calculate, it means that remaining four operations of the sample rate with 32k samples/secs are until data clock cycle 32-35 Just it is selected for calculating.In data clock cycle 36, there is no operation to have pending calculating.

Figure 43 illustrates in greater detail the clock forming circuit 80 shown in Fig. 3.Clock forming circuit 80 includes FLL （FLL）1100, for being in the first clock frequency from input clock signal generation（C_F1）The first clock signal.Illustrated In embodiment, FLL1100 can receive the first master clock signal and the second master clock signal.For example, first master clock is believed Number and second master clock signal can be generated with audio hub integrated circuit, or can be from piece external source （The crystal oscillator of the other purposes being such as used in the equipment containing audio hub, or USB clock sources）Receive. FLL1100 also receives the control signal for controlling the FLL, to cause that first clock signal is generated with desired frequency, No matter which master clock signal can use at that time.In illustrated embodiment, first clock frequency is 49.152MHz, i.e., 1024 × 48kHz, as commonly used in audio system and application.

First clock signal is sent to the first frequency divider 1102, and the first frequency divider 1102 removes first clock frequency With 2, second clock frequency is in generate（C_F2）Second clock signal.Thus, in illustrated embodiment, this second Clock frequency is 24.576MHz.The second clock signal is sent to the second frequency divider 1104, the second frequency divider 1104 by this Two clock frequencies are in the 3rd clock frequency divided by 2 to generate（C_F3）The 3rd clock signal.Thus, in illustrated implementation In scheme, the 3rd clock frequency is 12.288MHz.3rd clock signal is sent to tri-frequency divider 1106, the 3rd point 3rd clock frequency divided by 2, the 4th clock frequency is in generate by frequency device 1106（C_F4）The 4th clock signal.Thus, In illustrated embodiment, the 4th clock frequency is 6.144MHz.

First clock signal is also sent to first switch 1108, and the second clock signal is sent to second switch 1110, the 3rd clock signal is sent to the 3rd switch 1112, and the 4th clock signal is sent to the 4th switch 1114。

Chip includes multiple IP blocks（That is, functional block）1120th, 1122,1124, wherein only three are illustrated in Figure 43, Although it will be appreciated that, there will be much more such block in reality.For example, IP blocks 1120,1122,1124 can be programmable Digital signal processing block, or the digital signal processing block with fixing function, as described above.Especially, it is desirable to IP blocks 1120,1122, one of 1124 should be blender described above.

For each in IP blocks 1120,1122,1124, there is a preferred clock frequency.This preferred clock is frequently Rate can be fixed, or it can load and change according to the treatment of special time.Especially, blender described above It is preferred that clock frequency changes the number of signal path processed as needed, as described in reference picture 38 to Figure 42.

Each in IP blocks 1120,1122,1124 is associated with a corresponding multiplexer 1126,1128,1130.Multiplexer 1126th, each in 1128,1130 is received in this four clock rate Cs_F1、C_F2、C_F3、C_F4All four clock letter Number.

In IP blocks 1120,1122,1124 each at least that particular moment to corresponding multiplexer 1126, 1128th, 1,130 one control signal of transmission, indicates preferred clock frequency.Thus, each multiplexer 1126,1128,1130 to The IP blocks 1120,1122,1124 that it is associated transmit a clock signal in the preferred clock frequency.This has following excellent Gesture：Each IP block can operate in following clock frequency, the sufficiently high function with required by offer of the clock frequency, but not have Have high to unnecessarily consumption electric power.

Advantageously, although IP blocks 1120,1122,1124 can be physically located at any position in chip, association Multiplexer 1126,1128,1130 is physically close to FLL1100 and frequency divider 1102,1104,1106.This has the effect that：When Clock signal is not distributed to not require their IP blocks.

Further, the control signal of the their own preferred clock frequency of instruction for being generated by IP blocks 1120,1122,1124 It is also sent to logical block 1136.This is determined, for clock rate C_F1、C_F2、C_F3、C_F4In each, if there is requirement The IP blocks of that clock frequency.

For the clock rate C required by least one of these IP blocks_F1、C_F2、C_F3、C_F4In each, logical block 1136 ensure that corresponding switch 1108,1110,1112,1114 is remained closed（closed）.If however, clock rate C_F1、 C_F2、C_F3、C_F4One of do not needed by any IP blocks, then logical block 1136 ensure that corresponding switch 1108,1110,1112,1114 Remain open（open）.This has following advantage：Even if by this clock signal distribution as far as multiplexer 1126,1128, When 1130, also will not unnecessarily consumption electric power.

Figure 44 illustrates in greater detail a form for replacement of the clock forming circuit 80 shown in Fig. 3.

The chip include multiple blocks 1200.1,1200.2 ..., 1200.M, wherein only first is illustrated in detail in figure In 44.For example, block 1200.1,1200.2 ..., 1200.M can be programmable digital signal processing block, or have The digital signal processing block of fixing function, as described above.Especially, it is desirable to block 1200.1,1200.2 ..., One of 1200.M should be blender described above.

Block 1200.1,1200.2 ..., each in 1200.M answers for 1210, one N: 1 comprising a corresponding functional block With device 1212 and control logic 1214.For block 1200.1,1200.2 ..., each in 1200.M have one preferably Clock frequency.This preferred clock frequency can be fixed, or it can load and change according to the treatment of special time. Especially, the preferred clock frequency of blender described above changes the number of signal path processed as needed, such as It is described above.

Clock generator 1216 can with N number of frequency produce clock signal, be in this embodiment 49.152MHz, 24.576MHz, 12.288MHz and 6.144MHz.

IP blocks 1200.1,1200.2 ..., each in 1200.M at least in that special time to M: N OR gate 1218 one N signal of transmission, indicate its preferred clock frequency.IP blocks 1200.1,1200.2 ..., 1200.M wishes When changing its preferred clock frequency, it wishes the frequency that changes to the signal designation that it is transmitted to M: N OR gate 1218, but also refers to Show its current frequency untill when the change has been realized.

Therefore, the output of OR gate 1218 is a N signal, indicate in usable frequency which by block 1200.1, 1200.2nd ..., any one requirement in 1200.M.

Therefore, clock generator 1216 only generate in by block 1200.1,1200.2 ..., one in 1200.M or The clock signal of those frequencies required by multiple.

Each clock signal for being generated is sent to each in N: 1 multiplexer 1212, and each block 1200.1, 1200.2nd ..., the control logic 1214 in 1200.M selects the frequency required by corresponding functional block 1210.Preferably, it is multiple It is located at clock generator 1216 with device 1212（Although this may be relatively distant from their own functional block 1210）, this is Because this reduce transmitting the power loss that unnecessary high-frequency clock signal is associated with along path long.

In addition, clock generator 1216 sends control signal to power control block 1220, the highest that it is being generated is indicated Frequency.Then to the sending signal of power supply 1222, the signal controls its output voltage to power control block 1220, and the output voltage is As supply voltage to block 1200.1,1200.2 ..., each voltage for supplying in 1200.M.

Generally, if functional block is run with slower clock, it can be with relatively low service voltage（supply voltage）Operation.（Therefore, according to the clock rate of difference in functionality block, different service voltage meetings are provided to different functional blocks It is feasible.）If however, providing identical service voltage to each functional block, can realize that the more efficient of silicon is used. Therefore, in this embodiment, identical service voltage is provided to each functional block, but this is according to any one function Block supply maximum clock frequency and change.

Figure 44 a illustrate in greater detail a form for replacement of the clock forming circuit 80 shown in Fig. 3.The replacement Clock forming circuit 80.1 includes FLL（FLL）1100, for being in the first clock frequency from input clock signal generation （C_F1）The first clock signal.In illustrated embodiment, FLL1100 can receive the first master clock signal and the second master Clock signal.For example, first master clock signal and second master clock signal can be in the audio hub integrated circuits certainly It is generated with it, or can is from piece external source（The crystal of the other purposes being such as used in the equipment containing audio hub Oscillator, or USB clock sources）Receive.FLL1100 also receives the control signal for controlling the FLL, with cause this first when Clock signal is generated with desired frequency, no matter which master clock signal can use at that time.In illustrated embodiment, this One clock frequency is 49.152MHz, as commonly used in audio system and application.

As in Figure 43, in order to the purpose for illustrating shows three IP blocks 1120,1122,1124.Each IP block There is the preferred clock frequency of its own, and their own preferred clock is indicated by what IP blocks 1120,1122,1124 were generated The control signal of frequency is also sent to logical block 1136.1.

The clock signal generated by FLL1100 is sent to pulse in the form of clock gate and jumps over block（pulse skip block）1140.Pulse is jumped over control block 1142 and contains counter, for counting the arteries and veins in the clock signal generated by FLL1100 Punching.The control signal for jumping over control block 1142 from pulse is sent to multiplexer 1144 and control distribution block 1146.Specifically, In this embodiment for illustrating, pulse is jumped over control block and generates four data-signals, in four available clocks frequently Rate, i.e. 49.152MHz, 24.576MHz, 12.288MHz and 6.144MHz.

Logical block 1136.1 be determined in this four available clock frequencies which be IP blocks 1120,1122,1124 Any one desired maximum clock frequency.Based on the determination, the control multiplexer 1144 of logical block 1136.1, to cause to be in that The data-signal of individual highest frequency is sent to the control input that block 1140 is jumped in pulse.Used as response, block 1140 is jumped in pulse Can jump over by FLL1100 generate clock signal in a certain ratio pulse, with generate in IP blocks 1120,1122, The clock signal of the maximum clock frequency required by any one in 1124.This clock signal is then jumped over control from pulse Clamp dog 1140 is sent to the pulse for being associated with these three IP blocks 1120,1122,1124 respectively and jumps over block 1148,1150,1152.Arteries and veins Punching jump in block 1148,1150,1152 each controlled by a corresponding multiplexer 1154,1156,1158.

This four data-signals in this four available clock frequencies are also jumped over control block 1142 and are sent to from pulse Control distribution block 1146, control distribution block 1146 also receives control signal from logical block 1136.1.Specifically, logical block 1136.1 Which in this four available clock frequencies is determined required by one or more in IP blocks 1120,1122,1124.It is based on This determination, control distribution block 1146 ensure that in by IP blocks 1120,1122,1124 one or more require this frequently The data-signal of rate or each frequency is sent to multiplexer 1154,1156,1158.Thus, control distribution block 1146 is shielded The data-signal of the frequency in not needed by any one in IP blocks 1120,1122,1124, to cause them not in the core Unnecessarily it is fanned out on piece.

In IP blocks 1120,1122,1124 each be connected with to the multiplexer 1154 of its respective associated, 1156, 1158 send control signal, are sent in the IP blocks with causing that the multiplexer jumps over block 1148,1150,1152 to the pulse of association It is required that frequency data-signal.Pulse is jumped over block 1148,1150,1152 and then causes to jump over and jumps over block 1140 from pulse Clock signal in required a part of pulse, to cause that the clock signal in required frequency is sent to accordingly IP blocks 1120,1122,1124.

This has following advantage：The clock signal is allocated along single path, no matter frequency.While in difference The data-signal of frequency is allocated, but they need not be balanced, so they can be propagated on chip, and without the need for pass The length of signal path is noted, because sequential is less problem for the signal of these lacks of equilibrium.

Figure 44 b illustrate in greater detail the still another embodiment of the clock forming circuit 80 shown in Fig. 3.This is replaced The clock forming circuit 80.1 in generation is similar to the clock forming circuit 80.1 of the replacement shown in Figure 44 a, and with the spy of Figure 44 a The feature with identical function is levied to be indicated with identical Ref. No..

In the embodiment shown in Figure 44 b, there is each IP block 1120,1122,1124 a corresponding pulse to jump over Controller 1160,1162,1164, the pulse is jumped over controller 1160,1162,1164 and jumps over control block 1142 from pulse and receives One corresponding signal.Based on the corresponding signal that the reception of control block 1142 is jumped over from pulse, controller is jumped in each pulse 1160th, 1162,1164 cause its respective pulse jump over block 1148,1150,1152 jump over from pulse jump over block 1140 when Required a part of pulse in clock signal, to cause that the clock signal in required frequency is sent to corresponding IP Block 1120,1122,1124.

It means that sending only one synchronizing signal to each IP block, control letter is jumped over rather than greater number of pulse Number.

Figure 44 c show an alternative solution to Figure 44, are shown exemplified with clock generation such as Figure 43 a or Figure 43 b As source voltage control in the case of be performed.In that case, only one clock is assigned to IP blocks 1200.Further It is secondary, jumped under the control of block 1226 in selection control signal and pulse, there is pulse to jump over control signal and be assigned to these IP blocks, To allow that each IP block selects suitable pulse to jump over rate and jumps over the pulse of that clock, frequency is expected to provide to have The clock of rate.As described in before with reference to Figure 44, the source voltage is based on required sampling clock and is controlled.

Figure 45 to Figure 55 is illustrated in more detail the blender in one embodiment of the invention --- in such as Figure 15 The blender 290 for showing --- operation.Figure 45 is a block diagram, exemplified with the functional structure of the blender and other Hold；Figure 46, Figure 47 and Figure 48 are flow charts, exemplified with some parts of operation of the blender；Figure 49 is a block diagram, more in detail Carefully exemplified with the enable in the blender and clock control block；Figure 50 is a flow chart, illustrates in greater detail Figure 48's A part for method；Figure 51 is a flow chart, and fallout predictor is utilized exemplified with the MAC in the blender（utilisation predictor）The method of middle execution；Figure 52 is a block diagram, and the channel scheduler block in the blender is illustrated in more detail； Figure 53 is a flow chart, the method exemplified with being performed in the channel scheduler；Figure 54 is a block diagram, exemplified with the mixing Calculating streamline in device；And Figure 55 is a flow chart, held exemplified with the channel scheduler and the calculating streamline Capable method.

In the description of Figure 45 to Figure 55, term " channel " is used to refer to signal destination port, and it is from the mixing Device to specific DSP functions output, or from the output of chip：One channel has unique address, to cause output data Can be sent in shared bus.Each output channel has one or more " selectors ", and each selector is represented and arrives defeated Enter a possible connection of signal or signal source port：One selector have a register for association with by it defeated Enter the address in bus to select input signal, and alternatively there is a register for association to apply with to that route segment Gain coefficient.

Exemplified with the overall functionality structure of blender, and Figure 46 is a flow chart to Figure 45, there is provided audio compiles solution The overview of the operation of the blender in code device.

The blender 600 shown in Figure 45 includes register banks 602, and the register banks 602 are answered on control interface 650 Programmed with processor, the control interface is then by System Programming person（Such as user）Programming, sets required with the blender Connection, comprising gain control and to one of available sampling rate distribute each channel.Thus, corresponding to making that each has been programmed The operation of use-case is stored in the memory associated with the application processor, and the application processor also monitors the shape of whole equipment State.Operation corresponding to the use example of activity is then downloaded to register banks 602 based on this state.Thus, for example, working as intelligence Energy phone is used to during by the music playback that for example external system 23 will be recorded, for the relevant operation quilt of that use example Storage is in register banks 602.When call starts, the use example for manipulating audio call is downloaded.When the equipment User insertion head-mounted machine when, the relevant operation for that use example is downloaded to register banks 602, by that analogy.

Enable and clock control block 604 controls which input selector/defeated based on user by the request of register banks Go out channel to be enabled and disable.

That is, in any given time, register banks 602 indicate whether each selector to enable and clock control block 604 All it is requested and enables, and indicates the sample rate of each channel and the frequency of each SCK.

When having completed write-in of the data to register banks 602（Step 680 in Figure 46）When, enable and clock control block 604 also control clock transmissions（clock gearing）, so as to the data clock of blender must be used for（DCK）Can be scaled to Appropriate frequency.That is, it has decided on whether the data clock（DCK）It is sufficiently fast（Step 682 in Figure 46）, and if it too It is slow then adjust it（Step 684 in Figure 46）.Indicate the mark of which selector activity（flag）Quilt in 686 the step of Figure 46 Set（set）.

Channel dispatch block 620 chooses the next output channel for waiting to be calculated.Figure 47 is a flow chart, exemplified with letter The method performed in road Scheduling Block 620.Thus, when a new data clock（DCK）Along when being detected（In Figure 47 Step 688）, channel dispatch block 620 update it to sampling clock（SCK）Monitoring, to determine for each sampling clock rate To the time of exhausted limit, as described in more detail below.

Figure 48 is another flow chart, shows the method performed in channel dispatch block 620 and in calculating block 630. In this embodiment, the selection of channel dispatch block 620 has earliest the channel of limit absolutely as next channel waited and calculated （Step 694 in Figure 46）.Selected channel is notified to calculating block 630, and the calculating block 630 generation is directed to selected letter The output in road（Step 696 in Figure 48）, and this is repeated, until all calculating for being required in that SCK cycle all by Complete.

The control of streamline block 630 is calculated to obtain for an output sample value（output samplevalue）Data, And perform the calculating of the output sample value.In streamline block 630 is calculated, in some data clocks（DCK）Performed on cycle Calculate, as described above.Each output valve can need the data that combination is input into from one or more, and in channel meter Calculate operation under the control of control block 634.Therefore, control block 634 obtains the letter of next calculating to be performed from scheduler 620 Road ID（That is, OPADD）, and control block 634 then sends bus control signal and the control signal for MAC292, MAC292 iteration（iterate）These calculation procedures.

Once the final step of the calculating has been performed, with regard to the OPADD using the channel by result via output bus （Op_all buses）640 are sent to suitable output buffer 642.As described above, output buffer 642 and corresponding letter The association of number destination, and make each a cycle of output sample after the cycle that the executed about sampling clock is calculated The whole duration on can use.Output then can be in certain o'clock during that ensuing sampling clock cycle via a phase The output bus 644 answered is transferred to the output of plan.

As mentioned above, thus it is possible to vary data clock DCK frequencies, and preferably data clock DCK frequency quilts Being maintained at can be performed the low-limit frequency being consistent with all required operations are ensured, advantageously to make power consumption minimum Change.Thus, as shown in Figure 49, and as described in more detail below, enable and clock control block 604 is included：Selector Status block 606, it is movable that it indicates which operation in any one time；And MAC utilizes fallout predictor（MUP）Function 608, It is determined that for it is being currently enabled or be required enable all selectors perform calculate required by data clock（DCK）'s Minimum frequency.

Figure 50 is a flow chart, exemplified with a method by enabling and clock control block 604 is performed.

The method of Figure 50 starts in step 720, but treatment just starts in step 722, has now completed to write data into Register banks 602（What the step 680 such as in Figure 48 was also showed that）.

In step 724, it is determined which selector in possible selector is desired in that specific time.Such as What reference picture 49 was more fully described, if certain selector is asked in that time by one of processor, and/or if should Selector keeps being " current（current）", then the selector is determined to be and " is expected to（desired）".

As shown in Figure 49, for each the possible selector input for each channel, enable and clock control block 604 all contain a selector status block 606, for clarity, illustrate only such selector status block in Figure 49 606。

Each selector status block 606 receives right comprising each multiplexer in multiplexer 750, and these multiplexers Should be in all available sampling clocks（SCK）Speed input.Each multiplexer 750 receives a selection input, corresponding to suitable In the SCK of the channel associated with that selector,.Latch 752 is then in each of that suitable sampled clock signal Edge is risen to be timed.

Each selector status block 606 also receives mark on its incoming line 754, and the mark represents that specific choosing Select device whether " requested（requested）", i.e. whether it is identified as just being used in these activities by register banks 602 One of use example in.Selector " requested " mark is sent to an input with door 756, and is also sent to lock Storage 758, latch 758 only " is agreed to when it receives the DCK from clock drive control block 610（OK）" signal（Indicate to work as Preceding data clock（DCK）It is fast that rate can receive ground）When the mark just is continued to be sent to the second input with door 756.If should DCK clock frequencies are currently insufficient to fast but can be accelerated, then this this selector can be processed with temporary dam, until this plus Speed has occurred.If the DCK clock frequencies are in maximum, this can forever stop that the selector becomes operable.

If selector " requested " mark is set and is also transmitted by latch 758, generated with door 756 and selected Device " activity " indicates.Selector " activity " mark is sent to latch 752, based on the control letter supplied from multiplexer 750 Number, by selector " activity " mark, alternatively " current " mark of device continues to transmit the latch 752.The selector " activity " Mark is also sent to channel scheduler, as described in more detail below.

The ID of these selectors that selector " current " mark is set is sent to the channel meter for calculating streamline block 630 Calculate control block 634.These selectors are operational, and need to be processed in the present sample clock cycle.Thus, when one When individual selector is requested, it will be changed into " activity " first, but start just to be changed into " current " until its next SCK cycles, When perhaps it can not possibly be dispatched, to prevent this from just occurring before a SCK end cycle.

And, selector " requested " signal and the selector " current " signal are sent to OR gate 760, and In each selector status block 606 output of corresponding OR gate alternatively device " be expected to " position be sent to MAC using treatment Device（MUP）Block 608.Therefore, when it is determined that during required data clock rate, the selector that " being expected to " mark is set is included into Consider, as described below." being expected to " mark is somebody's turn to do in any selector set accordingly, for " requested ", even if should Selector not yet becomes " activity "；And indicate also for keeping any selector set of " current " to be somebody's turn to do " being expected to ", even if The selector has stopped by " requested " or " activity ".

Enable and clock control block 604 is also comprising the SCK status blocks 762 for each SCK.Each SCK status block is controlled The frequency of its corresponding SCK, when especially managing the transformation from a frequency to another frequency when called upon.In a reality Apply in example, the number of SCK status blocks 762 may, for example, be four, it means that there can be four differences in any one time SCK can use.However, this four SCK can be selected from the bigger one group SCK for having become potentially useful.

When the SCK clocks in CF are required, SCK fre_q[1] register is changed to the frequency for representing new demand The value of rate.The register value can be mapped to the frequency with any convenient mode.If there is certain sequentially with cause This mapping can be selected as matching and be used for the specific industrial standard of configuration data rate in one embodiment, then the implementation method It is simplest.For example：1=12kHz；2=24kHz；3=48kHz；Etc.；9=11.025kHz；10=22.05kHz；11= 44.1kHz；12=88.2kHz；Etc.；16=4kHz；17=8kHz；18=16kHz；Etc..This value represents new frequency and is transmitted To latch 764, it is latched until the change can be scheduled herein.

Latch 764 is controlled by OR gate 766.One input of OR gate 766 is that above mentioned transmission from clock controls DCK " agreement " signal of block 610, it indicates current data clock（DCK）Rate is acceptably fast.Second input of OR gate 766 The output of comparator 768, it is determined that the SCK frequencies of new request whether less than current active SCK frequencies.If it is determined that Current data clock（DCK）Rate is acceptably fast, or if it is determined that the SCK frequencies of the new request are less than current active SCK frequencies, then the SCK frequencies of the new request be transmitted through latch 764, to cause that it becomes the SCK frequencies of current active. This frequency is then sent to the Down-counter in the channel scheduler, as described in more detail below.

Motion frequency is also sent to the second latch 770, and second latch 770 is controlled by SCK clock signals.This is true The motion frequency has been protected until the beginning of next SCK clock cycle can just become " current " frequency.When the change occurs, refer to Show that the signal of " current " frequency is sent to SCK makers, the SCK makers cause that the signal is generated with that frequency.

The signal of " requested " SCK frequencies, " activity " SCK frequencies and " current " SCK frequencies is indicated to be sent to block 772, Block 772 determine these frequencies in which be highest.When determining whether that all required SCK frequencies can be in current DCK When rate is scheduled, the highest frequency in these three frequencies represents the worst situation.Therefore, the output of block 772 is transferred back to MUP608, allows it is determined that whether current DCK rates are suitable, as described in more detail below.

Figure 50 illustrates treatment the step of 726 in, MUP blocks 608 calculate required minimum DCK frequencies, to allow All required operations are scheduled all in their corresponding sampling clock cycles.

Figure 51 is a more detailed flow chart, and processor is utilized exemplified with MAC（MUP）The treatment performed in block 608.

The treatment of Figure 51 starts in step 778, and the value stored in accumulator is eliminated in step 780.

In step 784, one of these SCK, SCK (n) are selected, and count the selector associated with that SCK（For The selector, MUP blocks 608 have received selector and " are expected to " position from corresponding OR gate 760）Number.The count value is in step The first number is increased in rapid 786, with view of via the delay for calculating streamline.Recognize that single flowing water line computation spends 5 Individual DCK cycles, first number may, for example, be 5.The count value is increased the second number in step 788, with view of when changing Possible delay when becoming the SCK rates in the calculating streamline block.Second number may, for example, be 3, i.e. than the choosing of every channel The maximum number for selecting device is small by one.

Therefore, increased count value is represented in the worst cases to the choosing for owning " being expected to " in that SCK rate Select the conservative estimation of the possibility effect of device.

In step 790, the random time cycle is defined.For convenience, that random time cycle can be configured so that The least common multiple in the cycle of the signal in available SCK rates.For example, if available SCK rates are 8kHz and 48kHz, Their cycle is 1/ (8kHz) and 1/ (48kHz), and the random time cycle can be 1/ (8kHz), i.e. 125 μ s.

In order to allow the change asked of the frequency of SCK (n), the worst case frequency of SCK (n) is obtained, such as by corresponding Block 772 output determine.Then the worst case in SCK (n) cycles in this random time cycle is calculated（I.e., most Greatly may）Number.In the embodiment being given above, have the one of 8kHz clocks in the random time cycle of 1/ (8kHz) The individual cycle, and 48kHz clocks six cycles.This number of cycles is multiplied with the in the meter obtained in step 788 in step 790 Numerical value.

The product for obtaining in step 790 is added to an accumulator value in step 792.

Step 784-792 is then repeated for each SCK.Certainly, comparably, step 784-792 can be directed to each SCK is concurrently performed.

The final accumulator value obtained after step 792 is performed for the last time, represented in each random time week The number of the interim operation that may be required.

In step 800, one of selection DCK rates, DCK (m).Then in obtaining the above mentioned cycle at any time The number of cycles of DCK (m), and it is compared with the accumulator value obtained in the last time iteration of step 792.Thus, This number of cycles represents the number of the operation that can be performed in each random time cycle.Therefore determine in step 800, Whether the accumulator value obtained in the last time iteration of step 792 is less than or equal to the DCK (m) in the random time cycle Number of cycles.

If if it is, being chosen this indicates data clock rate DCK (m), it can be less than and utilize completely, and Whether the treatment proceeds to step 802, herein, indicates its acceptable mark（DCK(m)_OK）It is set equal to 1（This Mean that it can be acceptable）, and it is output to clock drive control block 610.

If determining that the accumulator value that is obtained in the last time iteration of step 792 is not less than or not in step 800 Equal to the number in the cycle of DCK (m) in the random time cycle, this indicates, if data clock rate DCK (m) is chosen, It can be more than utilizing completely, and whether the treatment proceeds to step 804, herein, indicates its acceptable mark（DCK (m)_OK）It is set equal to 0（This means it can be unacceptable）, and it is output to clock drive control block 610.

Step 800-806 is then repeated for each DCK rate.Certainly, comparably, step 800-806 can be with each DCK rates are concurrently performed.

When all these DCK rates are all tested with this mode, the treatment proceeds to step 810, then terminates.

Thus, each DCK rate is indicated（That is, in Figure 49：6.144MHz, 12.288MHz, 24.576MHz and 49.152MHz）Whether acceptable corresponding mark is exported to clock drive control block 610 from MUP blocks 608.

Clock drive controller 610 utilizes the output of fallout predictor 608 using MAC, to select suitable DCK clock frequencies.

Figure 50 is returned to, the schedulability of required operation under each possible DCK rate, the before processing is had calculated that Step 728 is entered, whether clock drive control block 610 determines the selector of " being expected to " can all current real herein Border DCK frequencies are scheduled.If it is not, then the treatment proceeds to step 730, herein, during by being sent to this via output 612 " clock selecting being expected to " signal of clock maker, request increases the DCK frequencies.The clock frequency is then in step 732 It is increased.

Once the DCK frequencies have been increased, and find that the selector of " being expected to " can all work as in step 728 Preceding actual DCK frequencies are scheduled, and the treatment just proceeds to step 734.

In step 734, if relatively low DCK frequencies can still allow the selector for owning " being expected to " to be all scheduled, One request is sent to clock generator to reduce the DCK frequencies.

Thus, when less selector is enabled, the blender is run on slower clock, thus advantageously save electricity Power, or when being required to adapt to new selector and becoming the request for enabling, the clock frequency can be increased.

If it is enough that MAC determines current clock frequency using predictor function 608, it will allow " requested " Selector become " activity "；Otherwise, it will stop that any selector becomes to enable.If stopped, this can also be by cutting Take the signal that is sent to the clock generator and be detected, so as to allow the exploitation of the consumer device comprising the routing circuit Person uses the signal as debugging signal.

In step 740, DCK " agreement " signals are sent to latch 758 from clock drive control block 610, to permit Perhaps the selector of " requested " becomes " activity ".If just have sent a request says that the DCK frequencies should be increased, directly It has been increased to the DCK frequencies, the signal is just sent to the latch.

Figure 50 illustrates treatment the step of 742 in, an edge about SCK is detected, and it the step of 744 It is used to control latch 752, to cause that selector " activity " mark becomes " current " mark of selector.

As described above, channel scheduler 620 selects the channel that next calculating will be performed for it.Channel dispatch Device 620 is in Figure 52（a）In be schematically depicted in more detail, Figure 52（b）It is the stream of a part for operation exemplified with channel scheduler 620 Cheng Tu.

The pending attribute block 622 of channel in channel scheduler 620 receives selector " activity " mark from door 756.Channel Pending attribute block 622 also receives all available SCK signals and all of channel-SCK distribution from register banks 602 （channel-SCK allocation）.Then, for each output channel, the pending mark of channel is stored in the non-award of bid of channel In will block 622, to indicate whether pending calculating.

Figure 52（b）Exemplified with the renewal of the pending mark of channel.Each channel is considered separately, although and Figure 52（b）Show Go out them one after the other to be processed, but they equally can concurrently be processed.

In step 892, determine whether the rising edge of corresponding sample rate clock SCK has been detected.If it is, should Treatment proceeds to step 894, and determines whether that channel is movable.If it is, the treatment proceeds to step 896, And the pending mark of the channel is set.

Thus, if a channel is enabled（That is, if having been received by the selection of any selector for that channel Device " activity " indicates）, then in the beginning in each sampling period for being assigned to that specific channel, a pending mark quilt of channel Set, such as relevant sample clock frequency（SCK）Indicate.

For each sampling clock, exist a corresponding SCK Down-counters block 830.1 ..., 830.X.In order to clear Chu, only shows in detail in these SCK Down-counter blocks in Figure 52.Based on being supplied to letter from register banks 602 Channel-SCK the distribution of road scheduler 620, the channel list block in the SCK Down-counter blocks（channel listing block）832 identify the channel with corresponding sample clock frequency.Result is sent to first input of N and door 834. Channel id with the pending traffic sign placement of channel is sent to second input of N and door 834.Thus, each SCK is counted downwards The pending channel associated with that SCK is capable of identify that with door 834 in device block 830, and generates a n output, each Position indicates whether corresponding channel is with corresponding sample clock frequency and with the channel of pending traffic sign placement.

With the multidigit of door 834（multi-bit）Output indication is in corresponding sample rate（SCK）These channels in Which channel has pending calculating.The output of this multidigit is sent to nor gate 835, when in corresponding sample rate（SCK）'s When these channels all do not have pending calculating, the nor gate 835 generation output signal.

Each SCK Down-counters block 830 also contains look-up table（LUT）836, look-up table 836 is containing representing that SCK's The value in cycle, the value was measured in the cycle of most slow available data clock DCK.Down-counter 838 is received for that The pulse of the corresponding SCK signals of individual SCK Down-counters block, and when the rising edge of that SCK signal is detected（Figure Step 870 in 53）, the value from look-up table 836 is loaded into Down-counter 838（Step 872 in Figure 53）.

For each subsequent cycle without the rising edge for detecting that SCK signal, Down-counter 838 is then Counted downwards from that value with the speed of one counting of each cycle of most slow available DCK signals, or if necessary then with this most The speed of the multiple of slow available DCK signals is counted downwards from that value.Thus, Down-counter 838 maintains to be sampled for that The record of the time to exhausted limit of clock SCK.

The output of nor gate 835 and the output of Down-counter 838 are sent to OR gate 837.Thus, when in corresponding Sample rate（SCK）One or more channels when there is pending calculating, Down-counter block 830 by it is corresponding it is current downwards Counter Value（Sck1_ count, sck2_ count ..., sckn_ count）Export comparator 840.When in corresponding sampling Rate（SCK）Channel all without pending calculating when, Down-counter block 830 to comparator 840 export maximum.

Although there has been described the use of Down-counter 838, can also realize in the following manner certainly identical Effect：That is, the cycle of the DCK signals is counted using device block is counted up, the week of corresponding SCK signals is represented until reaching The value of phase, to determine the remaining time to exhausted limit for that sampling clock SCK.

As mentioned above, comparator 840 receives the count value associated from different SCK rates, and it then selects to have The SCK of lowest count value, i.e. to there is most short expeced time at the end of the sampling period in the SCK rates with pending calculating SCK rates.

Thus, channel scheduler 620 selects the sample rate of limit priority first.In this embodiment illustrated, make With " limit is preferential absolutely earliest（earliest deadline first）" dispatching method.That is, the calculating with limit absolutely earliest is first First select to carry out best scheduling, and be that sample rate by being assigned determines for the exhausted limit of the calculating.At other In embodiment, it is possible to use other dispatching methods.

Then, from this group of channel for being assigned to that SCK, one channel of selection is used as next letter waited and calculated Road.

One signal of the output selected sampling clock of identification of comparator 840, and the identification of block 842 is assigned to that The channel of sampling clock.Result is sent to the first input with door 844, and the second input with door 844 at it receives channel not Certainly data.

The pending channel in selected sample rate is thus identified with door 844, and is as a result sent to priority Encoder 846.

Priority encoder 846 selects a channel.Selected channel must be pending and be assigned to selected The sample rate selected, but be in other respects arbitrary selection.In one embodiment, channel is selected with the ascending order of OPADD Select.Selected channel id is notified to the calculating Pipeline controller block 632 calculated in streamline block 630.

Once a channel is received by calculating streamline block 630, the mark being set in the pending attribute block 622 of channel Just it is eliminated, until next sampling period.Thus, at any time, channel scheduler 620 has to current sample period knot The record of calculating being performed is still had to during beam.

Calculate the channel id that Pipeline controller 632 obtains next calculating to be performed from scheduler 620（That is, it is defeated Go out address）, and its then these calculation procedure of iteration, it is as follows so as to provide control signal to other blocks in the streamline What face was more fully described.

Once the first step of the calculating is transfused to the streamline, this is just communicated and returns to the pending attribute block 622 of channel, with Allow that the calculating is marked as successful dispatch.Alternatively, the final step of the calculating has been enter into the streamline The fact can be communicated and return to the pending attribute block 622 of channel.

Figure 54 is exemplified with the form for calculating streamline block 630, and Figure 55 is one exemplified with the calculating streamline block The flow chart of the method for middle execution.

On a new DCK edge（Step 914 in Figure 55）, based on circuit 940 from the preferential of channel scheduler 620 The channel id that level encoder 846 is received（Indicate next channel to be performed）, calculate Pipeline controller block 632 and select One channel（Step 916 in Figure 55）.In 918 the step of Figure 55, Pipeline controller block 632 is calculated pending to the channel Attribute block sending signal（" advancing to next channel " signal in Figure 52）, to remove the non-award of bid of channel for that channel Will.As described above, used as a replacement, the pending mark of the channel can work as calculating and be eliminated when having completed.

Calculate Pipeline controller block 632 and also receive " current " selection from enable and clock control block 604 on circuit 942 Device ID.

In the step for the treatment of in Figure 55 920, calculate Pipeline controller block 632 and value n is set to 1.In step 922 In, calculate Pipeline controller block 632 and obtain the data value for being directed to the n-th selector associated with present channel.Reflected in register Hit, there is permanent association between selector and channel id.Thus, Pipeline controller block 632 is calculated on circuit 944 to posting Storage storehouse 602 sends selector ID, and register banks 602 return to corresponding source ID on circuit 946.It is defeated by enabling the blender Enter bus, the data value in this source ID can be read, and the data value is especially applied to the first of multiplexer 950 Input.

Register banks 602 also return to a corresponding gain on circuit 948 and set（Step 924 in Figure 55）, and it It is applied to coefficient and searches block 952, coefficient searches block 952 and generates corresponding multiplication coefficient.This multiplication coefficient is applied to multiple With the second input of device 950.Thus, in 926 the step of the method for Figure 55, the data value is multiplied by gain coefficient.For One selector（When existing on circuit 958 from the calculating one of Pipeline controller being controlled to accumulator section 954 During signal）, this result is stored in this and multiplies accumulating block（MAC）Accumulator section 954 in（Step 928 in Figure 55）, or For any subsequent selector, the result is added to existing value of the storage in accumulator section 954 to person（Step in Figure 55 930）, the step that the execution output of accumulator section 954 is calculated.

In 932 the step of Figure 55, it is determined whether have any other selector for present channel.If it is, should Treatment proceeds to step 934, and next DCK pulses edge is in waiting herein, and proceeds to step 938, and value n increases herein 1, and step 922-932 repeated.

When determine in step 932 without other selector be used for present channel when（It is next when existing on circuit 962 From the signal of the calculating Pipeline controller when）, then the value representative in accumulator 954 is stored for the calculating of that channel Final result, i.e. one or more input data values（Each is scaled by corresponding yield value）Sum.

Calculate Pipeline controller block 632 and the plan OPADD for being directed to that channel is enabled on output bus 640（It is logical The signal crossed on circuit 964）, to cause that final result is stored in the blender output buffer（That is, with corresponding signal mesh Block association destination）In.

The main users being considered above are the designer or System Programming person of final products or consumer device, but the product The end user of product also can transmit data using the product and by the product.However, easily to the letter by routing circuit Number stream reprogram and makes it possible to allow new final use example, also causes that following situation is feasible, i.e., by having specially Door technical ability terminal user or freely download or Downloadable real-time application software of paying with the help of there is no technical skill Terminal user, new use example can be allowed and/or for the data in one or more functions block.In order to avoid possible Damage（For example, passing through override（over-riding）Loudspeaker Protection path excessively drives（overdriving）Loudspeaker）, There may be and be secured at not modifiable path or gain setting in end product.

When another use example is converted to from a use example, or in enabled or disabled use example, there can be increasing Benefit or the suddenly change in enable/disabling path.In order to reduce the audible artefact during such change（artefact）, the mixing Component can be comprising circuit system by the grade of any change in gain（ramp rate）It is restricted to pre-set or programmable Grade, and may only allow signal zero crossing（zero-crossing）Neighbouring change in gain.

Thus, there is provided following SWITCHING CIRCUITRY, it allows multiple treatment to be located with different sample rates in a mixer Reason, so as to allow audio or comprehensive and very flexible treatment of other signals.

Figure 56 shows electronic equipment 1000, and it may, for example, be industrial equipment, professional equipment or consumer device, and Comprising the on-off circuit 1002 as described above with multiple signal sources and signal destination, and at least one blender, These signal sources and signal destination can be connected to the blender to set up signal path on the basis of time division multiplex.This is opened Powered-down road is implemented as an integrated circuit, and the integrated circuit has the first digital interface 1004.In equipment 1000, the first number Word interface 1004 is coupled to another integrated circuit 1006 by operability, is connect for another integrated circuit to and/or from this Receive and/or provide data signal.Another integrated circuit 1006 wholly or partly includes memory devices, short-distance radio Equipment and/or remote radio equipment.

Figure 57 shows electronic equipment 1010, and it may, for example, be industrial equipment, professional equipment or consumer device, and Comprising the on-off circuit 1012 as described above with multiple signal sources and signal destination, and at least one blender, These signal sources and signal destination can be connected to the blender to set up signal path on the basis of time division multiplex.This is opened Powered-down road is implemented as an integrated circuit, and the integrated circuit has the first digital interface 1014 and the second digital interface 1016. In equipment 1010, the first digital interface 1014 by operability be coupled to first other integrated circuit 1018, for And/or received from this first other integrated circuit and/or data signal is provided.Similarly, the quilt of the second digital interface 1016 Operational is coupled to second other integrated circuit 1020, for being connect to and/or from second other integrated circuit Receive and/or provide data signal.This first other integrated circuit 1018 and this second other integrated circuit 1020 are every It is individual all wholly or partly to include memory devices, short-range wireless device and/or remote radio equipment.

Figure 58 shows electronic equipment 1030, and it may, for example, be industrial equipment, professional equipment or consumer device, and Comprising the on-off circuit 1032 as described above with multiple signal sources and signal destination, and at least one blender, These signal sources and signal destination can be connected to the blender to set up signal path on the basis of time division multiplex.This is opened Powered-down road is implemented as an integrated circuit, and the integrated circuit has the first digital interface 1034, the and of the second digital interface 1036 3rd digital interface 1038.In equipment 1030, the first digital interface 1034 is coupled to first other collection by operability Into circuit 1040, for being received to and/or from this first other integrated circuit and/or providing data signal, the second numeral Interface 1036 is coupled to second other integrated circuit 1042 by operability, for other to and/or from this second Integrated circuit receives and/or provides data signal, and the 3rd digital interface 1038 is coupled to the 3rd in addition by operability Integrated circuit 1044, for being received to and/or from the 3rd other integrated circuit and/or providing data signal.This One other integrated circuit 1040, this second other integrated circuit 1042 and the 3rd other integrated circuit 1044 Each wholly or partly includes memory devices, short-range wireless device and/or remote radio equipment.

Figure 59 shows communication equipment 1060, and it comprising having multiple signal sources and signal destination as described above On-off circuit 1062, and at least one blender, these signal sources and signal destination can on the basis of time division multiplex quilt The blender is connected to set up signal path.The on-off circuit is implemented as an integrated circuit, and the integrated circuit has the One digital interface 1064.In equipment 1060, the first digital interface 1064 is coupled to another integrated circuit by operability 1066, for being received to and/or from another integrated circuit and/or providing data signal.Another integrated circuit 1066 Wholly or partly include it is following in one or more：Application processor, wireless coding and decoding device or communication processor.

Figure 60 shows communication equipment 1070, and it comprising having multiple signal sources and signal destination as described above On-off circuit 1072, and at least one blender, these signal sources and signal destination can on the basis of time division multiplex quilt The blender is connected to set up signal path.The on-off circuit is implemented as an integrated circuit, and the integrated circuit has the One digital interface 1074 and the second digital interface 1076.In equipment 1070, the first digital interface 1074 is by the coupling of operability To first other integrated circuit 1078, for being received to and/or from this first other integrated circuit and/or providing number Word signal.Similarly, the second digital interface 1076 by operability be coupled to second other integrated circuit 1080, for And/or received from this second other integrated circuit and/or data signal is provided.This first other integrated circuit 1078 Each of integrated circuit 1080 other with this second wholly or partly include it is following in one or more：Using place Reason device, wireless coding and decoding device or communication processor.

Figure 61 shows communication equipment 1090, and it comprising having multiple signal sources and signal destination as described above On-off circuit 1092, and at least one blender, these signal sources and signal destination can on the basis of time division multiplex quilt The blender is connected to set up signal path.The on-off circuit is implemented as an integrated circuit, and the integrated circuit has the One digital interface 1094, the second digital interface 1096 and the 3rd digital interface 1098.In equipment 1090, the first digital interface 1094 are coupled to first other integrated circuit 1100 by operability, for other integrated to and/or from this first Circuit receives and/or provides data signal, and the second digital interface 1096 is coupled to second other integrated electricity by operability Road 1102, for being received to and/or from this second other integrated circuit and/or providing data signal, and the 3rd numeral Interface 1098 is coupled to the 3rd other integrated circuit 1104 by operability, for other to and/or from the 3rd Integrated circuit receives and/or provides data signal.This first other integrated circuit 1100, this second other integrated electricity Each of road 1102 and the 3rd other integrated circuit 1104 wholly or partly include it is following in one or more： Application processor, wireless coding and decoding device or communication processor.

In this disclosure, it should be appreciated that exemplified with various parts.When such part is shown and described When, it should be noted that it can be replaced by the multiple parts for providing identical general function, and similarly, when for the side of illustration When function just being shown as into distribution between different masses, this function can also be provided in single part.

" scaling " of signal described herein, it can refer to the value for increasing or decreasing such signal（magnitude） Or value（value）, and be not excluded for these signals and can be retained constant possibility.

It should be apparent that, although in order to clearly and in order to understand that easily some elements of the disclosure have been combined Describe, but these elements can be used independently of each other, and shown or described feature can be by discretely or to appoint What is applied in combination.

Present disclosure relates in general to may be implemented as the circuit of integrated circuit, although the different aspect of the circuit can be with Implemented with hardware, firmware, software or any combination of them.For example, the present invention can above be carried with computer readable carrier The hardware description language of confession is implemented.

Although having shown that and describing specific embodiments of the present invention, it should be apparent that, do not departing from the scope of the present invention On the premise of, many changes can be made.

Claims (33)

1. a kind of integrated circuit, including digital mixed nucleus, the digital mixed nucleus can be configured to the multiple audio data samples for the treatment of Downward sample streams, and the digital mixed nucleus includes：

Multiple digital signal processing blocks, wherein each in the digital signal processing block includes a source port and a destination Port, each in the digital signal processing block can be configured to：

Downward sampled audio data sample flow is received in the destination port,

The downward sampled audio data stream that treatment is received, and

Processed downward sampled audio data stream is sent from the source port；

Programmable storage circuits system, can be configured to the multiple set of configuration data of storage, wherein in the multiple set of configuration data Each respectively defines at least two source ports and defines a destination port；And

Hybrid component, can be configured to：

The multiple subsequent signal paths corresponding to currently stored multiple set of configuration data are set up, and

In each signal path, the corresponding downward sampled audio number from least two source ports being defined is combined According to the data of sample flow, to provide the downward sampled data stream of combination, and

According to the corresponding set of configuration data in the multiple set of configuration data, sent out to the destination port being defined Send the downward sampled data stream of the combination；

Wherein, the integrated circuit also includes：

Downward sampling circuitry, with multiple input terminals and multiple lead-out terminals, the input terminal is used to receive sound Frequency data sample stream, the lead-out terminal is coupled to the digital mixed nucleus with will downward sampled audio data sample accordingly Stream is exported to the digital mixed nucleus；

Upward sampling circuitry, with multiple input terminals and multiple lead-out terminals, the input terminal is coupled to institute Digital mixed nucleus is stated to receive corresponding sampled audio data sample flow downwards, the lead-out terminal is coupled to corresponding addition Device is exporting corresponding sampled audio data sample upwards；And

Low latency process block for processing audio data sample, including：

At least one input terminal, is coupled to corresponding at least one input terminal of the downward sampling circuitry, uses In at least one of described audio data sample stream of reception；And

One lead-out terminal, is coupled at least one of described adder, for the audio data sample through processing to be added To corresponding sampled audio data sample upwards.

2. integrated circuit according to claim 1, also including at least one input interface, wherein the input interface or each Input interface includes a source port.

3. integrated circuit according to claim 1 and 2, also including at least one output interface, wherein the output interface or Each output interface includes a destination port.

4. integrated circuit according to claim 1 and 2, wherein programmable storage circuits system may be additionally configured to storage More than two set of configuration data, wherein each set of configuration data in more than second set of configuration data defines a source Mouthful and define a destination port, and

Wherein the hybrid component can be configured to more than second subsequent signal set up corresponding to more than second set of configuration data Path, and

In each signal path in more than second signal path, the data from one source port are multiplied by one Zoom factor, to provide the data flow for having scaled, and matches somebody with somebody according to corresponding in more than second set of configuration data Data group is put, the data flow for having scaled is sent to the destination port being defined.

5. integrated circuit according to claim 1 and 2, wherein programmable storage circuits system may be additionally configured to storage More than three set of configuration data, wherein each set of configuration data in the 3rd many set of configuration data defines a source Mouthful and define a destination port, and

Wherein the hybrid component can be configured to the 3rd many subsequent signals set up and correspond to the described 3rd many set of configuration data Path, and

In each signal path in the 3rd many signal paths, data are extracted from one source port, to provide Bypass data stream, and according to the corresponding set of configuration data in the 3rd many set of configuration data, by the bypass Data flow is sent to the destination port being defined.

6. integrated circuit according to claim 1 and 2, wherein hybrid component can be configured on the basis of time division multiplex Dispatch each in the subsequent signal path therethrough.

7. integrated circuit according to claim 1 and 2, wherein each configuration data in the multiple set of configuration data Group defines a corresponding sample rate.

8. integrated circuit according to claim 7, wherein being independently programmable for the sample rate of each signal path 's.

9. integrated circuit according to claim 1 and 2, wherein programmable storage circuits system can be configured in single position The following data of storage are put, the data define the sampling for all purposes ground port at least one digital signal processing block Rate.

10. integrated circuit according to claim 7, wherein programmable storage circuits system is configurable to store following number According to the data indicate an available sampling clock for predetermined number.

11. integrated circuits according to claim 1 and 2, wherein at least one of the multiple set of configuration data is configured Data group defines a corresponding zoom factor, and the corresponding zoom factor is waited to be applied to the phase from corresponding signal path The data of at least one source port answered.

12. integrated circuits according to claim 11, including limiter, the limiter are used for any of the zoom factor The grade of change is restricted to the scheduled rate of maximum or the programmable speed of maximum.

13. integrated circuits according to claim 11, including controller, the controller are used for only when from corresponding source The data of mouth just allow the zoom factor to change when having null value.

14. integrated circuits according to claim 1 and 2, including for receiving the control input of the set of configuration data.

15. integrated circuits according to claim 4, when claim 4 is subordinated to claim 2, wherein at least one Set of configuration data defines signal path between input interface and output interface.

16. integrated circuits according to claim 5, when claim 5 is subordinated to claim 2, wherein at least one Set of configuration data defines signal path between input interface and output interface.

Signal between 17. integrated circuit according to claim 15 or 16, the wherein input interface and the output interface Data on path do not change.

18. integrated circuits according to claim 1, wherein the low latency process block include digital filter.

19. integrated circuits according to claim 18, the wherein digital filter are self adaptations.

20. integrated circuits according to claim 1, wherein the low latency process block can be configured to used in feed-forward noise In elimination.

21. integrated circuits according to claim 1, the wherein sample rate of the low latency process block are far above described more The sample rate of individual digital signal processing block.

22. integrated circuits according to claim 1, wherein the low latency process block are connected and mix with from the numeral At least one of the multiple digital signal processing block of core signal processing blocks receive control signal.

23. integrated circuits according to claim 1 and 2, with the first digital interface, for from first other integrated circuits Data signal is received, and with the second digital interface, for receiving data signal from second other integrated circuits.

24. integrated circuits according to claim 23, also with the 3rd digital interface, for from the 3rd other integrated circuits Receive data signal.

25. a kind of electronic equipment, including the integrated circuit according to any claim in claim 1 to 24, also include： Storage device for storing multiple multiple set of configuration data of the special-purpose of the suitable electronic equipment；And for according to finger The data of the desired purposes of the electronic equipment are shown and suitable multiple set of configuration data have been loaded into the programmable storage Device in circuit system.

26. electronic equipments according to claim 25, wherein indicate the data of the desired purposes of the electronic equipment being What the software from the electronic equipment is embedded in was supplied.

27. electronic equipments according to claim 25, wherein indicate the data of the desired purposes of the electronic equipment being Supplied in response to the service condition of the electronic equipment.

28. electronic equipments according to claim 27, the wherein service condition include the input of the user of the electronic equipment.

29. electronic equipment according to any claim in claim 25 to 28, the wherein storage device include deposit Device.

30. electronic equipment according to any claim in claim 25 to 28, the wherein storage device include non-easy The property lost memory.

31. electronic equipment according to any claim in claim 25 to 28, including graphical user interface, the figure The figure that user interface is configured as the element that the integrated circuit is presented to user is represented, and reception defines signal path User input, and accordingly generate suitable set of configuration data.

A kind of 32. portable communication devices, including the integrated circuit according to claim 23 or 24, including be connected to this first The application processor of digital interface, and it is connected to the communication processor of second digital interface.

A kind of 33. portable communication devices, including integrated circuit according to claim 24, including it is connected to first numeral The application processor of interface, is connected to the communication processor of second digital interface, and be connected to the 3rd digital interface Wireless transceiver.