CN113629126A - Array substrate, manufacturing method thereof and display panel - Google Patents
Array substrate, manufacturing method thereof and display panel Download PDFInfo
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- CN113629126A CN113629126A CN202111190041.8A CN202111190041A CN113629126A CN 113629126 A CN113629126 A CN 113629126A CN 202111190041 A CN202111190041 A CN 202111190041A CN 113629126 A CN113629126 A CN 113629126A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
Abstract
The application discloses an array substrate, a manufacturing method of the array substrate and a display panel. The array substrate is divided into a light-transmitting area and a non-light-transmitting area; the array substrate comprises a substrate and a thin film transistor layer, wherein the thin film transistor layer is arranged on the substrate; the thin film transistor layer comprises a thin film transistor part corresponding to the non-light-transmitting area and a color resistance part corresponding to the light-transmitting area; the color resistance part is directly arranged on the substrate; or the color resistance part and the substrate are provided with inorganic film layers or organic film layers, and the total number of the inorganic film layers or the organic film layers is less than or equal to 1. The array substrate of the technical scheme can reduce the phenomenon of optical waveguide and improve the brightness and the light output of back light emission.
Description
Technical Field
The application relates to the technical field of display panels, in particular to an array substrate, a manufacturing method of the array substrate and a display panel.
Background
Organic Light-Emitting displays (OLEDs), also known as Organic Light-Emitting Semiconductors (OLEDs), have been widely used due to their advantages of low power consumption, fast response speed, and wide viewing angle. When the OLED display panel is back-emitting, light emitted from the light-emitting layer releases light to the array substrate (TFT side), and the light forms a picture on the substrate after penetrating through the array substrate. The thin film transistor on the array substrate is opaque, light can only be released from the light-transmitting window, and the penetrating efficiency of the light-transmitting area directly influences the brightness of the light.
In the existing array substrate structure, multiple inorganic film layers exist between the sub-color resistors and the substrate, because the refractive indexes between the inorganic film layers are different, a waveguide effect can occur between the multiple inorganic film layers, and light originally emitted from the back of the array substrate can be released to the edge position, so that the back light-emitting brightness is reduced.
Disclosure of Invention
The main purpose of the present application is to provide an array substrate, which aims to solve the problem of low luminance of a back-illuminated OLED display panel.
In order to achieve the above purpose, the array substrate provided by the present application is divided into a light-transmitting region and a non-light-transmitting region; the array substrate comprises a substrate and a thin film transistor layer, wherein the thin film transistor layer is arranged on the substrate; the thin film transistor layer comprises a thin film transistor part corresponding to the non-light-transmitting area and a color resistance part corresponding to the light-transmitting area; the color resistance part is directly arranged on the substrate;
or the color resistance part and the substrate are provided with inorganic film layers or organic film layers, and the total number of the inorganic film layers or the organic film layers is equal to 1.
In an embodiment of this application, the basement with be equipped with light shield layer and first buffer layer between the thin film transistor layer, the light shield layer is located the basement corresponds in the position of thin film transistor portion, first buffer layer is located the light shield layer with on the basement, the colour hinders the portion and locates first buffer layer.
In an embodiment of the present application, a second buffer layer is further disposed between the thin film transistor portion and the first buffer layer.
In an embodiment of the present application, when the color resistance portion is directly disposed on the substrate, a light shielding layer, a first buffer layer, and a second buffer layer are sequentially disposed between the thin film transistor portion and the substrate.
In an embodiment of the present application, the thin film transistor portion includes an active layer, a gate insulating layer, a gate electrode, an organic insulating layer, and a source electrode and a drain electrode disposed on the organic insulating layer and spaced apart from each other; and the source electrode and the drain electrode are respectively connected with the active layer through the via hole of the organic insulating layer.
In an embodiment of the present application, the refractive index of the first buffer layer ranges from 1.0 to 1.2.
In an embodiment of the present application, the color resistance portion is composed of a red color resistance unit, a green color resistance unit, and a blue color resistance unit;
alternatively, the color resistance portion is composed of a red color resistance unit, a green color resistance unit, a blue color resistance unit, and a white color resistance unit.
The application also provides a manufacturing method of the array substrate, which comprises the following steps:
providing a substrate, and forming a light shielding layer on the substrate;
forming a buffer layer on the light-shielding layer;
forming a plurality of thin film transistors on the buffer layer at positions corresponding to the light shielding layer;
forming a plurality of color resistance units arranged at intervals on the substrate or the buffer layer, wherein the thin film transistor is positioned between two adjacent color resistance units;
and forming a flat layer and a pixel electrode layer on the color resistance unit and the thin film transistor.
In an embodiment of the application, when a plurality of color-resisting units are formed on the substrate, the step of forming a plurality of color-resisting units arranged at intervals on the substrate or the buffer layer includes:
etching the buffer layer, and etching off the buffer layers on two sides of the thin film transistor;
and directly forming a plurality of color resistance units on the substrate.
The application also provides a display panel, including array substrate, OLED luminescent layer and packaging part, the OLED luminescent layer is located on the array substrate, the packaging part is located on the OLED luminescent layer, array substrate adopts as above-mentioned arbitrary array substrate.
In the technical scheme of the application, the array substrate comprises a substrate and a thin film transistor layer, the thin film transistor layer comprises a thin film transistor part corresponding to a non-light-transmitting area and a color resistance part corresponding to a light-transmitting area, and light rays penetrate through the color resistance part, the substrate and a film layer between the color resistance part and the substrate and then are emitted out in an opening area, so that the total number of organic or inorganic film layers arranged between the color resistance part and the substrate is 1 or the color resistance part is directly arranged on the substrate, namely, between the color resistance part and the substrate, the interface of the inorganic film layer or the interface of the inorganic film layer and the organic film layer is less than three, the number of the inorganic film layers or the organic film layers with different refractive indexes is reduced, the thickness of the film layers is correspondingly reduced, the probability of optical waveguide phenomenon between the film layer interfaces is reduced, the low light emitting efficiency caused by multiple refractions of light is avoided, and the loss of light emitted from the edge of the substrate is also avoided, thereby effectively improving the light output quantity and the brightness and the light output efficiency of the back face luminescence. Certainly, the light emitting efficiency is improved, and meanwhile, the power consumption of the display panel can be reduced, so that the energy is effectively saved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a cross-sectional view of a first embodiment of an array substrate according to the present application;
FIG. 2 is a cross-sectional view of a second embodiment of an array substrate of the present application;
FIG. 3 is a cross-sectional view of a third embodiment of an array substrate of the present application;
FIG. 4 is a flowchart illustrating a method of fabricating an array substrate according to an embodiment of the present disclosure;
fig. 5 is a cross-sectional view corresponding to step S1 in the method for manufacturing the array substrate shown in fig. 4;
fig. 6 is a cross-sectional view corresponding to step S2 in the method for manufacturing the array substrate shown in fig. 4;
fig. 7 is a cross-sectional view corresponding to step S3 in the method for manufacturing the array substrate shown in fig. 4;
fig. 8 is a cross-sectional view corresponding to step S4 in the method for manufacturing the array substrate shown in fig. 4;
fig. 9 is a cross-sectional view corresponding to step S5 in the method for manufacturing the array substrate shown in fig. 4;
FIG. 10 is a cross-sectional view of an embodiment of a display panel according to the present application.
The reference numbers illustrate:
100: a display panel;
10: an array substrate; 11: a light-shielding layer; 12: a buffer layer; 121: a first buffer layer; 122: a second buffer layer; 13: a thin film transistor; 131: a gate electrode; 132: a source electrode; 133: a drain electrode; 134: an active layer; 14: a gate insulating layer; 15: a passivation layer; 16: an organic insulating layer; 17: a pixel electrode layer; 18: a planarization layer; 19: a color resist portion; 191: a color resistance unit;
20: an OLED light emitting layer; 21: a light emitting layer; 22: a cathode layer; 23: a packaging layer;
30: a substrate; 40: a pixel defining layer; 50: and (7) packaging the components.
The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that if directional indications (such as up, down, left, right, front, and back … …) are referred to in the embodiments of the present application, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present application, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
The application provides an array substrate, a manufacturing method thereof and a display panel, wherein the display panel is back-side light-emitting and comprises the array substrate and an OLED light-emitting layer which are sequentially arranged, light emitted by the OLED light-emitting layer is emitted to the array substrate and penetrates through a color resistance part on the array substrate to display a color picture. The number of layers of the organic film layer or the inorganic film layer between the color resistance part and the substrate is reduced, so that the phenomenon that the optical waveguide is generated on the interface of the organic film layer or the inorganic film layer due to different refractive indexes is reduced, and the luminous brightness and the emergent efficiency of the display panel are improved.
Referring to fig. 1 to 3, in the first embodiment of the present application, the array substrate 10 is divided into a transparent region and a non-transparent region; the array substrate 10 comprises a substrate 30 and a thin film transistor layer, wherein the thin film transistor layer is arranged on the substrate 30; the thin film transistor layer comprises a thin film transistor part corresponding to the non-light-transmitting area and a color resistance part 19 corresponding to the light-transmitting area; the color resistance part 19 is directly arranged on the substrate 30;
or, an inorganic film layer or an organic film layer is disposed between the color resist portion 19 and the substrate 30, and the total number of the inorganic film layer or the organic film layer is equal to 1.
In this embodiment, the display panel 100 applied to the array substrate 10 is an organic self-emitting display (OLED), and is a back-light emitting structure, and includes a substrate 30, the array substrate 10, and an OLED light emitting layer 20 stacked in sequence, and light emitted from the OLED light emitting layer 20 is emitted toward the array substrate 10.
Specifically, the substrate 30 provides support for the thin film transistor layer, and the light emitted from the light-transmitting region also passes through the substrate 30, so that the substrate 30 needs to be made of a transparent material, such as glass, while providing support, so as to reduce the light loss and improve the light output. Of course, when the substrate 30 made of a flexible material is required, the material of the substrate 30 may be selected from plastic and the like. The color resistance part 19 includes a plurality of color resistance units 191, the thin film transistor part includes a plurality of thin film transistors 13, and one thin film transistor 13 is interposed between every two adjacent color resistance units 191.
It can be understood that the thin film transistor portion includes an active layer 134, a gate insulating layer 14, a gate electrode 131, an organic insulating layer 16 stacked in sequence, and further includes a source electrode 132 and a drain electrode 133 disposed on the organic insulating layer 16 and spaced apart from each other, and the source electrode 132 and the drain electrode 133 are connected to the active layer 134 through a via hole of the organic insulating layer 16, respectively. The thin film transistor 13, i.e. the control switch, is respectively disposed in each pixel for controlling the switch of each pixel. The thin film transistor 13 includes an active layer 134, a gate electrode 131, a source electrode 132, and a drain electrode 133 disposed from bottom to top, the active layer 134 is formed on the substrate 30, and the active layer 134 is doped to form a source electrode 132 region and a drain electrode 133 region; a gate insulating layer 14 is formed between the active layer 134 and the gate electrode 131 to space and insulate the two; depositing a metal layer on the gate insulating layer 14, and patterning the metal layer to form a gate 131; similarly, in order to isolate the metal layer, the organic insulating layer 16 is formed on the gate electrode 131, and the organic insulating layer 16 covers part of the gate insulating layer 14 and the active layer 134; a metal layer is deposited on the organic insulating layer 16, and source and drain electrodes 132 and 133 are formed by patterning the metal layer to be spaced apart, and the source electrode 132 is connected to the source electrode 132 region through a via hole opened in the organic insulating layer 16, and the drain electrode 133 is also connected to the drain electrode 133 region through a via hole opened in the organic insulating layer 16, and a channel region is formed between the source electrode 132 and the drain electrode 133. The material of the metal layer is an opaque conductive metal material, such as one or a combination of molybdenum, titanium, chromium, and aluminum, which is not limited herein. The material of the gate insulating layer 14 may be one or a combination of silicon oxide and silicon nitride.
At the same time, a scan line is formed together with the gate electrode 131, and the scan line is connected to the gate electrode 131 to supply a voltage for turning on and off the thin film transistor 13. When no voltage is applied to the gate electrode 131, the thin film transistor 13 is turned off; after applying a voltage to the gate electrode 131, an electron accumulation may be formed in the active layer 134 of a semiconductor property, thereby applying a voltage to the source electrode 132 and the drain electrode 133 so that the channel region is approximated to an on-resistance, and thus the thin film transistor 13 is in an on-state. After the thin film transistor 13 is formed, a passivation layer 15 is further deposited on the source electrode 132, the drain electrode 133 and the organic insulating layer 16, and the passivation layer 15 is patterned by a photolithography process, where the material of the passivation layer 15 may be one or more of silicon oxide and silicon nitride, so as to protect the thin film transistor 13.
Here, the organic insulating layer 16 is an organic film layer, the passivation layer 15 and the gate insulating layer 14 are both inorganic film layers, refractive indexes of every two inorganic film layers are different, refractive indexes of the organic film layer and the inorganic film layer are also different, and the refractive indexes of the organic film layer and the inorganic film layer are larger than that of air. The color resistance unit 191 is directly arranged on the substrate 30, or an organic film layer or an inorganic film layer is arranged between the color resistance unit 191 and the substrate 30, so that at most two interfaces need to pass through after light passes through the color resistance unit 191, and the number and the thickness of the organic film layer or the inorganic film layer which needs to pass through are effectively reduced.
In the technical scheme of the application, the array substrate 10 includes a substrate 30 and a thin film transistor layer, the thin film transistor layer includes a thin film transistor portion corresponding to a non-light-transmitting region and a color resistance portion 19 corresponding to a light-transmitting region, in an opening region (i.e., a light-transmitting region), light can pass through the color resistance portion 19, the substrate 30 and a film layer between the color resistance portion 19 and the substrate 30 and then be emitted, so that the total number of organic or inorganic film layers arranged between the color resistance portion 19 and the substrate 30 is set to be 1, or the color resistance portion 19 is directly arranged on the substrate 30, that is, between the color resistance portion 19 and the substrate 30, the interface of the inorganic film layer or the interface of the inorganic film layer and the organic film layer is set to be less than three, the number of the inorganic film layers or the organic film layers with different refractive indexes is reduced, and correspondingly the film layer thickness is also reduced, thereby reducing the probability of occurrence of optical waveguide phenomenon between the film layer interfaces, and avoiding low light efficiency caused by multiple refractions, and the loss of light output quantity caused by the release of the emergent light from the edge of the substrate 30 is avoided, so that the light output quantity is effectively improved, and the brightness and the emergent efficiency of back light emission are improved. Of course, the light extraction efficiency is improved, and meanwhile, the power consumption of the display panel 100 can be reduced, so that the energy is effectively saved. Compared with the products of the same grade, the competitiveness of the display panel 100 can be effectively ensured.
First embodiment
In an embodiment of the present application, a light shielding layer 11 and a first buffer layer 121 are disposed between the substrate 30 and the thin film transistor layer, the light shielding layer 11 is disposed on the substrate 30 corresponding to the position of the thin film transistor portion, the first buffer layer 121 is disposed on the light shielding layer 11 and the substrate 10, and the color resistor 19 is disposed on the first buffer layer 121.
It is understood that, in order to improve the display effect, a light shielding layer 11 is further deposited on the substrate 30, and the light shielding layer 11 corresponds to the position of the thin film transistor 13; and in an orthographic projection on the substrate 30, the light-shielding layer 11 covers the thin film transistor 13. In order to isolate the light-shielding layer 11 from the active layer 134, a first buffer layer 121 is further disposed between the light-shielding layer 11 and the active layer 134, the first buffer layer 121 completely covers the light-shielding layer 11 and the substrate 30, and the first buffer layer 121 can also play a role in buffering when the display screen is impacted by extrusion or falling and the like, so that the breaking phenomenon is reduced, and the first buffer layer is also an inorganic film layer.
Here, an inorganic film layer is disposed between the substrate 30 and the color resistance unit 191, and the inorganic film layer is a first buffer layer 121, on one hand, the first buffer layer 121 is located at the outermost layer of the array substrate 10 relative to other organic or inorganic film layers, so as to facilitate processing; on the other hand, because of having a certain buffering effect, when the color resistance unit 191 and the thin film transistor 13 are both disposed on the first buffer layer 121, the structural stability of the display panel 100 can be effectively improved, the usability thereof can be ensured, the number and thickness of the film layers through which light passes can be reduced, and the optical waveguide effect can be reduced.
Of course, in other embodiments, an inorganic film layer may be disposed as the gate insulating layer 14 or the passivation layer 15.
On the basis that only one first buffer layer 121 is arranged between the substrate 30 and the color resistance unit 191, in order to further improve the light emitting efficiency and the light emitting amount, the refractive index range of the first buffer layer is set to be 1.0-1.2. Here, the refractive index of the first buffer layer is set to be close to 1, that is, substantially the same as the refractive index of air, for example, 1.0, 1.1, 1.2, and the like, so that the number of times and probability of refraction of the emergent light are further reduced, and the efficiency and brightness of the emergent light from the back surface are improved.
Second embodiment
Referring to fig. 2, a second buffer layer 122 is further disposed between the thin film transistor portion and the first buffer layer 121.
It is understood that, in order to achieve different effects, two buffer layers may be provided, that is, the second buffer layer 122 is further provided on the first buffer layer 121, and the material and the processing manner of the two buffer layers may be different, that is, the refractive indexes of the two buffer layers are also different, for example, the first buffer layer 121 is provided on the substrate 30, and can play a certain role in preventing water vapor. In this embodiment, in order to reduce the optical waveguide effect, when the buffer layers are provided with two layers, the color resistance unit 191 is disposed on the first buffer layer 121 closest to the substrate 30, and the second buffer layer 122 is disposed only between the thin film transistor portion and the first buffer layer 121, and is not disposed between the color resistance unit 191 and the substrate 30, so as to reduce the number of film interfaces through which the emergent light passes, that is, reduce the number of interfaces generating a refractive index difference, ensure the probability and the amount of the emergent light emitted from the front surface, and improve the front display brightness.
Third embodiment
Referring to fig. 3, when the color resist 19 is directly disposed on the substrate 30, a light-shielding layer 11, a first buffer layer 121 and a second buffer layer 122 are sequentially disposed between the thin film transistor portion and the substrate 30.
In this embodiment, when the number of the film layers sandwiched between the color resist 19 and the substrate 30 is 0, that is, the two film layers are in direct contact with each other, the number of interfaces on which the refractive index difference occurs in the outgoing light is minimized, so that the brightness and the light output amount of the front outgoing light can be improved to the maximum extent. Of course, in order to ensure the structural stability of the display panel 100, the first buffer layer 121 and the second buffer layer 122 are disposed between the thin film transistor 13 and the substrate 30, so as to achieve different isolation buffer effects. Of course, in other embodiments, the buffer layer may be a single layer.
On the basis of any one of the three embodiments, the array substrate 10 further includes a flat layer 18 and a pixel electrode layer 17, the flat layer 18 covers the color resistor 19 and the thin film transistor 13, and the pixel electrode layer 17 is disposed on the flat layer 18 and electrically connected to the thin film transistor 13 through the flat layer 18.
Here, the array substrate 10 further includes a planarization layer 18, and the planarization layer 18 covers the surfaces of the photo tft 13 and the color resistor 19, so that the structures of the color resistor 19 and the tft 13 can be protected, and the structural planarization and the sealing property can be improved. Specifically, when the passivation layer 15 is disposed on the surface of the thin film transistor 13, the planarization layer 18 covers the color resistor 19 and the passivation layer 15, and the planarization layer 18 can be processed by filling using a mold, thereby improving the processing efficiency. Of course, the flat layer 18 is required to be a light-transmitting material to ensure that light is emitted to the color resist 19 therethrough.
In order to realize the light emission of the OLED display panel 100, a pixel electrode is disposed in each pixel region, a plurality of pixel electrodes form a pixel electrode layer 17, the pixel electrode layer 17 is disposed on the flat layer 18, through holes are correspondingly formed on the flat layer 18 and the passivation layer 15, the through holes can expose a portion of the drain electrode 133, and the pixel electrode layer 17 electrically contacts the drain electrode 133 through the through holes, thereby serving as an anode and cooperating with the cathode layer 22 of the OLED light emitting layer 20 to generate light emission of light emitting molecules. The material of the pixel electrode may be Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), and the like, which is not limited herein. Here, the OLED light emitting layer 20 is disposed on the pixel electrode layer 17, and after it emits light, it only needs to pass through the flat layer 18 to enter the color resistance unit 191, so that, optionally, the flat layer 18 is set to have a high light transmittance of 95%, thereby effectively reducing the light loss, and further improving the light utilization rate and the light output amount.
In an embodiment of the present application, the color resistance part 19 is composed of a red color resistance unit 191, a green color resistance unit 191, and a blue color resistance unit 191;
alternatively, the color resist 19 includes red color resist cells 191, green color resist cells 191, blue color resist cells 191, and white color resist cells 191.
In this embodiment, in order to realize a color image, the color resist section 19 needs to set three primary colors so as to form a color image with sharp contrast in cooperation with the emitted white light. In one embodiment, the color resistance part 19 is composed of a red color resistance unit 191, a green color resistance unit 191 and a blue color resistance unit 191, and the three color resistance units 191 are sequentially arranged and repeatedly arranged by taking the three color resistance units 191 as units.
In another embodiment, the color resistance part 19 may also be composed of a red color resistance unit 191, a green color resistance unit 191, a blue color resistance unit 191 and a white color resistance unit 191, and the four color resistance units 191 are sequentially arranged and repeatedly arranged by taking four as a unit, and can also realize a better color image by matching with the white light emitting layer 21.
Referring to fig. 4 to 9, the present application further provides a manufacturing method of an array substrate, where fig. 4 is a schematic flow chart of the manufacturing method of the array substrate, and the manufacturing method of the array substrate 10 includes the following steps:
step S1: providing a substrate 30, and forming a light shielding layer 11 on the substrate 30;
step S2: forming a buffer layer 12 on the light-shielding layer 11;
step S3: forming a plurality of thin film transistors 13 on the buffer layer 12 at positions corresponding to the light-shielding layer 11;
step S4: forming a plurality of color resistance units 191 arranged at intervals on the substrate 30 or the buffer layer 12, wherein the thin film transistor 13 is positioned between the two color resistance units 191;
step S5: a planarization layer 18 and a pixel electrode layer 17 are formed on the color resistance unit 191 and the thin film transistor 13.
Referring to fig. 5, in step S1, in order to support the array substrate 10, a substrate 30 is prepared, wherein the substrate 30 may be made of glass, smooth and pollution-free, and in the case of the flexible display panel 100, a material such as plastic may be selected. Then, a plurality of light shielding layers 11 are formed on the substrate 30, specifically, a metal film is deposited on the substrate 30, and then the light shielding layers 11 are formed by patterning, at this time, the bottom of the light shielding layers 11 is attached to the substrate 30, and the substrate 30 plays a supporting role.
Referring to fig. 6 again, in step S2, the buffer layer 12 is formed on the substrate 30 such that the buffer layer 12 at least covers the light-shielding layer 11. Here, the buffer layer 12 may be configured as a layer or a stacked two-layered structure according to actual requirements.
Referring to fig. 7 again, in step S3, a thin film transistor portion is fabricated, and the active layer 134, the gate electrode 131, the source electrode 132, and the drain electrode 133 of the thin film transistor 13 are deposited layer by layer corresponding to the light-shielding layer 11. Specifically, the active layer 134 is formed on the buffer layer 12, and the active layer 134 is doped to form the source electrode 132 region and the drain electrode 133 region; depositing a gate insulating layer 14 on the active layer 134, depositing a metal layer on the gate insulating layer 14, and patterning the metal layer to form a gate 131; similarly, in order to isolate the metal layer, the organic insulating layer 16 is formed on the gate electrode 131, and the organic insulating layer 16 covers part of the gate insulating layer 14 and the active layer 134; a metal layer is deposited on the organic insulating layer 16, and source and drain electrodes 132 and 133 are formed by patterning the metal layer to be spaced apart, and the source electrode 132 is connected to the source electrode 132 region through a via hole opened in the organic insulating layer 16, and the drain electrode 133 is also connected to the drain electrode 133 region through a via hole opened in the organic insulating layer 16, and a channel region is formed between the source electrode 132 and the drain electrode 133.
Referring to fig. 8 again, in step S4, in an embodiment, the color-resisting units 191 need to be deposited on the buffer layer 12, the gate insulating layer 14 and the organic insulating layer 16 originally extending to the color-resisting units 191 should be etched and removed, and then a plurality of spaced color-resisting units 191 are formed on the buffer layer 12, and the color-resisting portions 19 are formed by the plurality of color-resisting units 191. Here, when the color resist units 191 are formed on the buffer layer 12, the buffer layer 12 of step S2 is laid on the substrate 30, and the color resist units 191 may be directly deposited on the buffer layer 12. In another embodiment, the buffer layer 12 is not disposed where the color resistance unit 191 needs to be deposited, and the color resistance unit 191 is directly deposited on the substrate 30.
Referring to fig. 9 again, in step S5, a planarization layer 18 is formed on the color resists 19 and the tfts 13. Specifically, when the passivation layer 15 is disposed on the surface of the thin film transistor 13, the planarization layer 18 covers the color resistor 19 and the passivation layer 15, and the planarization layer 18 can be processed by filling using a mold, thereby improving the processing efficiency. Of course, the flat layer 18 is required to be a light-transmitting material to ensure that light is emitted to the color resist 19 therethrough. The planarization layer 18 covers the surfaces of the photo tft 13 and the color resistor 19, thereby protecting the structures of the color resistor 19 and the tft 13, improving the structural flatness and sealing performance, and providing a good supporting effect for the pixel electrode layer 17 disposed thereon, and preventing the pixel electrode layer from being broken. The pixel electrode layer 17 is fabricated by depositing a metal layer on the planarization layer 18 and then patterning the metal layer to form the pixel electrode layer 17 in a desired shape. A plurality of pixel electrodes in the pixel electrode layer 17 are electrically connected to the plurality of drain electrodes 133 through the planarization layer 18 and the passivation layer 15, respectively, thereby enabling input of voltages and signals.
In an embodiment, when a plurality of the color-resisting units 191 are formed on the substrate 30, the step of forming a plurality of color-resisting units 19 spaced apart on the substrate 30 or the buffer layer 12 includes:
etching the buffer layer 12 to etch away the buffer layers on the two sides of the thin film transistor 13, that is, etching away the portion of the buffer layer 12 where the thin film transistor 13 is not disposed;
a plurality of the color resistance units 191 are directly formed on the substrate 30.
Here, when forming the color resistance units 191 on the substrate 30, first, a buffer layer 12 is uniformly laid, and the buffer layer 12 of step S2 is etched and removed at positions corresponding to the positions where the color resistance units 191 are deposited, thereby exposing the corresponding substrate 30, where the color resistance units 191 are directly deposited on the substrate 30. Thus, the number of film interfaces between the color resistance unit 191 and the substrate 30 is controlled to be less than 3, and the brightness of front light emission is improved. Of course, the buffer layer 12 may be deposited directly on the desired position, without affecting the deposition of the color resistance unit 191 directly on the substrate 30.
Referring to fig. 10, the present application further provides a display panel 100, including the array substrate 10 as described above, an OLED light emitting layer 20 is disposed on the array substrate 10, and a package 50 is disposed on the OLED light emitting layer 20. Since the array substrate in the display panel 100 of the present application includes all the technical solutions of all the embodiments, at least all the advantages brought by the technical solutions of the embodiments are provided, and no further description is provided herein.
As known, the OLED display panel 100 is a current type semiconductor light emitting device based on an organic material. Here, the OLED light emitting layer 20 includes a light emitting layer 21 (EL), a Cathode layer 22 (Cathode), and an encapsulation layer 23 (Film Encap), the light emitting layer 21 is made of an organic material, and the Cathode layer 22 may be made of a metal material such as Al. By applying a voltage, the metals of the pixel electrode and the cathode layer 22, which are anodes, respectively input electrons and holes to the organic light emitting layer 21, and excitons are generated therein, and light is emitted in a radiation manner, and the light passes through the planarization layer 18 and the color resist portion 19, thereby realizing display of a color screen. The structure of the OLED light emitting layer 20 is only for understanding the display panel 100 of the present application and is not limited to the above structure, for example, the OLED light emitting layer 20 further includes a hole transport layer and the like.
On the basis of reducing the number and thickness of film layers through which emergent light passes, the light-emitting brightness can be effectively improved, so that the material life of the light-emitting layer 21 of the OLED light-emitting layer 20 can be prolonged, and the service performance of the OLED light-emitting layer 20 is improved.
In addition, in order to define the space between the pixel electrodes, a pixel defining layer 40 (PDL) is further disposed between the pixel electrode layer 17 and the OLED light emitting layer 20, and the pixel defining layer 40 is disposed on the planarization layer 18 and is disposed corresponding to the position of the thin film transistor 13; the pixel defining layer 40 extends to the periphery and covers a portion of the pixel electrode, thereby forming a more stable structure.
The OLED light emitting layer 20 may be directly deposited on the pixel electrode layer 17, or may be separately fabricated, and then the OLED light emitting layer 20 is assembled to the array substrate 10 in an abutting manner. Here, when directly depositing on pixel electrode layer 17, need not to increase other technologies, only need deposit each layer in proper order can, effectively guarantee the shaping effect, conveniently process, reduce assembly process, improve machining efficiency. Of course, if the OLED light emitting layer 20 is manufactured separately, the edges of the two layers may be aligned by using a device and then bonded to ensure the yield of the product.
A package 50 is further disposed above the OLED light emitting layer 20, and the material of the package 50 may be glass or metal foil, so as to correspond to the display panel 100 that can be formed in a planar shape or the display panel 100 that can be flexibly bent.
The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications and equivalents of the subject matter of the present application, which is intended to be covered by the claims and their equivalents, or which are directly or indirectly applicable to other related arts are intended to be included within the scope of the present application.
Claims (10)
1. An array substrate is divided into a light-transmitting area and a non-light-transmitting area; the array substrate comprises a substrate and a thin film transistor layer, wherein the thin film transistor layer is arranged on the substrate; the thin film transistor layer comprises a thin film transistor part corresponding to the non-light-transmitting area and a color resistance part corresponding to the light-transmitting area; the method is characterized in that:
the color resistance part is directly arranged on the substrate;
or an inorganic film layer or an organic film layer is arranged between the color resistance part and the substrate, and the total number of the inorganic film layer or the organic film layer is equal to 1.
2. The array substrate of claim 1, wherein a light shielding layer and a first buffer layer are disposed between the substrate and the thin film transistor layer, the light shielding layer is disposed on the substrate at a position corresponding to the thin film transistor portion, the first buffer layer is disposed on the light shielding layer and the substrate, and the color resist portion is disposed on the first buffer layer.
3. The array substrate of claim 2, wherein a second buffer layer is further disposed between the thin film transistor portion and the first buffer layer.
4. The array substrate of claim 1, wherein when the color resists are directly disposed on the substrate, a light-shielding layer, a first buffer layer and a second buffer layer are sequentially disposed between the thin film transistor portion and the substrate.
5. The array substrate according to any one of claims 1 to 4, wherein the thin film transistor portion comprises an active layer, a gate insulating layer, a gate electrode, an organic insulating layer, and a source electrode and a drain electrode which are disposed on the organic insulating layer and are spaced apart from each other; and the source electrode and the drain electrode are respectively connected with the active layer through the via hole of the organic insulating layer.
6. The array substrate of any one of claims 2 to 4, wherein the first buffer layer has a refractive index ranging from 1.0 to 1.2.
7. The array substrate according to any one of claims 1 to 4, wherein the color resistance portion is composed of a red color resistance unit, a green color resistance unit, and a blue color resistance unit;
alternatively, the color resistance portion is composed of a red color resistance unit, a green color resistance unit, a blue color resistance unit, and a white color resistance unit.
8. The manufacturing method of the array substrate is characterized by comprising the following steps of:
providing a substrate, and forming a light shielding layer on the substrate;
forming a buffer layer on the light-shielding layer;
forming a plurality of thin film transistors on the buffer layer at positions corresponding to the light shielding layer;
forming a plurality of color resistance units arranged at intervals on the substrate or the buffer layer, wherein the thin film transistor is positioned between two adjacent color resistance units;
and forming a flat layer and a pixel electrode layer on the color resistance unit and the thin film transistor.
9. The method for manufacturing the array substrate according to claim 8, wherein when the plurality of color resistance units are formed on the substrate, the step of forming the plurality of color resistance units arranged at intervals on the substrate or the buffer layer includes:
etching the buffer layer, and etching off the buffer layers on two sides of the thin film transistor;
and directly forming a plurality of color resistance units on the substrate.
10. A display panel comprising an array substrate, an OLED light-emitting layer disposed on the array substrate, and a package disposed on the OLED light-emitting layer, wherein the array substrate is the array substrate according to any one of claims 1 to 7.
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