CN113629073A - TFT backboard and display panel - Google Patents

TFT backboard and display panel Download PDF

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CN113629073A
CN113629073A CN202110848391.2A CN202110848391A CN113629073A CN 113629073 A CN113629073 A CN 113629073A CN 202110848391 A CN202110848391 A CN 202110848391A CN 113629073 A CN113629073 A CN 113629073A
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electrode
tft
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source
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CN113629073B (en
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陈远鹏
徐源竣
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

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Abstract

The embodiment of the application provides a TFT backboard and a display panel. The TFT back plate comprises a driving TFT, and the driving TFT comprises a shading layer, an active layer, a grid electrode and a source drain electrode metal layer which are sequentially stacked and arranged at intervals; the light shielding layer and the grid electrode are arranged corresponding to the active layer; the source drain metal layer comprises a source electrode, a drain electrode and a switching layer; the switching layer is respectively connected with the grid electrode and the shading layer to electrically connect the grid electrode and the shading layer. The TFT backplate that this application embodiment provided adopts the light shield layer to cover the active layer to improve drive TFT's illumination stability, still adopt simultaneously to connect grid and light shield layer with source electrode and drain electrode with the switching layer that the layer set up, make drive TFT form double gate TFT structure, can improve drive TFT's output current, and guarantee that the TFT backplate has better stability, this TFT backplate can be used to realize the drive of jumbo size high refresh rate high brightness's display panel.

Description

TFT backboard and display panel
Technical Field
The application relates to the technical field of display, in particular to a TFT backboard and a display panel.
Background
An Active-matrix organic light-emitting diode (AMOLED) Display technology has higher contrast than an LCD (Liquid Crystal Display) Display, has richer color reduction capability, can realize flexible foldable Display, is a high-performance Display technology for replacing an LCD, and is widely applied to many high-end Display fields such as flexible foldable Display, large-size transparent Display and the like in recent years. The large size, high resolution and high refresh rate of the AMOLED technology are the prerequisite for realizing 8K +5G, and are also the mainstream display technology in the future.
The LED (light-emitting diode) display technology is a novel active light-emitting display technology, has a higher contrast than LCD and AMOLED display, has a richer color reduction capability, is a high-performance display technology for replacing LCD and AMOLED, and is widely applied to many high-end display fields in recent years. The LED display technology can be divided into a Mini-LED and a micro-LED according to the size of the light emitting unit, wherein the Mini-LED can realize direct display and serve as a backlight for high-end LCD display, and the micro-LED can realize higher resolution display than the Mini-LED.
The traditional AMOLED display panel and the LED display panel both adopt a 3T1C driving framework, and are combined with an oxide semiconductor Thin Film Transistor (TFT), so that the problems of low driving current and poor backboard reliability are faced to a certain extent, and the high-performance display integrating large-size, high-resolution and high-refresh rate is difficult to realize.
Disclosure of Invention
The embodiment of the application provides a TFT backplate and display panel, and the TFT backplate can be applied to display panel, and the TFT backplate has stronger current driving ability and reliability.
In a first aspect, an embodiment of the present application provides a TFT backplane, which includes a driving TFT, where the driving TFT includes a light shielding layer, an active layer, a gate electrode, and a source/drain metal layer that are sequentially stacked and arranged at intervals;
the light shielding layer and the grid electrode are arranged corresponding to the active layer;
the source drain metal layer comprises a source electrode, a drain electrode and a switching layer;
the switching layer is respectively connected with the grid electrode and the shading layer, so that the grid electrode is electrically connected with the shading layer.
In some embodiments, the TFT backplane further comprises a substrate base plate, a buffer layer, a gate insulating layer, and an interlayer dielectric layer;
the light shielding layer is arranged on the substrate, and the buffer layer covers the light shielding layer and the substrate;
the active layer, the gate insulating layer and the gate are sequentially stacked on the buffer layer, and the interlayer dielectric layer covers the active layer, the gate insulating layer and the gate;
the source drain electrode metal layer is arranged on the interlayer dielectric layer;
a first through hole is formed in the interlayer dielectric layer between the switching layer and the grid electrode, and the switching layer is connected with the grid electrode through the first through hole;
and a second through hole is formed in the interlayer dielectric layer between the switching layer and the shading layer and on the buffer layer, and the switching layer is connected with the shading layer through the second through hole.
In some embodiments, the TFT backplane further comprises a passivation layer, a planarization layer, a first electrode, and a pixel definition layer;
the passivation layer covers the source drain metal layer and the interlayer dielectric layer;
the flat layer covers the passivation layer;
the first electrode is arranged on the flat layer, and the pixel defining layer covers the first electrode and the flat layer;
a third through hole is formed in the passivation layer and the flat layer between the first electrode and the source electrode, and the first electrode is connected with the source electrode through the third through hole;
and a fourth through hole is formed in the area, corresponding to the first electrode, of the pixel defining layer, and the bottom of the fourth through hole is used for arranging an OLED device.
In some embodiments, the TFT backplane further comprises a passivation layer, a conductive layer, and an insulating protection layer;
the passivation layer covers the source drain metal layer and the interlayer dielectric layer;
the conducting layer comprises a second electrode and a third electrode which are arranged at intervals; the conducting layer is arranged on the passivation layer, and the insulating protection layer covers the conducting layer and the passivation layer;
a fifth through hole is formed in the passivation layer between the second electrode and the source electrode, and the second electrode is connected with the source electrode through the fifth through hole;
and a sixth through hole is formed in the area, corresponding to the second electrode, of the insulating protection layer, a seventh through hole is formed in the area, corresponding to the third electrode, of the insulating protection layer, the part, exposed in the sixth through hole, of the second electrode is used for being connected with the anode of the LED device, and the part, exposed in the seventh through hole, of the third electrode is used for being connected with the cathode of the LED device.
In some embodiments, the material of the active layer is an oxide semiconductor material.
In some embodiments, the oxide semiconductor material includes an indium element, a zinc element, and an oxygen element, and a molar amount of the indium element is greater than a molar amount of the zinc element in the oxide semiconductor material.
In some embodiments, the material of the light shielding layer comprises one or more of molybdenum, aluminum, copper, titanium, tungsten, chromium, nickel and metal alloys thereof, and the thickness of the light shielding layer is
Figure BDA0003181545980000031
In some embodiments, the gate includes a first metal layer and a second metal layer stacked, the first metal layer is disposed toward the active layer, and the second metal layer is disposed toward the source/drain metal layer;
the material of the first metal layer comprises at least one of molybdenum, titanium, tungsten, chromium, nickel and metal alloys of the molybdenum, the titanium, the tungsten, the chromium and the nickel, and the thickness of the first metal layer is
Figure BDA0003181545980000032
The material of the second metal layer comprises at least one of aluminum and copper, and the thickness of the second metal layer is
Figure BDA0003181545980000033
In a second aspect, an embodiment of the present application further provides a display panel, which includes a TFT backplane and a light emitting device, where the TFT backplane is the TFT backplane as described above, and a source of the driving TFT in the TFT backplane is electrically connected to the light emitting device.
In some embodiments, the light emitting device comprises at least one of an OLED device and an LED device.
The TFT backplate that this application embodiment provided adopts the light shield layer to cover the active layer to improve drive TFT's illumination stability, still adopt simultaneously to connect grid and light shield layer with source electrode and drain electrode with the switching layer that the layer set up, make drive TFT form double gate TFT structure, can improve drive TFT's output current, and guarantee that the TFT backplate has better stability, this TFT backplate can be used to realize the drive of jumbo size high refresh rate high brightness's display panel.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a schematic view of a first structure of a TFT backplane according to an embodiment of the present disclosure.
Fig. 2 is a schematic view of a first structure of a display panel according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a second structure of a TFT backplane according to an embodiment of the present disclosure.
Fig. 4 is a schematic view of a second structure of a display panel according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic view illustrating a first structure of a TFT backplane according to an embodiment of the present disclosure. The embodiment of the application provides a TFT backplane 100, which can be applied to an AMOLED display backplane to improve the current driving capability of the AMOLED display backplane, where the TFT backplane 100 may include a driving TFT, and the driving TFT includes a light shielding layer 20, an active layer 40, a gate 50, and a source drain metal layer, which are sequentially stacked and arranged at intervals; the light shielding layer 20 and the gate electrode 50 are both arranged corresponding to the active layer 40; the source and drain metal layer comprises a source electrode 61, a drain electrode 62 and a transfer layer 63; the via layer 63 connects the gate electrode 50 and the light-shielding layer 20, respectively, and electrically connects the gate electrode 50 and the light-shielding layer 20. It is understood that the driving TFT refers to a TFT for driving a light emitting device to emit light, and an output current of the driving TFT directly affects performance parameters such as light emission luminance of the light emitting device.
In the TFT backplane 100 according to the embodiment of the present application, the light shielding layer 20 can significantly improve the illumination stability of the driving TFT, and after the gate electrode 50 is connected to the light shielding layer 20, the gate electrode 50 substantially constitutes a top gate, and the light shielding layer 20 substantially constitutes a bottom gate, that is, the driving TFT substantially has a dual-gate TFT structure. In the conventional TFT structure, the light shielding layer 20 is usually connected to the source electrode 61 to improve the illumination stability and the output saturation characteristic of the driving TFT, but the structure can suppress the output current of the TFT and significantly reduce the driving characteristic of the TFT. While having a higher output current, the TFT backplane 100 of the embodiment of the present application also has a stronger stability, and can be used for driving a large-sized, high-refresh-rate, and high-brightness display panel.
Referring to fig. 1, the TFT backplane 100 may further include a substrate 10, a buffer layer 31, a gate insulating layer 32, and an interlayer dielectric layer 33;
the light-shielding layer 20 is arranged on the substrate 10, and the buffer layer 31 covers the light-shielding layer 20 and the substrate 10;
an active layer 40, a gate insulating layer 32, and a gate electrode 50 are sequentially stacked on the buffer layer 31, and an interlayer dielectric layer 33 covers the active layer 40, the gate insulating layer 32, and the gate electrode 50;
the source drain metal layer is arranged on the interlayer dielectric layer 33;
a first through hole 91 is formed in the interlayer dielectric layer 33 between the via layer 63 and the gate 50, and the via layer 63 is connected to the gate 50 through the first through hole 91;
the interlayer dielectric layer 33 and the buffer layer 31 between the transition layer 63 and the light-shielding layer 20 are provided with second through holes 92, and the transition layer 63 is connected to the light-shielding layer 20 through the second through holes 92.
Referring to fig. 1, the TFT backplane 100 may further include a passivation layer 34, a planarization layer 35, a first electrode 71, and a pixel defining layer 80;
the passivation layer 34 covers the source drain metal layer and the interlayer dielectric layer 33;
the planarization layer 35 covers the passivation layer 34;
the first electrode 71 is disposed on the planarization layer 35, and the pixel defining layer 80 covers the first electrode 71 and the planarization layer 35;
a third through hole 93 is formed in the passivation layer 34 and the planarization layer 35 between the first electrode 71 and the source electrode 61, and the first electrode 71 and the source electrode 61 are connected through the third through hole 93;
the pixel defining layer 80 is provided with a fourth through hole 94 in a region corresponding to the first electrode 71, and the bottom of the fourth through hole 94 is used for arranging the OLED device 101.
The base substrate 10 may be a glass substrate.
The material of the light-shielding layer 20 may be one or more of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni), and metal alloys thereof, and the thickness of the light-shielding layer 20 may be
Figure BDA0003181545980000051
The buffer layer 31 may be a single layer of silicon nitride (SiN)x) Single layer silicon oxide (SiO)x) Single layer silicon oxynitride (SiO)xNx) Or a double-layer composite film of the above materials, the buffer layer 31 may have a thickness of
Figure BDA0003181545980000052
The material of the active layer 40 may be an oxide semiconductor material. Illustratively, the oxide semiconductor material contains an indium (In) element, a zinc (Zn) element, and an oxygen (O) element, and the molar amount of the indium element is larger than the molar amount of the zinc element In the oxide semiconductor material. The molar weight of indium and zinc elements in a traditional oxide semiconductor material IGZO (indium gallium zinc oxide) is 1:1, and the mobility of the oxide semiconductor material can be improved by increasing the content of the indium element, so that the output current of a driving TFT (thin film transistor) is improved. The dual-gate TFT structure formed by connecting the light shielding layer 20 and the gate electrode 50 as described above is known to improve the mobility of the driving TFT, and by improving the TFT structure and improving the oxide semiconductor material, the output current of the driving TFT can be increased to 2 times or more of the original output current while ensuring high illumination stability, and the problems of reduction in the emission brightness, refresh rate, resolution, display size, and the like of the AMOLED display panel due to reduction in the driving current can be significantly improved.
The material of the gate insulating layer 32 may be silicon oxide (SiO)2) The thickness of the gate insulating layer 32 may be
Figure BDA0003181545980000061
The gate electrode 50 may include a first metal layer and a second metal layer stacked, the first metal layer being disposed toward the active layer 40, the second metal layer being disposed toward the source and drain metal layers; the material of the first metal layer can be at least one of molybdenum, titanium, tungsten, chromium, nickel and metal alloys of the molybdenum, the titanium, the tungsten, the chromium and the nickel, and the thickness of the first metal layer is
Figure BDA0003181545980000062
The material of the second metal layer may be at least one of aluminum and copper, and the thickness of the second metal layer may be
Figure BDA0003181545980000063
The material of the interlayer dielectric layer 33 may be silicon oxide (SiO)2) The thickness of the interlayer dielectric layer 33 may be
Figure BDA0003181545980000064
The source/drain metal layer may have a double-layer metal structure, wherein the first layer (adjacent to the interlayer dielectric layer 33) may be a transition metal material, such as molybdenum (Mo), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni), or an alloy thereof, or a conductive oxide material, such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), aluminum-doped zinc oxide (AZO), or the like, and the first layer may have a thickness of
Figure BDA0003181545980000065
The material of the second layer (close to the passivation layer 34) may be a metal material such as aluminum (Al), copper (Cu), etc., and the thickness of the second layer may be
Figure BDA0003181545980000066
The material of the passivation layer 34 may be silicon oxide (SiO)2) The thickness of the passivation layer 34 may be
Figure BDA0003181545980000067
The material of the first electrode 71 may be a metal or a transparent conductive metal oxide (e.g., ITO).
The material of the planarization layer 35 may be an organic material, such as a photoresist.
The material of the pixel defining layer 80 may be an organic material, such as a photoresist material.
The TFT backplane 100 of the embodiment of the present application may be a TFT backplane having a 3T1C driving architecture, and the TFT backplane 100 may further include a switching TFT and a detecting TFT, where a source of the switching TFT is connected to the gate 50 of the driving TFT, and the detecting TFT is electrically connected to the driving TFT for detecting performance of the driving TFT. Of course, the TFT backplane 100 of the embodiment of the present application may also be a TFT backplane having a 2T1C driving architecture.
The method for manufacturing the TFT backplane 100 provided in this embodiment may specifically include:
(1) cleaning the base substrate 10;
(2) depositing a light shielding layer 20 and carrying out patterning treatment;
(3) depositing a buffer layer 31 to cover the light-shielding layer 20;
(4) depositing an oxide semiconductor layer, and performing patterning to form an active region (active layer 40) of the driving TFT, an active region of the switching TFT, and an active region of the detecting TFT;
(5) depositing a gate insulating layer 32;
(6) depositing a grid metal layer;
(7) defining the pattern of the grid 50 and the pattern of the grid insulating layer 32 by using a photomask, firstly etching the grid metal layer by wet etching, and then etching the grid insulating layer 32 by using a dry method by using the metal protective layer pattern as self-alignment;
(8) processing a region, which is not protected by the gate insulating layer 32, on the oxide semiconductor layer using Plasma (Plasma) to form an N + conductor region serving as a source/drain electrode 61/62 contact; the oxide semiconductor layer under the gate insulating layer 32 is not processed and serves as a TFT channel;
(9) depositing an interlayer dielectric layer 33, and etching a source contact hole and a drain contact hole of the interlayer dielectric layer 33 and a switching hole of the light shielding layer 20 by using a patterning process;
(10) depositing a source and drain metal layer, and defining a source 61, a drain 62, a switching layer 63 and other metal wiring areas by using the same photomask;
(11) depositing a passivation layer 34 and etching a via hole;
(12) depositing a planarization layer 35, making via holes by yellow light;
(13) preparing a first electrode 71 for contacting the OLED light emitting device;
(14) the pixel definition layer 80 is deposited and the light emitting region is defined by yellow light to complete the fabrication of the TFT backplane 100.
Referring to fig. 2, fig. 2 is a first structural schematic diagram of a display panel according to an embodiment of the present disclosure. The embodiment of the application also provides an AMOLED display panel 200, which includes the TFT backplane 100 and the OLED device 101 shown in fig. 1, the OLED device 101 is disposed in the fourth through hole 94 and electrically connected to the first electrode 71, and the structure of the TFT backplane 100 is described above and is not described herein.
Referring to fig. 3, fig. 3 is a schematic diagram of a second structure of a TFT backplane according to an embodiment of the present disclosure. The embodiment of the application further provides a TFT backplane 100 ' which can be applied to an LED display backplane to improve the current driving capability of the LED display backplane, and the TFT backplane 100 ' can include a driving TFT, where the driving TFT includes a light shielding layer 20 ', an active layer 40 ', a gate 50 ', and a source drain metal layer, which are sequentially stacked and arranged at intervals; the light shielding layer 20 ' and the gate electrode 50 ' are both disposed corresponding to the active layer 40 '; the source and drain metal layer comprises a source electrode 61 ', a drain electrode 62 ' and a transfer layer 63 '; the via layer 63 ' connects the gate electrode 50 ' and the light-shielding layer 20 ', respectively, and electrically connects the gate electrode 50 ' and the light-shielding layer 20 '.
It is understood that the light shielding layer 20 ' can significantly improve the light stability of the driving TFT, and after the gate electrode 50 ' is connected to the light shielding layer 20 ', the gate electrode 50 ' substantially constitutes a top gate, and the light shielding layer 20 ' substantially constitutes a bottom gate, that is, the driving TFT substantially has a dual-gate TFT structure. In the conventional TFT structure, the light shielding layer 20 'is usually connected to the source electrode 61' to improve the illumination stability and the output saturation characteristic of the TFT, but the structure can suppress the output current of the TFT and significantly reduce the driving characteristic of the TFT. The TFT backplane 100' of the embodiment of the present application has a relatively high output current, and also has a relatively high stability, and can be used for driving a large-sized, high-refresh-rate, and high-brightness display panel.
Referring to fig. 3, the TFT backplane 100 ' may further include a substrate 10 ', a buffer layer 31 ', a gate insulating layer 32 ', and an interlayer dielectric layer 33 ';
the shading layer 20 ' is arranged on the substrate 10 ', and the buffer layer 31 ' covers the shading layer 20 ' and the substrate 10 ';
an active layer 40 ', a gate insulating layer 32' and a gate electrode 50 'are sequentially stacked on the buffer layer 31', and an interlayer dielectric layer 33 'covers the active layer 40', the gate insulating layer 32 'and the gate electrode 50';
the source drain metal layer is arranged on the interlayer dielectric layer 33';
a first through hole 91 ' is formed in the interlayer dielectric layer 33 ' between the via layer 63 ' and the gate 50 ', and the via layer 63 ' is connected to the gate 50 ' through the first through hole 91 ';
the interlayer dielectric layer 33 'between the via layer 63' and the light-shielding layer 20 'and the buffer layer 31' are provided with second through holes 92 ', and the via layer 63' is connected to the light-shielding layer 20 'through the second through holes 92'.
Referring to fig. 3, the TFT backplane 100 ' may further include a passivation layer 34 ', a conductive layer, and an insulating protection layer 36 ';
the passivation layer 34 'covers the source drain metal layer and the interlayer dielectric layer 33';
the conductive layer comprises a second electrode 72 'and a third electrode 73' which are arranged at intervals; the conductive layer is arranged on the passivation layer 34 ', and the insulating protection layer 36 ' covers the conductive layer and the passivation layer 34 ';
a fifth through hole 95 ' is formed in the passivation layer 34 ' between the second electrode 72 ' and the source electrode 61 ', and the second electrode 72 ' and the source electrode 61 ' are connected through the fifth through hole 95 ';
the insulating protection layer 36 'is provided with a sixth through hole 96' in a region corresponding to the second electrode 72 ', the insulating protection layer 36' is provided with a seventh through hole 97 'in a region corresponding to the third electrode 73', a portion of the second electrode 72 'exposed in the sixth through hole 96' is used for connecting the anode of the LED device 102 ', and a portion of the third electrode 73' exposed in the seventh through hole 97 'is used for connecting the cathode of the LED device 102'.
The substrate base plate 10' may be a glass base plate.
The material of the light-shielding layer 20 'may be one or more of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni) and metal alloys thereof, and the thickness of the light-shielding layer 20' may be
Figure BDA0003181545980000091
The buffer layer 31' may be a single layer of silicon nitride (SiN)x) Single layer silicon oxide (SiO)x) Single layer silicon oxynitride (SiO)xNx) Or a double-layer composite film of the above materials, the buffer layer 31' may have a thickness of
Figure BDA0003181545980000092
The material of the active layer 40' may be an oxide semiconductor material. Illustratively, the oxide semiconductor material contains an indium (In) element, a zinc (Zn) element, and an oxygen (O) element, and the molar amount of the indium element is larger than the molar amount of the zinc element In the oxide semiconductor material. The molar weight of indium and zinc elements in a traditional oxide semiconductor material IGZO (indium gallium zinc oxide) is 1:1, and the mobility of the oxide semiconductor material can be improved by increasing the content of the indium element, so that the output current of a driving TFT (thin film transistor) is improved. The mobility of the driving TFT can be improved by the double-gate TFT structure formed by connecting the light shielding layer 20 'and the gate electrode 50', and the application can improve the output current of the driving TFT by 2 times or more than the original output current while ensuring the stability of high illumination by improving the TFT structure and improving the oxide semiconductor material, thereby significantly improving the requirement of the LED display panel for high driving current.
The material of the gate insulating layer 32' may be silicon oxide (SiO)2) The gate insulating layer 32' may have a thickness of
Figure BDA0003181545980000093
The gate electrode 50 'may include a first metal layer and a second metal layer stacked, the first metal layer being disposed toward the active layer 40', and the second metal layer being disposed toward the source and drain metal layers; the material of the first metal layer can be at least one of molybdenum, titanium, tungsten, chromium, nickel and metal alloys of the molybdenum, the titanium, the tungsten, the chromium and the nickel, and the thickness of the first metal layer is
Figure BDA0003181545980000094
The material of the second metal layer may be at least one of aluminum and copper, and the thickness of the second metal layer may be
Figure BDA0003181545980000095
The material of the interlayer dielectric layer 33' may be silicon oxide (SiO)2) The thickness of the interlayer dielectric layer 33' may be
Figure BDA0003181545980000101
The source/drain metal layer may have a double-layered metal structure, wherein the first layer (adjacent to the interlayer dielectric layer 33') may be a transition metal material, such as molybdenum (Mo), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni), or an alloy thereof, or a conductive oxide material, such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), aluminum-doped zinc oxide (AZO), or the like, and the first layer may have a thickness of
Figure BDA0003181545980000102
The material of the second layer (close to the passivation layer 34') may be a metal material such as aluminum (Al), copper (Cu), etc., and the thickness of the second layer may be
Figure BDA0003181545980000103
The material of the passivation layer 34' may be silicon oxide (SiO)2) The thickness of the passivation layer 34' may be
Figure BDA0003181545980000104
The material of the conductive layer may be a metal or a transparent conductive metal oxide (e.g., ITO).
The material of the insulating protective layer 36' may be an organic insulating material, such as a photoresist material. The insulating protective layer 36 may function to prevent conduction between the second electrode 72 'and the third electrode 73', and protect the underlying stacked structure.
The TFT backplane 100 'in the embodiment of the present application may be a TFT backplane having a 3T1C driving architecture, that is, the TFT backplane 100' may further include a switching TFT and a detecting TFT, where a source 61 'of the switching TFT is connected to a gate 50' of the driving TFT, and the detecting TFT is electrically connected to the driving TFT for detecting performance of the driving TFT. Of course, the TFT backplane 100' of the embodiment of the present application may also be a TFT backplane having a 2T1C driving architecture.
The method for manufacturing the TFT backplane 100' provided in this embodiment may specifically include:
(1) cleaning the base substrate 10';
(2) depositing a light shielding layer 20' and carrying out patterning treatment;
(3) depositing a buffer layer 31 'to cover the light-shielding layer 20';
(4) depositing an oxide semiconductor layer, and performing patterning to form an active region (active layer 40') of the driving TFT, an active region of the switching TFT, and an active region of the detecting TFT;
(5) depositing a gate insulating layer 32';
(6) depositing a grid metal layer;
(7) defining the pattern of the gate 50 ' and the pattern of the gate insulating layer 32 ' by using a photomask, etching the gate metal layer by wet etching, and etching the gate insulating layer 32 ' by dry etching by using the metal protective layer pattern as self-alignment;
(8) processing a region not protected by the gate insulating layer 32 ' on the oxide semiconductor layer using Plasma (Plasma) to form an N + conductor region serving as a source/drain electrode 61 '/62 ' contact; the oxide semiconductor layer under the gate insulating layer 32' is not processed and serves as a TFT channel;
(9) depositing an interlayer dielectric layer 33 ', and etching a source contact hole and a drain contact hole of the interlayer dielectric layer 33 ' and a transfer hole of the light-shielding layer 20 ' by using a patterning process;
(10) depositing a source and drain metal layer, and defining a source electrode 61 ', a drain electrode 62 ', a switching layer 63 ' and other metal wiring areas by using the same photomask;
(11) depositing a passivation layer 34' and etching a via;
(12) depositing a conductive layer, and preparing a second electrode 72 ' and a third electrode 73 ' through a patterning process to contact the LED device 102 ';
(13) and depositing an insulating protection layer 36 ', defining a binding region (a sixth through hole 96 ' and a seventh through hole 97 ') of the LED device 102 ' by yellow light, and finishing the manufacturing of the TFT backboard 100 '.
Referring to fig. 4, fig. 4 is a schematic view illustrating a second structure of a display panel according to an embodiment of the present disclosure. The embodiment of the present application further provides an LED display panel 200 ', which includes the TFT backplane 100' and the LED device 102 'shown in fig. 3, wherein the anode of the LED device 102' is electrically connected to the second electrode 72 ', the cathode of the LED device 102' is electrically connected to the third electrode 73 ', and the structure of the TFT backplane 100' is described above and is not repeated herein.
The TFT backplane and the display panel provided in the embodiments of the present application are described in detail above. The principles and implementations of the present application are described herein using specific examples, which are presented only to aid in understanding the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. The TFT backboard is characterized by comprising a driving TFT, wherein the driving TFT comprises a shading layer, an active layer, a grid electrode and a source drain metal layer which are sequentially stacked and arranged at intervals;
the light shielding layer and the grid electrode are arranged corresponding to the active layer;
the source drain metal layer comprises a source electrode, a drain electrode and a switching layer;
the switching layer is respectively connected with the grid electrode and the shading layer, so that the grid electrode is electrically connected with the shading layer.
2. The TFT backplane of claim 1, further comprising a substrate, a buffer layer, a gate insulating layer, and an interlayer dielectric layer;
the light shielding layer is arranged on the substrate, and the buffer layer covers the light shielding layer and the substrate;
the active layer, the gate insulating layer and the gate are sequentially stacked on the buffer layer, and the interlayer dielectric layer covers the active layer, the gate insulating layer and the gate;
the source drain electrode metal layer is arranged on the interlayer dielectric layer;
a first through hole is formed in the interlayer dielectric layer between the switching layer and the grid electrode, and the switching layer is connected with the grid electrode through the first through hole;
and a second through hole is formed in the interlayer dielectric layer between the switching layer and the shading layer and on the buffer layer, and the switching layer is connected with the shading layer through the second through hole.
3. The TFT backplane of claim 2, further comprising a passivation layer, a planarization layer, a first electrode, and a pixel definition layer;
the passivation layer covers the source drain metal layer and the interlayer dielectric layer;
the flat layer covers the passivation layer;
the first electrode is arranged on the flat layer, and the pixel defining layer covers the first electrode and the flat layer;
a third through hole is formed in the passivation layer and the flat layer between the first electrode and the source electrode, and the first electrode is connected with the source electrode through the third through hole;
and a fourth through hole is formed in the area, corresponding to the first electrode, of the pixel defining layer, and the bottom of the fourth through hole is used for arranging an OLED device.
4. The TFT backplane of claim 2, further comprising a passivation layer, a conductive layer, and an insulating protection layer;
the passivation layer covers the source drain metal layer and the interlayer dielectric layer;
the conducting layer comprises a second electrode and a third electrode which are arranged at intervals; the conducting layer is arranged on the passivation layer, and the insulating protection layer covers the conducting layer and the passivation layer;
a fifth through hole is formed in the passivation layer between the second electrode and the source electrode, and the second electrode is connected with the source electrode through the fifth through hole;
and a sixth through hole is formed in the area, corresponding to the second electrode, of the insulating protection layer, a seventh through hole is formed in the area, corresponding to the third electrode, of the insulating protection layer, the part, exposed in the sixth through hole, of the second electrode is used for being connected with the anode of the LED device, and the part, exposed in the seventh through hole, of the third electrode is used for being connected with the cathode of the LED device.
5. The TFT backplane of claim 1, wherein the material of the active layer is an oxide semiconductor material.
6. The TFT backplane of claim 5, wherein the oxide semiconductor material comprises indium element, zinc element, and oxygen element, and wherein a molar amount of indium element is greater than a molar amount of zinc element in the oxide semiconductor material.
7. The TFT backplane according to any of claims 1-6, wherein the material of the light-shielding layer comprises one or more of molybdenum, aluminum, copper, titanium, tungsten, chromium, nickel and metal alloys thereof, and the thickness of the light-shielding layer is
Figure FDA0003181545970000021
8. The TFT backplane according to any of claims 1-6, wherein the gate comprises a first metal layer and a second metal layer arranged in a stack, the first metal layer being disposed toward the active layer and the second metal layer being disposed toward the source drain metal layer;
the material of the first metal layer comprises at least one of molybdenum, titanium, tungsten, chromium, nickel and metal alloys of the molybdenum, the titanium, the tungsten, the chromium and the nickel, and the thickness of the first metal layer is
Figure FDA0003181545970000022
The material of the second metal layer comprises at least one of aluminum and copper, and the thickness of the second metal layer is
Figure FDA0003181545970000023
9. A display panel comprising a TFT backplane and a light emitting device, wherein the TFT backplane is as claimed in any one of claims 1 to 8, and the source of the driving TFT in the TFT backplane is electrically connected to the light emitting device.
10. The display panel of claim 9, wherein the light emitting device comprises at least one of an OLED device and an LED device.
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