CN113625188B - Bypass device failure detection device and method - Google Patents
Bypass device failure detection device and method Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
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- G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
- G01R19/16538—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies
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Abstract
The invention provides a bypass device failure detection device, wherein a first processor is connected with a second processor through an isolation module, the output power of a boost PFC converter determined by the second processor is obtained, a voltage theoretical value of an output capacitor in the boost PFC converter when a bypass device is closed is determined according to the obtained input current and input voltage of the primary side of a transformer in the boost PFC converter, the output power of the boost PFC converter and the time period from the bypass device to the bypass device, and whether the bypass device is in a failure state or not is judged according to the voltage theoretical value of the output capacitor in the boost PFC converter when the bypass device is closed and the voltage actual value of the output capacitor in the boost PFC converter when the bypass device is closed.
Description
Technical Field
The invention relates to the field of server power supply detection, in particular to a bypass device failure detection device and method.
Background
The Inrush Current (Inrush Current) is a device that an ac input Current quickly charges a primary side capacitor of an electrical device when the electrical device is powered on, and an Inrush Current Limiter (Inrush Current Limiter), also called an Inrush Current Limiter or an Inrush Current Limiter, is a device that limits the Inrush Current, and is intended to prevent electrical stress from damaging the electronic device and to prevent a Fuse (Fuse) from being blown or an open circuit (Breaker) from being tripped due to damage of a component on a primary side line caused by the impact of the Inrush Current.
Devices commonly used to limit inrush current include Negative Temperature Coefficient (NTC) thermistors, positive Temperature Coefficient (PTC) thermistors, and fixed-value resistors. The NTC thermistor can be connected in series to a circuit of a power supply to limit surge current, and the NTC thermistor has low temperature and high resistance when power is transmitted, so that large current generated when power is transmitted can be avoided. As the current continues to flow, the temperature of the NTC thermistor increases and the resistance value decreases, thus allowing a larger current to flow. The NTC thermistor is designed to be larger than a thermistor for measuring a temperature alone, and a current allowed to flow through the NTC thermistor is also large.
After the surge current is restrained, the surge current limiter becomes a part consuming energy, and the server power supply has a requirement for high efficiency, so a bypass device is connected in parallel beside the surge current limiter, and when the server power supply is in a normal state, the surge current limiter is restrained and can control the bypass device to be opened, at the moment, the surge current limiter can not flow current any more, the current can flow through the bypass device with small impedance, and the normal work and the efficiency improvement can be achieved.
After the bypass device is started, the bypass device starts to work, if the boost PFC converter circuit works normally, the output voltage of the boost PFC converter circuit is stabilized at the design voltage, if the bypass device is closed, the bypass device stops working, even if the boost PFC converter circuit works normally, the current is limited to pass through by the impedance in the middle, and the output capacitor of the boost PFC converter circuit cannot be charged and stabilized at the design voltage.
The abnormal short circuit of the bypass device connected with the surge current limiter in parallel is a failure mode which is frequently generated, the bypass device is uncontrollable after the short circuit, the surge current limiter loses the function, and subsequently, if the stress during the voltage restart or the transient interruption occurs, parts on a power supply path can be damaged, or the idle switch at a machine room end is tripped, so that the normal power supply of a server power supply is not facilitated.
Disclosure of Invention
The invention aims to solve the problems in the prior art, and innovatively provides a bypass device failure detection device and method, so that the problems of device damage on a power supply path of a power supply and machine room end idle trip caused by the abnormality of a bypass device are effectively solved, and the power supply stability and reliability of a server power supply are effectively improved.
A first aspect of the present invention provides a bypass failure detection apparatus, including: the boost PFC converter comprises an inrush current module comprising a bypass device, a boost PFC converter, a first processor, a second processor and an isolation module, wherein the input end of the inrush current module is connected with the output end of alternating current, the output end of the inrush current module is connected with the input end of the boost PFC converter, and the first output end of the boost PFC converter is connected with the input end of the first processor; the second output end of the boost PFC converter is connected with the input end of the second processor; the second processor determines the output power of the boost PFC converter according to the acquired output current and output voltage of the secondary side of the transformer in the boost PFC converter; the first processor is connected with the second processor through the isolation module and used for obtaining the output power of the boost PFC converter determined by the second processor when the first processor communicates with the second processor, determining a voltage theoretical value of an output capacitor in the boost PFC converter when a bypass is closed according to the obtained input current and input voltage of the primary side of a transformer in the boost PFC converter, the output power of the boost PFC converter and the time period from the bypass opening to the bypass closing, and judging whether the bypass is in a failure state or not according to the voltage theoretical value of the output capacitor in the boost PFC converter when the bypass is closed and the voltage actual value of the output capacitor in the boost PFC converter when the bypass is closed.
Optionally, the specific theoretical voltage value of the output capacitor in the boost PFC converter when the bypass is closed is determined according to the input current at the primary side of the transformer in the boost PFC converter, the input voltage, the output power of the boost PFC converter, and the time period from the bypass being turned on to the bypass being turned off:
determining the input power of the boost PFC converter according to the acquired input current and input voltage of the primary side of a transformer in the boost PFC converter;
determining the efficiency of the boost PFC converter according to the input power of the boost PFC converter and the output power of the boost PFC converter;
and determining a voltage theoretical value of the output capacitor in the boost PFC converter when the bypass is closed according to the output power of the boost PFC converter, the efficiency of the boost PFC converter, the output capacitor in the boost PFC converter, the voltage of the output capacitor in the boost PFC converter before the bypass is opened and the time period from the bypass opening to the bypass closing.
Further, determining a theoretical voltage value of the output capacitor of the boost PFC converter during bypass failure detection according to the output power of the boost PFC converter, the efficiency of the boost PFC converter, the output capacitor of the boost PFC converter, the voltage of the output capacitor of the boost PFC converter before the bypass is turned on, and a time period from the bypass is turned on to the bypass is specifically:
Optionally, the determining, according to the theoretical voltage value of the output capacitor of the boost PFC converter when the bypass is closed and the actual voltage value of the output capacitor of the boost PFC converter when the bypass is closed, whether the bypass is in the failure state specifically includes:
comparing the actual voltage value of an output capacitor in the boost PFC converter when the bypass device is closed with a preset voltage threshold value, wherein the preset voltage threshold value is half of the sum of the voltage of the output capacitor in the boost PFC converter before the bypass device is started and the theoretical voltage value of the output capacitor in the boost PFC converter when the bypass device is closed;
if the actual voltage value of an output capacitor in the boost PFC converter when the bypass device is closed is smaller than a preset voltage threshold value, the bypass device is normally opened and closed; if the voltage value of the output capacitor in the boost PFC converter when the bypass device is closed is larger than the preset voltage threshold value, the bypass device is not normally started and is in a failure state.
Further, when the bypass device is in the failure state, the first processor outputs an alarm signal to alarm.
Optionally, the isolation module is a MOS transistor.
A second aspect of the present invention provides a bypass device failure detection method, which is implemented based on the bypass device failure detection apparatus in the first aspect of the present invention, and includes:
the first processor controls the bypass device to be started, and controls the bypass device to be closed after the bypass device is started for a first time period, so that input voltage and input current of a primary side of a transformer in the boost PFC converter are obtained;
acquiring output power of a secondary side of a transformer in the boost PFC converter determined by the second processor through an isolation module;
and determining a voltage theoretical value of an output capacitor in the boost PFC converter when a bypass is closed according to the acquired input current and input voltage of the primary side of a transformer in the boost PFC converter, the output power of the boost PFC converter and the time period from the bypass to the bypass, and judging whether the bypass is in a failure state or not according to the voltage theoretical value of the output capacitor in the boost PFC converter when the bypass is closed and the voltage actual value of the output capacitor in the boost PFC converter when the bypass is closed.
Optionally, the determination of the theoretical voltage value of the output capacitor in the boost PFC converter when the bypass is closed according to the input current, the input voltage, the output power of the boost PFC converter at the primary side of the transformer in the boost PFC converter, and the time period from the bypass being turned on to the bypass being turned off is specifically:
determining the input power of the boost PFC converter according to the acquired input current and input voltage of the primary side of a transformer in the boost PFC converter;
determining the efficiency of the boost PFC converter according to the input power of the boost PFC converter and the output power of the boost PFC converter;
and determining a voltage theoretical value of the output capacitor in the boost PFC converter when the bypass is closed according to the output power of the boost PFC converter, the efficiency of the boost PFC converter, the output capacitor in the boost PFC converter, the voltage of the output capacitor in the boost PFC converter before the bypass is opened and the time period from the bypass opening to the bypass closing.
Further, determining a theoretical voltage value of the output capacitor of the boost PFC converter when the bypass is closed according to the output power of the boost PFC converter, the efficiency of the boost PFC converter, the output capacitor of the boost PFC converter, the voltage of the output capacitor of the boost PFC converter before the bypass is turned on, and a time period from the bypass is turned on to the bypass is specifically:
Optionally, the determining, according to the theoretical voltage value of the output capacitor of the boost PFC converter when the bypass is closed and the actual voltage value of the output capacitor of the boost PFC converter when the bypass is closed, whether the bypass is in the failure state specifically includes:
comparing the actual voltage value of an output capacitor in the boost PFC converter when the bypass device is closed with a preset voltage threshold value, wherein the preset voltage threshold value is half of the sum of the voltage of the output capacitor in the boost PFC converter before the bypass device is started and the theoretical voltage value of the output capacitor in the boost PFC converter when the bypass device is closed;
if the actual voltage value of an output capacitor in the boost PFC converter when the bypass device is closed is smaller than a preset voltage threshold value, the bypass device is normally opened and closed; if the voltage value of the output capacitor in the boost PFC converter when the bypass device is closed is larger than the preset voltage threshold value, the bypass device is not normally started and is in a failure state
The technical scheme adopted by the invention comprises the following technical effects:
1. the invention effectively solves the problems of device damage on a power supply path of the power supply and tripping at the air switch of the machine room end caused by the abnormality of the bypass device, and effectively improves the stability and reliability of the power supply of the server power supply.
2. The technical scheme of the invention can detect whether the bypass device connected in parallel with the surge current limiter is invalid or not, and store and feed back the abnormality, thereby avoiding the problem that the server is influenced by the trip of the machine room when the Power supply unit (Power supply unit) in the server is damaged.
3. In the technical scheme of the invention, the first processor and the second processor are isolated by the isolation module, and the current and the voltage of the primary side and the secondary side of the transformer are respectively collected, so that mutual interference is avoided, and the reliability of failure detection of the bypass device is improved.
4. In the technical scheme of the invention, when the bypass device is in a failure state, the first processor outputs the alarm signal to alarm so as to inform maintenance personnel to maintain in time and carry out preventive replacement, thereby avoiding the subsequent non-power state of the output capacitor of the boost PFC converter and the generation of overlarge surge current caused by power transmission of input voltage, and further effectively improving the power supply stability and reliability of the server power supply.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without any creative effort.
FIG. 1 is a schematic diagram of an apparatus according to an embodiment of the present invention;
FIG. 2 is a schematic flow diagram of a second method embodiment of the present invention;
fig. 3 is a schematic flow chart of step S3 in the second method according to the embodiment of the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
Example one
As shown in fig. 1, the present invention provides a bypass failure detection apparatus, including: the boost PFC converter comprises an inrush current module 1 comprising a bypass device 11, a boost PFC converter 2, a first processor 3, a second processor 4 and an isolation module 5, wherein the input end of the inrush current module 1 is connected with the output end of alternating current, the output end of the inrush current module 1 is connected with the input end of the boost PFC converter 2, and the first output end of the boost PFC converter 2 is connected with the input end of the first processor 3 and is used for collecting input current and input voltage of the primary side of a transformer in the boost PFC converter 2; a second output end of the boost PFC converter 2 is connected with an input end of the second processor 4 and used for collecting output current and output voltage of a secondary side of a transformer in the boost PFC converter 2; the second processor 4 determines the output power of the boost PFC converter 2 according to the acquired output current and output voltage of the secondary side of the transformer in the boost PFC converter 2; the first processor 3 is connected to the second processor 4 through the isolation module 5, and is configured to obtain the output power of the boost PFC converter 2 determined by the second processor 4 when communicating with the second processor 4, determine a theoretical voltage value of an output capacitor of the boost PFC converter 2 when the bypass device 11 is closed according to the obtained input current, input voltage, output power of the boost PFC converter 2 on the primary side of a transformer in the boost PFC converter 2, and a time period from when the bypass device 11 is opened to when the bypass device 11 is closed, and determine whether the bypass device 11 is in a failure state according to the theoretical voltage value of the output capacitor of the boost PFC converter 2 when the bypass device 11 is closed and the actual voltage value of the output capacitor of the boost PFC converter 2 when the bypass device 11 is closed.
The bypass 11 is connected in parallel with a current limiting resistor inside the surge current module 1, the input end of the surge current module 1 (bypass 11) is connected with the output end of alternating current, the output end of the surge current module 1 is connected with the input end of the boost PFC converter 2, further, the input end of the surge current module 1 (bypass 11) is connected with the output end of an EMI (EMI Power Filter) filtering module 6, and the input end of the EMI filtering module 6 is connected with the output end of alternating current. Specifically, the implementation manner of the EMI filter module 6 may be either an EMI filter or an EMI filter circuit, and those skilled in the art may select the implementation manner according to the actual situation, and the invention is not limited herein.
The boost PFC (Power Factor Correction) converter 2 may be any boost PFC converter circuit, as long as the boost PFC converter circuit includes a transformer and an output capacitor therein, and can implement boost conversion and Power Factor Correction, and the invention is not limited herein.
A first output end of the boost PFC converter 2 is connected with an input end of the first processor 3 and is used for boosting input current and input voltage of a primary side of a transformer in the PFC converter 2; a second output end of the boost PFC converter 2 is connected with an input end of the second processor 4 and is used for boosting the output current and the output voltage of the secondary side of a transformer in the PFC converter 2; the second processor 4 determines the output power of the boost PFC converter 2 according to the acquired output current and output voltage of the secondary side of the transformer in the boost PFC converter 2; the first processor 2 is connected with the second processor 4 through the isolation module 5, and is configured to obtain the output power of the boost PFC converter 2 determined by the second processor 4 when communicating with the second processor 4, specifically, the control enable terminal of the isolation module 5 may be connected with the control enable output terminal of the first processor 3, and when enabled, the first processor 3 communicates with the second processor 4, and isolates an interference signal between the first processor and the second processor when communicating; when the first processor 3 and the second processor 4 are not enabled, the communication is stopped, and when the first processing isolation module 5 is implemented as an MOS transistor, generally, the communication can be implemented as a single MOS transistor, or implemented by connecting a plurality of MOS transistors in parallel with each other. The connection mode of the MOS transistor in the isolation module 5 may be that the gate of the MOS transistor is connected to the control enable terminal of the first processor 3, taking a P-type MOS transistor as an example, the drain of the MOS transistor is connected to the power output terminal of the PSU module 1, the source of the MOS transistor is connected to the input terminal of the second processor 4, the anode of the parasitic diode is connected to the power output terminal of the first processor 2, and the cathode of the parasitic diode is connected to the input terminal of the second processor 4.
In addition, the control output terminal of the first processor 3 is also connected to the control input terminal of the bypass 11 for controlling the opening and closing of the bypass 11.
The first processor 3 determines a theoretical voltage value of an output capacitor (Vbulk) in the boost PFC converter 2 when the bypass 11 is closed according to the input current and the input voltage of the primary side of the transformer in the boost PFC converter 2, the output power of the boost PFC converter 2, and the time period from the bypass 11 being turned on to the bypass 11 being turned off, specifically:
determining the input power of the boost PFC converter 2 according to the acquired input current and input voltage of the primary side of a transformer in the boost PFC converter 2;
determining the efficiency of the boost PFC converter 2 according to the input power of the boost PFC converter 2 and the output power of the boost PFC converter 2; that is, the efficiency of the boost PFC converter 2 is the output power of the boost PFC converter 2/the input power of the boost PFC converter 2.
And determining the theoretical value of the voltage of the output capacitor in the boost PFC converter 2 when the bypass 11 is closed according to the output power of the boost PFC converter 2, the efficiency of the boost PFC converter 2, the output capacitor in the boost PFC converter 2, the voltage of the output capacitor in the boost PFC converter 2 before the bypass 11 is opened and the time period from the closing of the bypass 11 to the closing of the bypass 11.
Specifically, the theoretical voltage value of the output capacitor in the boost PFC converter 2 when the bypass 11 is closed is determined according to the output power of the boost PFC converter 2, the efficiency of the boost PFC converter 2, the output capacitor in the boost PFC converter 2, the voltage of the output capacitor in the boost PFC converter 2 before the bypass 11 is opened, and the time period from the bypass 11 being opened to the bypass 11 being closed, and specifically:
Specifically, the first processor 3 may open the bypass 11 for a fixed time period or according to an input instruction, close the bypass 11 after the bypass 11 is opened for a certain time period (i.e., a time period T from the bypass being opened to the bypass being closed), and perform failure detection on the bypass 11, where a value of the time period T may be a value between 0 and PSU retention time (which refers to a time period from the bypass being opened to the bypass being closed), the PSU retention time is generally at most 12ms, and preferably, the bypass 11 may be closed after being opened for 10ms, and whether the bypass 11 is failed or not is detected, i.e., a voltage value of an output capacitor in the boost PFC converter when the bypass is closed is detected, and a value of the time period T may be as large as possible to increase detection accuracy and reliability.
After the bypass 11 is turned off, since the surge resistor in the surge current module 1 can limit the current entering, it can be calculated that the output capacitor in the boost PFC converter 2 has the normal voltage (i.e. the voltage V of the output capacitor in the boost PFC converter before the bypass is turned on) normal ) Drop to voltage V C (the theoretical value of the voltage of the output capacitor in the boost PFC converter when the time period T has elapsed, i.e. the theoretical value of the voltage of the output capacitor in the boost PFC converter when the bypass is closed).
The first processor 3 determines whether the bypass device 11 is in the failure state according to the theoretical voltage value of the output capacitor in the boost PFC converter 2 when the bypass device 11 is closed and the actual voltage value of the output capacitor in the boost PFC converter 2 when the bypass device 11 is closed, specifically:
comparing the actual voltage value of the output capacitor in the boost PFC converter 2 when the bypass device 11 is closed with a preset voltage threshold value, wherein the preset voltage threshold value is half of the sum of the voltage of the output capacitor in the boost PFC converter 2 before the bypass device 11 is started and the theoretical voltage value of the output capacitor in the boost PFC converter 2 when the bypass device 11 is closed;
if the actual voltage value of the output capacitor in the boost PFC converter 2 when the bypass is closed is smaller than the preset voltage threshold, the bypass 11 is normally opened and closed; if the voltage value of the output capacitor in the boost PFC converter 2 when the bypass 11 is turned off is greater than the preset voltage threshold, the bypass 11 is not normally turned on (and turned off), and is in a failure state, i.e., the bypass 11 is abnormal and cannot normally operate.
Specifically, the preset voltage threshold is half of the sum of the voltage of the output capacitor in the boost PFC converter 2 before the bypass 11 is turned on and the theoretical voltage value of the output capacitor in the boost PFC converter 2 when the bypass 11 is turned off. I.e. the preset voltage threshold
Adjustments may also be made based on system power and the time to shut down the bypass 11, and the invention is not limited herein. The actual voltage value of the output capacitor of the boost PFC converter 2 when the bypass is closed is the measured value of the output capacitor of the boost PFC converter 2 when the bypass is closed.
When the bypass 11 is in the disabled state, the first processor 3 outputs an alarm signal to alarm. Specifically, the status bit can be output from the SMB _ ALERT pin, or the alarm output signal pin can be set by user and the corresponding status bit can be set; when the bypass 11 is in the normal state, a PSU _ Health pin can be used to output the normal state signal and set the corresponding status bit.
When the server detects the output signal of the first processor 3, it can know whether the bypass is in a failure state through PMBus (power management bus) polling, i.e. the bypass is disabled and not normally turned on.
In the technical solution of the present invention, the acquisition of the parameters of the boost PFC converter 2 by the first processor 3 and the second processor 4 is performed simultaneously when the bypass device on-time reaches T, which includes but is not limited to: the input current and the input voltage at the primary side of the transformer in the boost PFC converter 2, the output voltage and the output current at the secondary side of the boost PFC converter 2, the output capacitor in the boost PFC converter 2, the voltage of the output capacitor in the boost PFC converter 2 before the bypass 11 is turned on, the time period from the bypass 11 being turned on to the bypass 11 being turned off, and the like.
On the basis of the existing power supply, the first processor, the second processor and the isolation module are added, failure detection of the bypass device is achieved, the problems that devices on a power supply path of the power supply are damaged due to abnormal short circuit of the bypass device and the machine room end is tripped open and shut are effectively solved, and the stability and the reliability of power supply of the server power supply are effectively improved.
The technical scheme of the invention can detect whether the bypass device connected in parallel with the surge current limiter is invalid or not, and store and feed back the abnormality, thereby avoiding the problem that the server is influenced by the trip of the machine room when the Power supply unit (Power supply unit) in the server is damaged.
In the technical scheme of the invention, the first processor and the second processor are isolated by the isolation module, and the current and the voltage of the primary side and the secondary side of the transformer are respectively collected, so that the mutual interference is avoided, and the reliability of the failure detection of the bypass device is improved.
In the technical scheme of the invention, when the bypass device is in a failure state, the first processor outputs the alarm signal to alarm so as to inform maintenance personnel to maintain in time and carry out preventive replacement, thereby avoiding the subsequent non-power state of the output capacitor of the boost PFC converter and the generation of overlarge surge current caused by power transmission of input voltage, and further effectively improving the power supply stability and reliability of the server power supply.
Example two
As shown in fig. 2, the technical solution of the present invention further provides a bypass device failure detection method, which is implemented based on the bypass device failure detection apparatus of the first embodiment, and includes:
s1, a first processor controls a bypass device to be started, and controls the bypass device to be closed after the bypass device is started for a first time period, so that input voltage and input current of a primary side of a transformer in a boost PFC converter are obtained;
s2, acquiring the output power of the secondary side of a transformer in the boost PFC converter determined by the second processor through an isolation module;
and S3, determining a theoretical voltage value of an output capacitor in the boost PFC converter when a bypass is closed according to the acquired input current, input voltage, output power of the boost PFC converter and a time period from the bypass to the bypass, and judging whether the bypass is in a failure state or not according to the theoretical voltage value of the output capacitor in the boost PFC converter when the bypass is closed and an actual voltage value of the output capacitor in the boost PFC converter when the bypass is closed.
In step S1, the first processor may start the bypass device in a fixed time period or according to an input instruction, the bypass device is turned off after the bypass device is turned on for a certain time period (i.e., a time period T from the bypass device being turned off to the bypass device being turned off), and a bypass device failure detection is performed, where a value of the time period T may be a value between 0 and PSU retention time (which refers to a time period from turning off the bypass device to turning off), the PSU retention time is generally at most 12ms, and preferably, the bypass device may be turned off after being turned on for 10ms, and whether the bypass device is failed or not is detected, i.e., an actual voltage value of an output capacitor in the boost PFC converter when the bypass device is turned off is detected, and the value of the time period T may be as large as possible to increase detection accuracy and reliability.
After the bypass is closed, the surge resistor in the surge current module can limit the current to enter, and the voltage V of the output capacitor in the boost PFC converter can be calculated from the normal voltage (namely the voltage V of the output capacitor in the boost PFC converter before the bypass is opened) normal ) Drop to voltage V C (the theoretical value of the voltage of the output capacitor in the boost PFC converter when the time period T has elapsed, i.e. the theoretical value of the voltage of the output capacitor in the boost PFC converter when the bypass is closed).
In step S2, the first processor is connected to the second processor through the isolation module, and is configured to obtain the output power of the boost PFC converter determined by the second processor when communicating with the second processor, specifically, the control enable end of the isolation module may be connected to the control enable output end of the first processor, and when enabled, implement communication between the first processor and the second processor, and isolate an interference signal between the first processor and the second processor when communicating; when not enabled, the first processor stops communicating with the second processor.
In step S3, as shown in fig. 3, the method specifically includes:
s31, determining the input power of the boost PFC converter according to the acquired input current and input voltage of the primary side of a transformer in the boost PFC converter;
s32, determining the efficiency of the boost PFC converter according to the input power of the boost PFC converter and the output power of the boost PFC converter;
s33, determining a theoretical voltage value of the output capacitor in the boost PFC converter when the bypass is closed according to the output power of the boost PFC converter, the efficiency of the boost PFC converter, the output capacitor in the boost PFC converter, the voltage of the output capacitor in the boost PFC converter before the bypass is opened and the time period from the bypass is closed to the bypass is closed;
s34, judging whether the actual voltage value of the output capacitor in the boost PFC converter when the bypass device is closed is smaller than a preset voltage threshold value, wherein the preset voltage threshold value is half of the sum of the voltage of the output capacitor in the boost PFC converter before the bypass device is started and the theoretical voltage value of the output capacitor in the boost PFC converter when the bypass device is closed; if the judgment result is yes, executing step S35, and if the judgment result is no, executing step S36;
s35, the bypass device is normally opened and closed;
s36, the bypass device is not normally opened and is in a failure state.
In step S33, the specific voltage value of the output capacitor in the boost PFC converter when the bypass is closed is determined according to the output power of the boost PFC converter, the efficiency of the boost PFC converter, the output capacitor in the boost PFC converter, the voltage of the output capacitor in the boost PFC converter before the bypass is turned on, and the time period from the bypass is turned off to the bypass is:
In steps S31 to S36, specifically, the preset voltage threshold is half of the sum of the voltage of the output capacitor in the boost PFC converter before the bypass is turned on and the theoretical value of the voltage of the output capacitor in the boost PFC converter when the bypass is turned off. I.e. the preset voltage threshold
And may be adjusted based on system power and the time to turn off the bypass, as the invention is not limited herein.
When the bypass device is in a failure state, the first processor outputs an alarm signal to alarm. Specifically, the status bit can be output from the SMB _ ALERT pin, or the alarm output signal pin can be set by user-defined and the corresponding status bit can be set; when the bypass is in normal state, a PSU _ Health pin can be used to output the normal state signal and set the corresponding state bit.
When the server detects the output signal of the first processor, it can know whether the bypass is in failure state, i.e. the bypass is short-circuited, by polling through PMBus (power management bus).
It should be noted that, in the technical solution of the present invention, the acquisition of the parameters of the boost PFC converter by the first processor and the second processor is performed simultaneously when the bypass is turned on for a time T, which includes but is not limited to: the boost PFC converter comprises an input current and an input voltage of a primary side of a transformer in the boost PFC converter, an output voltage and an output current of a secondary side of the boost PFC converter, an output capacitor in the boost PFC converter, a voltage of the output capacitor in the boost PFC converter before a bypass device is started, a time period from the bypass device to the bypass device is started to be closed and the like.
The invention effectively solves the problems of device damage on a power supply path of the power supply and tripping of the machine room end during air opening caused by abnormal short circuit of the bypass device, and effectively improves the stability and reliability of power supply of the server power supply.
The technical scheme of the invention can detect whether the bypass device connected in parallel with the surge current limiter is invalid or not, and store and feed back the abnormality, thereby avoiding the problem that the server is influenced by the trip of the machine room when the Power supply unit (Power supply unit) in the server is damaged.
In the technical scheme of the invention, the first processor and the second processor are isolated by the isolation module, and the current and the voltage of the primary side and the secondary side of the transformer are respectively collected, so that the mutual interference is avoided, and the reliability of the failure detection of the bypass device is improved.
According to the technical scheme, when the bypass device is in the failure state, the first processor outputs the alarm signal to alarm so as to inform maintenance personnel of maintenance in time for preventive replacement, and the phenomenon that the boost PFC converter outputs an electricity-free state of the capacitor and generates overlarge surge current after input voltage power transmission can be avoided, so that the power supply stability and reliability of the server power supply are effectively improved.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.
Claims (8)
1. A bypass failure detection device, comprising: the boost PFC converter comprises an inrush current module comprising a bypass device, a boost PFC converter, a first processor, a second processor and an isolation module, wherein the input end of the inrush current module is connected with the output end of alternating current, the output end of the inrush current module is connected with the input end of the boost PFC converter, and the first output end of the boost PFC converter is connected with the input end of the first processor; the second output end of the boost PFC converter is connected with the input end of the second processor; the second processor determines the output power of the boost PFC converter according to the acquired output current and output voltage of the secondary side of the transformer in the boost PFC converter; the first processor is connected with the second processor through an isolation module and used for obtaining the output power of the boost PFC converter determined by the second processor when the first processor communicates with the second processor, determining a voltage theoretical value of an output capacitor in the boost PFC converter when a bypass is closed according to the obtained input current and input voltage of the primary side of a transformer in the boost PFC converter, the output power of the boost PFC converter and the time period from the bypass opening to the bypass closing, and judging whether the bypass is in a failure state or not according to the voltage theoretical value of the output capacitor in the boost PFC converter when the bypass is closed and the voltage actual value of the output capacitor in the boost PFC converter when the bypass is closed; the method comprises the following steps of determining a theoretical voltage value of an output capacitor in the boost PFC converter when a bypass device is closed according to the acquired input current, input voltage, output power of the boost PFC converter and a time period from the bypass device to the bypass device, wherein the theoretical voltage value is specifically as follows:
determining the input power of the boost PFC converter according to the acquired input current and input voltage of the primary side of a transformer in the boost PFC converter;
determining the efficiency of the boost PFC converter according to the input power of the boost PFC converter and the output power of the boost PFC converter;
and determining a voltage theoretical value of the output capacitor in the boost PFC converter when the bypass is closed according to the output power of the boost PFC converter, the efficiency of the boost PFC converter, the output capacitor in the boost PFC converter, the voltage of the output capacitor in the boost PFC converter before the bypass is opened and the time period from the bypass opening to the bypass closing.
2. The bypass failure detection device according to claim 1, wherein the determination of the theoretical voltage value of the output capacitor of the boost PFC converter during the bypass failure detection according to the output power of the boost PFC converter, the efficiency of the boost PFC converter, the output capacitor of the boost PFC converter, the voltage of the output capacitor of the boost PFC converter before the bypass is turned on, and the time period from the bypass is turned on to the bypass is specifically:
3. The bypass device failure detection device according to claim 1, wherein the step of determining whether the bypass device is in the failure state according to the theoretical voltage value of the output capacitor in the boost PFC converter when the bypass device is closed and the actual voltage value of the output capacitor in the boost PFC converter when the bypass device is closed is specifically as follows:
comparing the actual voltage value of an output capacitor in the boost PFC converter when the bypass device is closed with a preset voltage threshold value, wherein the preset voltage threshold value is half of the sum of the voltage of the output capacitor in the boost PFC converter before the bypass device is started and the theoretical voltage value of the output capacitor in the boost PFC converter when the bypass device is closed;
if the actual voltage value of an output capacitor in the boost PFC converter when the bypass device is closed is smaller than a preset voltage threshold value, the bypass device is normally opened and closed; if the voltage value of the output capacitor in the boost PFC converter when the bypass device is closed is larger than the preset voltage threshold value, the bypass device is not normally started and is in a failure state.
4. The bypass failure detection device according to claim 3, wherein the first processor outputs an alarm signal to perform an alarm when the bypass is in the failure state.
5. The bypass failure detection device according to any one of claims 1 to 4, wherein the isolation module is a MOS transistor.
6. A bypass failure detection method implemented on the basis of the bypass failure detection apparatus according to any one of claims 1 to 5, comprising:
the first processor controls the bypass device to be started, and controls the bypass device to be closed after the bypass device is started for a first time period, so that input voltage and input current of a primary side of a transformer in the boost PFC converter are obtained;
acquiring output power of a secondary side of a transformer in the boost PFC converter determined by the second processor through an isolation module;
determining a theoretical voltage value of an output capacitor in the boost PFC converter when a bypass device is closed according to the acquired input current and input voltage of the primary side of a transformer in the boost PFC converter, the output power of the boost PFC converter and the time period from the bypass device to be closed, and judging whether the bypass device is in a failure state or not according to the theoretical voltage value of the output capacitor in the boost PFC converter when the bypass device is closed and the actual voltage value of the output capacitor in the boost PFC converter when the bypass device is closed; specifically, determining a theoretical voltage value of an output capacitor in the boost PFC converter when a bypass is closed according to the acquired input current and input voltage of the primary side of a transformer in the boost PFC converter, the output power of the boost PFC converter and the time period from the bypass to the bypass, wherein the theoretical voltage value is as follows:
determining the input power of the boost PFC converter according to the acquired input current and input voltage of the primary side of a transformer in the boost PFC converter;
determining the efficiency of the boost PFC converter according to the input power of the boost PFC converter and the output power of the boost PFC converter;
and determining a voltage theoretical value of the output capacitor in the boost PFC converter when the bypass is closed according to the output power of the boost PFC converter, the efficiency of the boost PFC converter, the output capacitor in the boost PFC converter, the voltage of the output capacitor in the boost PFC converter before the bypass is opened and the time period from the bypass opening to the bypass closing.
7. The bypass failure detection method according to claim 6, wherein the determination of the theoretical voltage value of the output capacitor of the boost PFC converter when the bypass is closed according to the output power of the boost PFC converter, the efficiency of the boost PFC converter, the output capacitor of the boost PFC converter, the voltage of the output capacitor of the boost PFC converter before the bypass is opened, and the time period from the bypass being opened to the bypass being closed is specifically:
8. The bypass failure detection method according to claim 6, wherein the step of judging whether the bypass is in the failure state according to the theoretical voltage value of the output capacitor in the boost PFC converter when the bypass is closed and the actual voltage value of the output capacitor in the boost PFC converter when the bypass is closed is specifically as follows:
comparing the actual voltage value of an output capacitor in the boost PFC converter when the bypass device is closed with a preset voltage threshold value, wherein the preset voltage threshold value is half of the sum of the voltage of the output capacitor in the boost PFC converter before the bypass device is started and the theoretical voltage value of the output capacitor in the boost PFC converter when the bypass device is closed;
if the actual voltage value of an output capacitor in the boost PFC converter when the bypass device is closed is smaller than a preset voltage threshold value, the bypass device is normally opened and closed; if the voltage value of the output capacitor in the boost PFC converter when the bypass device is closed is larger than the preset voltage threshold value, the bypass device is not normally started and is in a failure state.
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| US7095215B2 (en) * | 2004-06-04 | 2006-08-22 | Astec International Limited | Real-time voltage detection and protection circuit for PFC boost converters |
| JP5563425B2 (en) * | 2010-10-21 | 2014-07-30 | 富士通テレコムネットワークス株式会社 | Power supply |
| JP6213183B2 (en) * | 2013-11-21 | 2017-10-18 | 富士電機株式会社 | Switching power supply circuit |
| CN104820183B (en) * | 2015-05-15 | 2018-08-03 | 阳光电源股份有限公司 | The on off state detection method and device of relay are bypassed in boost chopper |
| TWI641206B (en) * | 2016-05-23 | 2018-11-11 | 立錡科技股份有限公司 | Power converter and secondary side controller and short circuit determination method for current sensing resistor of the power converter |
| US10272785B2 (en) * | 2017-01-31 | 2019-04-30 | Ford Global Technologies, Llc | Fault detection of a bypass diode in a variable voltage convert system |
| CN107121611B (en) * | 2017-06-27 | 2020-04-28 | 南京理工大学 | Method for monitoring failure of output capacitor of DCM Boost PFC converter |
| CN111446851B (en) * | 2020-04-22 | 2023-03-31 | 深圳华德电子有限公司 | Power input surge current suppression circuit with power factor correction module |
| CN111446852B (en) * | 2020-04-22 | 2023-03-31 | 深圳华德电子有限公司 | Switching power supply and control method thereof |
| CN111983302B (en) * | 2020-08-07 | 2022-05-13 | 苏州浪潮智能科技有限公司 | Power correction circuit abnormality detection method, system and circuit |
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