CN113612944A - Infrared detector video analog signal acquisition processing method and system - Google Patents
Infrared detector video analog signal acquisition processing method and system Download PDFInfo
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
- H04N25/44—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/20—Circuitry for controlling amplitude response
- H04N5/202—Gamma control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
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- H04N5/213—Circuitry for suppressing or minimising impulsive noise
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/30—Transforming light or analogous information into electric information
- H04N5/33—Transforming infrared radiation
Abstract
The invention relates to a method and a system for acquiring and processing video analog signals of an infrared detector. The problem that the output pixel rate of the detector and ADC sampling are not in batch matching is solved. The invention carries out analog-to-digital conversion aiming at the video analog signal output by the low pixel rate detector, adopts an ADC (analog-to-digital converter) with the sampling rate being 2 times or several times of the pixel reading rate, and adds the digital signals of a flat area with stable multi-sampling positions and small image relative gray level fluctuation by carrying out multi-sampling (related to the ratio of the sampling rate of the ADC and the pixel output frequency of the infrared detector) on the same pixel to obtain an average signal as an effective quantization value of the pixel. The problem that the output pixel rate of the detector and the sampling rate of the ADC are not in batch is well solved, the high-performance ADC can be used in an image system with a low pixel rate, and the image quality is effectively improved.
Description
Technical Field
The invention belongs to a using method of an ADC (analog to digital converter) device of a video, and relates to a method and a system for acquiring and processing video analog signals of an infrared detector.
Background
With the progress and development of industrial technologies, machine vision imaging has been widely applied to various fields such as industrial production, road monitoring and security, and besides, machine vision is also widely applied to various fields such as aerospace, military reconnaissance and scientific research, and the range of the working spectrum thereof is expanded from the visible light band to the fields such as ultraviolet and infrared along with different application fields and different requirements, wherein especially visible light imaging equipment is the most common and the most well known, such as a mobile phone camera. In recent years, however, infrared imaging systems have been developed dramatically in some fields due to the particularity of infrared images.
The factors influencing the image quality of the imaging system include the optical-mechanical system, the performance of the detector, analog-digital conversion and other components. For the image quality, one of the important assessment indexes is that the signal-to-noise ratio is required to be high, the signal-to-noise ratio refers to the ratio of an effective image signal to noise, and theoretically, the larger the ratio is, the lower the acquired image noise is, the higher the image signal is, and thus, the better the image definition and the contrast are. The signal-to-noise ratio is higher in some special scientific researches and remote sensing imaging. Taking remote sensing imaging as an example, in recent years, with the continuous development of the optical remote sensing field, the requirement for high-resolution imaging is higher and higher, and the high resolution not only provides higher requirements for an optical mechanical system, but also provides challenges for a detector and a digitized image.
Currently, the pixel clock of the infrared detector is relatively low, usually only several mega or ten-mega hertz, and the sampling frequency of the ADC devices on the market is generally high, and sometimes even up to several tens of mega-hertz. There will be situations where the detector output pixel rate is not in batch with the ADC samples.
Disclosure of Invention
The invention aims to provide a method and a system for acquiring video analog signals of an infrared detector, which solve the problem that the output pixel rate of the detector and ADC sampling are not in batch. The invention utilizes the ADC device with high sampling rate to carry out low pixel acquisition, not only can improve the signal-to-noise ratio, but also does not increase extra hardware resources.
The conception of the invention is as follows:
the invention carries out analog-to-digital conversion aiming at the video analog signal output by the low pixel rate detector, adopts an ADC (analog-to-digital converter) with the sampling rate being 2 times or several times of the pixel reading rate, and adds the digital signals of a flat area with stable multi-sampling positions and small image relative gray level fluctuation by carrying out multi-sampling (related to the ratio of the sampling rate of the ADC and the pixel output frequency of the infrared detector) on the same pixel to obtain an average signal as an effective quantization value of the pixel. The method can ensure that some high-performance ADCs are used in an image system with a low pixel rate, and effectively improve the image quality.
The technical scheme of the invention is to provide a video analog signal acquisition and processing method of an infrared detector, which is characterized by comprising the following steps:
step 1, constructing an infrared detector video analog signal acquisition and processing system;
the infrared detector video analog signal acquisition and processing system mainly comprises an ADC (analog-to-digital converter), an FPGA (field programmable gate array) data processing unit, a clock unit, a storage unit, a power supply and distribution unit and a data output unit;
the input end of the ADC is electrically connected with the video analog signal output end of the infrared detector, the FPGA data processing unit is electrically connected with the ADC, and the input end of the data output unit is electrically connected with the signal output end of the FPGA data processing unit; the clock unit and the storage unit are electrically connected with the FPGA data processing unit;
step 2, configuring a working clock;
configuring a proper pixel reading clock xMHz for the infrared detector through the FPGA data processing unit, and simultaneously providing a sampling clock yMHz for the ADC, so that y is equal to nx, and n is equal to or larger than 2;
step 3, adjusting the sampling position of the ADC;
adjusting the sampling position of the ADC to ensure that each sampling point is in the effective pixel interval of the video analog signal;
step 4, sampling and digital domain processing;
step 4.1, the ADC collects video analog signals output by the infrared detector according to a set sampling clock, and converts the video analog signals into digital signals, and because the sampling clock of the ADC is n times of the pixel reading clock of the infrared detector, n times of sampling can be realized on the same pixel video analog signals under one sampling clock, and n groups of digital signals corresponding to the pixel video analog signals are obtained;
step 4.2, the FPGA data processing unit performs digital domain processing on the digital signals, m groups of digital signals in the n groups of digital signals are selected, the average value of the m groups of digital signals is obtained, and the average value is used as an effective quantization value of the pixel and is generally called as a gray value; wherein m is less than or equal to n;
step 5, repeating the step 4, completing sampling and digital domain processing of all pixel video analog signals output by the infrared detector, and obtaining all pixel gray values;
and 6, the FPGA data processing unit enables all the pixel points to form an image frame, and the recombined data is sent to the data output unit for output.
Further, step 3 specifically comprises:
the video analog signal output by the infrared detector is connected with an infrared detector video analog signal acquisition system, after the system is powered on, the sampling point position of the ADC is tested in a laboratory, the relative position relation between the sampling point and the infrared detector video analog signal is checked through an oscilloscope, parameters are adjusted repeatedly for many times, and each sampling point is ensured to be in an effective pixel interval of the video analog signal.
In order to further improve the signal-to-noise ratio, in step 4.2, the m groups of digital signals have relatively stable sampling positions and relatively small image fluctuation compared with the rest n-m groups of signals.
The invention also provides a video analog signal acquisition and processing system of the infrared detector, which is characterized by comprising an ADC (analog-to-digital converter), an FPGA (field programmable gate array) data processing unit, a clock unit, a storage unit, a power supply and distribution unit and a data output unit;
the input end of the ADC is electrically connected with the video analog signal output end of the infrared detector; the FPGA data processing unit is electrically connected with the ADC; the input end of the data output unit is electrically connected with the signal output end of the FPGA data processing unit; the clock unit and the storage unit are electrically connected with the FPGA data processing unit;
the FPGA data processing unit is used for configuring a proper pixel reading clock for the infrared detector and providing a sampling clock for the ADC; meanwhile, digital domain processing is realized, and m groups of digital signals output by the ADC are selected for each pixel to perform averaging operation; all the pixel points which are processed in the digital domain form an image frame, and the recombined data is sent to a data output unit for output;
the ADC is used for collecting a video analog signal output by the infrared detector according to a set sampling clock and converting the video analog signal into a digital signal; the sampling clock of the ADC is yMHz, y is nx, n is more than or equal to 2, n is more than or equal to m, and x is the pixel reading clock xMHz of the infrared detector;
the clock unit is used for providing a working clock;
the storage unit is used for providing code storage for the FPGA data processing unit, so that the system can normally run after being powered up again each time;
the power supply and distribution unit is used for providing power for the whole system;
and the data output unit is used for outputting the data recombined by the FPGA data processing unit.
Furthermore, the infrared detector is a medium wave infrared detector, the resolution ratio is 640 multiplied by 512, the maximum pixel rate is 8MHz, and 4 paths of video analog signals are output simultaneously.
Further, the ADC is ADDI7004, and the sampling clock of the ADC is 16 MHz.
Furthermore, the FPGA data processing unit selects the FPGA model of Xilinx corporation as XC4VSX55-10FF 1148I.
Further, the memory unit uses the Xilinx corporation specific FLASH configuration chip XCF 32P.
Further, the clock unit selects a crystal vibrator of 100 MHz.
Furthermore, the power supply and distribution unit adopts a low-dropout voltage-stabilized power supply device.
The invention has the beneficial effects that:
1. according to the invention, on the premise of not changing the infrared detector and the ADC, the same pixel is sampled for multiple times, and the digital signals of a flat area with stable sampling positions and small image relative gray level fluctuation are added to calculate and average the digital signals as the gray value of the pixel, so that the problem that the output pixel rate of the detector and the ADC sampling rate are not in batch is well solved, and the high-performance ADC can be used in an image system with a low pixel rate.
2. The high-sampling ADC analog-to-digital converter provided by the invention is used for collecting the infrared detector analog signal with low pixel rate, and the gray value of the point is obtained by averaging through multiple times of sampling. Usually, a lot of random noise is superposed even in a flat region output by the detector, and the sampling method can greatly improve the signal-to-noise ratio and acquire high-performance images. The same pixel is sampled and averaged for m times by using the high sampling frequency of AD to serve as an output gray value, and after m times of sampling and filtering are carried out theoretically, the signal-to-noise ratio can be improved
And (4) doubling.
3. The method provided by the invention has the advantages of convenience, simplicity, effectiveness and the like. With the popularization of infrared vision, the solution has wide application prospect.
Drawings
FIG. 1 is a block diagram of a video analog signal processing system of an infrared detector according to the present invention;
fig. 2 is a schematic diagram of the method for processing the video analog signal of the infrared detector according to the present invention, wherein multiple sampling is performed on the same pixel.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below, and it is apparent that the described embodiments are a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making creative efforts based on the embodiments of the present invention, shall fall within the protection scope of the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
Furthermore, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
As shown in fig. 1, the video analog signal acquisition and processing system of the infrared detector in this embodiment mainly includes an ADC analog-to-digital converter, an FPGA data processing unit, a FLASH memory unit, a clock unit, a data output unit, and a power supply and distribution unit, and is connected to an analog video signal output end of an external infrared detector through the ADC analog-to-digital converter. The FPGA data processing unit is electrically connected with the ADC; the input end of the data output unit is electrically connected with the signal output end of the FPGA data processing unit; the clock unit and the storage unit are electrically connected with the FPGA data processing unit.
The infrared detector mainly provides analog video signals for the ADC, and the output pixel rate can be configured by the FPGA data processing unit. In this embodiment, a medium wave infrared detector produced by the medium power system 11 is selected, the resolution is 640 × 512, the maximum pixel rate is 8MHz, and 4 analog signals can be simultaneously output.
The ADC is mainly used to digitize analog video signals, and in this embodiment, a high-performance ADDI7004 chip of TI corporation is selected. The single chip of the device can realize the digitization of 4 paths of video analog signals, greatly saves the circuit scale and has lower sampling noise. The device has the characteristics of high speed, small volume and low power consumption. The sampling rate is 10-72 MHz, and the quantization bit number is 14 bits. Because the output rate of the infrared detector is 8MHz, and the minimum sampling rate of the selected ADC is 10MHz, the sampling rate of the ADC is 16MHz and is 2 times of the output pixel clock of the infrared detector, and the gray values sampled for 2 times are added and averaged to be used as the gray value of the pixel point. The user may use a sampling rate of 3 times, 4 times or more according to actual needs.
The FPGA data processing unit provides configuration parameters for the infrared detector and the ADC, configures a proper pixel reading clock for the infrared detector, and provides a sampling clock for the ADC; in this embodiment, as described above, the pixel readout clock of the infrared detector is configured to be 8MHz, and the sampling clock of the ADC analog-to-digital converter is configured to be 16 MHz. And simultaneously, carrying out digital and processing on digital signals output by the ADC, summing and averaging the digital signals output by the ADC, forming all pixel points subjected to digital domain processing into image frames, and sending the recombined data to a data output unit for output. In the embodiment, the FPGA model of Xilinx corporation is XC4VSX55-10FF1148I, pixel operation and image processing are completed through an internal logic unit, and parallel 14-bit pixel data are framed, so that an internal storage unit can cache according to actual frames and lines of a detector.
The FLASH storage unit provides code storage for the FPGA data processing unit, so that the system can normally operate after being powered on again each time. The FLASH memory unit is a nonvolatile, electrically erasable and programmable read-only memory. In this embodiment, the Xilinx corporation specific FLASH configuration chip XCF32P was used.
The clock unit provides an operating clock for the whole system, and a crystal vibrator of 100MHz is selected in the embodiment.
The power supply and distribution unit provides power for the whole system, and the embodiment adopts a low-dropout voltage-stabilized power supply device.
The embodiment specifically realizes the acquisition and processing of the video analog signal of the infrared detector through the following processes:
step 1, constructing the video analog signal acquisition and processing system of the infrared detector.
Step 2, configuring a working clock;
after the hardware environment is built, configuring a proper pixel reading clock xMHz for the infrared detector through the FPGA data processing unit, and simultaneously providing a sampling clock yMHz for the ADC, so that y is equal to nx, and n is more than or equal to 2; in this embodiment, the pixel readout clock of the infrared detector is configured to be 8MHz, and the sampling clock of the ADC analog-to-digital converter is configured to be 16 MHz.
Step 3, adjusting the sampling position of the ADC;
after the parameters of the infrared detector and the ADC are configured, the sampling position of the ADC is finely adjusted through laboratory tests, and each sampling point is ensured to be in an effective pixel interval and cannot deviate from a video analog signal interval actually output by the infrared detector.
The method can be realized by the following steps: the analog video signal output end of the infrared detector is connected with the ADC, after the system is powered on, the sampling point position of the ADC is tested in a laboratory, the relative position relation between the sampling point and the analog signal of the infrared detector is checked through an oscilloscope, parameters are adjusted repeatedly for many times, and the optimal sampling position is obtained. After the sampling points are confirmed, normal imaging tests can be carried out, laboratory tests can be carried out according to requirements, and development can be completed.
Step 4, sampling and digital domain processing;
step 4.1, the ADC collects video analog signals output by the infrared detector according to a set sampling clock, and converts the video analog signals into digital signals, where y is nx in the above formula, so that the same pixel video analog signal can be sampled n times under one sampling clock, and n groups of digital signals corresponding to the pixel video analog signal are obtained, as shown in fig. 2;
step 4.2, the FPGA data processing unit performs digital domain processing on the digital signals, can select m groups of digital signals in the n groups of digital signals according to requirements, and calculates the average value of the m groups of digital signals, and takes the average value as an effective quantization value of the pixel, which is generally called as a gray value; wherein m is less than or equal to n. Compared with the rest n-m groups of signals, the m groups of digital signals have stable sampling positions and smaller image relative gray level fluctuation.
Step 5, repeating the step 4, completing sampling and digital domain processing of all pixel video analog signals output by the infrared detector, and obtaining all pixel gray values;
and 6, the FPGA data processing unit enables all the pixel points to form an image frame, and the recombined data is sent to the data output unit to be output, namely, a complete image analog-to-digital conversion is obtained.
Claims (10)
1. A video analog signal acquisition and processing method of an infrared detector is characterized by comprising the following steps:
step 1, constructing an infrared detector video analog signal acquisition and processing system;
the infrared detector video analog signal acquisition and processing system comprises an ADC (analog-to-digital converter), an FPGA (field programmable gate array) data processing unit, a clock unit, a storage unit, a power supply and distribution unit and a data output unit;
the input end of the ADC is electrically connected with the video analog signal output end of the infrared detector, the FPGA data processing unit is electrically connected with the ADC, and the input end of the data output unit is electrically connected with the signal output end of the FPGA data processing unit; the clock unit and the storage unit are electrically connected with the FPGA data processing unit;
step 2, configuring a working clock;
configuring a proper pixel reading clock xMHz for the infrared detector through the FPGA data processing unit, and simultaneously providing a sampling clock yMHz for the ADC, so that y is equal to nx, and n is equal to or larger than 2;
step 3, adjusting the sampling position of the ADC;
adjusting the sampling position of the ADC to ensure that each sampling point is in the effective pixel interval of the video analog signal;
step 4, sampling and digital domain processing;
step 4.1, the ADC collects video analog signals output by the infrared detector according to a set sampling clock, converts the video analog signals into digital signals, can realize n-time sampling on the same pixel video analog signals under one sampling clock, and obtains n groups of digital signals corresponding to the pixel video analog signals;
step 4.2, the FPGA data processing unit carries out digital domain processing on the digital signals, m groups of digital signals in the n groups of digital signals are selected, the average value of the m groups of digital signals is obtained, and the average value is used as the gray value of the pixel; wherein m is less than or equal to n;
step 5, repeating the step 4, completing sampling and digital domain processing of all pixel video analog signals output by the infrared detector, and obtaining all pixel gray values;
and 6, the FPGA data processing unit enables all the pixel points to form an image frame, and the recombined data is sent to the data output unit for output.
2. The method for acquiring and processing the video analog signal of the infrared detector according to claim 1, wherein the step 3 is specifically as follows:
the video analog signal output by the infrared detector is connected with an infrared detector video analog signal acquisition system, after the system is powered on, the sampling point position of the ADC is tested in a laboratory, the relative position relation between the sampling point and the infrared detector video analog signal is checked through an oscilloscope, parameters are adjusted repeatedly for many times, and each sampling point is ensured to be in an effective pixel interval of the video analog signal.
3. The method for acquiring and processing the video analog signals of the infrared detector as claimed in claim 1, wherein in step 4.2, the m groups of digital signals have relatively stable sampling positions and relatively small image gray level fluctuation compared with the rest n-m groups of signals.
4. The utility model provides an infrared detector video analog signal gathers processing system which characterized in that: the device comprises an ADC (analog-to-digital converter), an FPGA (field programmable gate array) data processing unit, a clock unit, a storage unit, a power supply and distribution unit and a data output unit;
the input end of the ADC is electrically connected with the video analog signal output end of the infrared detector; the FPGA data processing unit is electrically connected with the ADC; the input end of the data output unit is electrically connected with the signal output end of the FPGA data processing unit; the clock unit and the storage unit are electrically connected with the FPGA data processing unit;
the FPGA data processing unit is used for configuring a proper pixel reading clock for the infrared detector and providing a sampling clock for the ADC; meanwhile, digital domain processing is realized, and m groups of digital signals output by the ADC are selected for each pixel to perform averaging operation; all the pixel points which are processed in the digital domain form an image frame, and the recombined data is sent to a data output unit for output;
the ADC is used for collecting a video analog signal output by the infrared detector according to a set sampling clock and converting the video analog signal into a digital signal; the sampling clock of the ADC is yMHz, y is nx, n is more than or equal to 2, n is more than or equal to m, and x is the pixel reading clock xMHz of the infrared detector;
the clock unit is used for providing a working clock;
the storage unit is used for providing code storage for the FPGA data processing unit, so that the system can normally run after being powered up again each time;
the power supply and distribution unit is used for providing power for the whole system;
and the data output unit is used for outputting the data recombined by the FPGA data processing unit.
5. The infrared detector video analog signal acquisition processing system according to claim 4, characterized in that: the infrared detector is a medium wave infrared detector, the resolution ratio is 640 multiplied by 512, the maximum pixel rate is 8MHz, and 4 paths of video analog signals are output simultaneously.
6. The infrared detector video analog signal acquisition processing system according to claim 5, characterized in that: the ADC is ADDI7004, and the sampling clock of the ADC is 16 MHz.
7. The infrared detector video analog signal acquisition processing system according to claim 6, characterized in that: the FPGA data processing unit is XC4VSX55-10FF 1148I.
8. The infrared detector video analog signal acquisition processing system according to claim 7, characterized in that: the memory unit is used for configuring a chip XCF32P for a FLASH dedicated to Xilinx corporation.
9. The infrared detector video analog signal acquisition processing system according to claim 8, characterized in that: the clock unit is a crystal vibrator of 100 MHz.
10. The infrared detector video analog signal acquisition processing system according to claim 9, characterized in that: the power supply and distribution unit adopts a low-dropout voltage-stabilized power supply device.
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