CN103957365A - CMOS image sensor structure for realizing predictive coding image compression - Google Patents
CMOS image sensor structure for realizing predictive coding image compression Download PDFInfo
- Publication number
- CN103957365A CN103957365A CN201410137993.7A CN201410137993A CN103957365A CN 103957365 A CN103957365 A CN 103957365A CN 201410137993 A CN201410137993 A CN 201410137993A CN 103957365 A CN103957365 A CN 103957365A
- Authority
- CN
- China
- Prior art keywords
- circuit
- predictive coding
- value
- image sensor
- sensor structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The invention relates to the integrated circuit design field of microelectronics and the digital image coding compression field. According to the technical scheme, a CMOS image sensor structure for realizing predictive coding image compression is used for achieving the purposes that on the basis of no reduction of image sensing quality, the area and power consumption introduced in due to a predictive coding module which is additionally used are reduced, predictive coding is completed while an image is acquired, and disorder caused by an operational amplifier in the coding process is eliminated. The CMOS image sensor structure is characterized in that firstly, a pixel value read from a pixel array is transmitted to a correlated double-sampling circuit to be subjected to correlated double-sampling so that fixed-pattern noise can be eliminated, then, a predictive coding circuit carries out predicted value obtaining operation under control of a sequential circuit, a column-level subtracter is used for obtaining the difference, namely a residual value, between the predicted value and an original pixel value after the predicted value is obtained, and finally, the residual value is subjected to analog-digital conversion to obtain final output codes. The CMOS image sensor structure for realizing predictive coding image compression is mainly applied to integrated circuit design.
Description
Technical field
The present invention relates to microelectronic integrated circuit (IC) design field and digital image coding compression field, particularly a kind of for realizing the cmos image sensor structure of predictive coding.
Technical background
The video signal collective processing procedure of tradition based on cmos image sensor need to quantize whole pixel values, is transferred to chip and compresses processing in addition, and the data after compression can store or transmit.Be not difficult to find, the end of reading of cmos image sensor all reads total data, in compression process subsequently, again mass of redundancy data is given up, and whole image compression process has been done a large amount of idle works, makes treatment effeciency low.If can, in the data after end directly obtains compression of reading of cmos image sensor, redundant data can be eliminated on source, particularly along with the continuous increase of pel array scale, need data volume to be processed constantly to surge, on such sheet, compression step seems more meaningful, and the development of CMOS technique provides possibility for compatible image compression function on sheet.
Because image compression function is integrated on mobile device more, so the area of chip and power consumption have all been proposed to many restrictions.This makes not all compression algorithm all be applicable to compress on sheet, classical image compression algorithm has block matrix conversion, wavelet transformation and predictive coding etc., first two method needs the operation of the more complicated such as vectorial sum of products adds up, often need to realize with DSP, its hardware consumption is huge, and the advantage that it brings aspect image compression can be offset by its excessive power consumption and area.What predictive coding will easily realize comparatively speaking is many, and it only need to utilize the pixel of current pixel periphery to predict its value, and predicted value and current pixel value are subtracted each other to generation residual value just can complete predictive coding.In addition, the method for compressing image such as 2D-DCT and wavelet transformation is all Image Lossy Compression, in some field, and such as medical treatment, space flight etc., the image that damages is like this can not be received, and predictive coding has unrivaled advantage as a kind of Lossless Image Compression method.Existing focal plane compression method mostly is block matrix transformation approach, and this needs a large amount of switched-capacitor circuits and huge capacitor array, and this not only can make the shortcoming of the low precision of analog circuit be exaggerated, and is also difficult to meet the requirement of area.
Summary of the invention
For overcoming the deficiencies in the prior art, a kind of novel cmos image sensor structure that can realize predictive-coded picture compression is proposed.Compare with conventional process flow, do not reducing on the basis of image sensing quality, reduce area and the power consumption due to the extra predictive coding module of using (as DSP or for the ASIC circuit of predictive coding conversion), introduced.In image acquisition, complete predictive coding, and eliminate the imbalance being brought by operational amplifier in the process of coding.For this reason, the technical scheme that the present invention takes is, for realizing the cmos image sensor structure of predictive-coded picture compression, be specially, first the pixel value of reading from pel array is sent to correlated-double-sampling (correlated double sample, CDS) in circuit, carry out correlated-double-sampling to eliminate fixed pattern noise, next predictive coding circuit will carry out the operation of asking for of predicted value under the control of sequence circuit, try to achieve after predicted value and will utilize row level subtracter to try to achieve poor between predicted value and original pixel value, it is residual value, finally residual value is carried out to analog-to-digital conversion (AD) and just obtained final output encoder,
Predictive coding circuit be take 2 * 2 block of pixels and is carried out as unit, every two pixel two row share a predictive coding circuit, 2 * 2 block of pixels is sent in predictive coding circuit in accordance with the order from top to bottom successively, predictive coding circuit is combined by integrating circuit and memory circuit two parts, wherein integrating circuit is for averaged, i.e. predicted value; Memory circuit is for the pixel value with the unit's of classifying as storage 2 * 2 block of pixels; Row level subtracter is for asking difference operation in the hope of residual value to pixel value and predicted value.
Integrating circuit is by two sampling capacitance C that are connected respectively to two pixel columns
s, amplifier, sampling capacitance C
shomophase input control switch, sampling capacitance C
santi-phase input control switch, amplifier feedback capacity C
c, amplifier feedback capacity C
ccontrol switch, amplifier feedback switch, reference point position are to amplifier feedback capacity C
cbetween switch form.
Memory circuit consists of two sampling capacitances, amplifier, sampling capacitance anti-phase input control switch, amplifier feedback capacity control switch, the amplifier feedback switch that are connected respectively to two pixel columns.
Technical characterstic of the present invention and effect:
The invention provides a kind of cmos image sensor structure that can realize predictive-coded picture compression.Among predictive coding is dissolved into the intrinsic handling process of cmos image sensor, complete Lossless Image Compression, there is the incomparable advantages of Image Lossy Compression such as block matrix conversion.Utilize analog circuit to complete the predictive coding work that in the past can only complete with DSP or complicated ASIC circuit, there is low-power consumption and low area that analog circuit is intrinsic.Predictive coding is carried out in 2 * 2 block of pixels, and four pixel values are averaging and can obtain predicted value, and algorithm is simply easy to hardware and realizes, and the error of bringing due to predictive coding can not added up.When asking predicted value, also completed the work of eliminating operational amplifier offset.Output data can be carried out any coding, have improved imageing sensor efficiency, are applicable to the fields such as wireless sensing, video monitoring, biologic medical.
Accompanying drawing explanation
Fig. 1 is the overall structure schematic diagram of proposed cmos image sensor;
Fig. 2 is the structural representation of predictive coding circuit module;
Fig. 3 is the circuit theory schematic diagram of predictive coding module;
Fig. 4 is the sequence circuit schematic diagram of predictive coding module.
Embodiment
In order to reduce the circuit complexity of chip, improve treatment effeciency, predictive coding is operated in to analog domain and complete.The invention provides a kind of cmos image sensor structure that can realize predictive-coded picture compression.By pel array, read and correlated double sampling circuit, predictive coding circuit, analog to digital converter (analog to digital converter, ADC) and sequential control circuit form, referring to Fig. 1.First the pixel value of reading from pel array is sent to correlated-double-sampling (correlated double sample, CDS) in circuit, carry out correlated-double-sampling to eliminate fixed pattern noise, next predictive coding circuit will carry out the operation of asking for of predicted value under the control of sequence circuit, try to achieve after predicted value and will utilize row level subtracter to try to achieve poor between predicted value and original pixel value, be residual value, finally residual value carried out to analog-to-digital conversion (AD) and just obtained final output encoder.Main invention part is predictive coding circuit.
Overall architecture adopts row level processing form, predictive coding be take 2 * 2 block of pixels and is carried out as unit, so every two row of predictive coding circuit share one, 2 * 2 block of pixels is sent in predictive coding circuit in accordance with the order from top to bottom successively, module map is referring to Fig. 2, circuit theory diagrams are shown in Fig. 3, it is combined by integrating circuit and memory circuit two parts, wherein integrating circuit is for averaged, it is predicted value, specifically by switched-capacitor circuit, four pixel values in 2 * 2 block of pixels added up and utilize electric capacity ratio to complete the operation except four, by capacitor C S, CC and amplifier A1 form, adopted Op-amp sharing, two row pixels share the operation that an amplifier is carried out electric charge transfer, wherein the capacitance of CC is that four times of CS are to complete the operation that is averaging divided by four, memory circuit is for the pixel value with the unit's of classifying as storage 2 * 2 block of pixels, so often itemize private one, it consists of C1, C2, Cf, A2, C1 ', C2 ', Cf ', A3 ', and two classify identical circuit structure as.The capacitance size of each electric capacity is: CS=1/4CC=0.5pf, C1=C2=Cf=C1 '=C2 '=Cf '=0.5pf.; Row level subtracter is for asking difference operation in the hope of residual value to pixel value and predicted value.
As shown in Figure 4, whole predictive coding process is divided into three operating states to working timing figure: reset phase, integration phase and read phase.The specific works principle that the block of pixels of take below 2 * 2 is example explanation circuit, as shown in Figure 3, the later pixel value of correlated-double-sampling reads into successively memory circuit with the unit of classifying as and predicted value produces in circuit, with the pixel of a line, reads simultaneously.
At reseting stage, Kr, K1, Kr ', K1 ' set high, the voltage at CS two ends becomes VCS=Vref+Voff1-Vcds[i] (i=1 or 2, represent line number), electric charge on Cc is QCc=4C*Voff1, the reference voltage that wherein Vref is operational amplifier, the offset voltage that Voff1 is A1, Vcds1 is the pixel value after correlated-double-sampling.The voltage at memory circuit Cf two ends after reset operation of below becomes VCf=Voff2, VCf '=Voff3, and Voff2 and Voff3 are the offset voltages of A2 and two amplifiers of A3 here.
In the stage of averaging, K2 sets high, and Cs both end voltage becomes Voff1, make electric charge on Cs transfer to Cc upper, at this moment QCc=4C*Voff1+C* (Vpix[1,1]+Vpix[1,2]), in bracket, be two pixel values of the first row first row and the first row secondary series.Such operation can repeat one-period again, makes four pixel values all complete cumulative sum except four operation.At this moment QCc=4C*Voff1+C* (Vpix[1,1]+Vpix[1,2]+Vpix[2,1]+Vpix[2,2]), because the voltage at Cc two ends is Vom and Voff1, so (Voff1+Vref-Vom) * 4C=4C*Voff1+C* (Vpix[1,1]+Vpix[1,2]+Vpix[2,1]+Vpix[2,2]), can obtain Vom=Vref-1/4C* (Vpix[1,1]+Vpix[1,2]+Vpix[2,1]+Vpix[2,2]).By prediction circuit, just can obtain the mean value of block of pixels like this, also eliminate the offset voltage of operational amplifier simultaneously.When averaging above, pixel value also stores into respectively in memory circuit separately by row, C1, C1 ' and C2, C2 ' have stored respectively the pixel value of the first row and the second row, and concrete operation is to utilize the gating of the not overlapping clock control S1 of two-phase and S2 to carry out read pixel value.The voltage at C1 two ends is VC1=VCDS[1,2] and-Voff2, the voltage at C2 two ends is VC2=VCDS[2,2]-Voff2, the voltage at C1 ' two ends is VC1=VCDS[1,1]-Voff3, the voltage at C2 ' two ends is VC2=VCDS[2,1]-Voff3.
When the signal-obtaining stage arrives, prediction circuit has completed the operation of averaging, so Vom keeps stable output.Memory circuit completes the transfer of the upper electric charge of C1, C1 ', C2 and C2 ' under the control of K1 ', K2 ', S1 ' and S2 '.After two pixel values of the first row are read, QCf=-C*Voff2+C*VCDS[1,1], QCf '=-C*Voff2+C*VCDS[1,2].
So Vo1=Vref-Vpix[1,1], Vo2=Vref-Vpix[1,2].Next, Vom, Vo1 and Vom, Vo2 by making difference operation in the row level subtracter being sent to respectively separately, obtaining residual value are
VR[i wherein, j] represent the residual value of the capable j row of i pixel value,
the mean value of four pixel values, i.e. predicted value in block of pixels.
So far obtained the residual value of pixel, next residual value will be transported in row level ADC and carry out quantization operation, and the digital code value after quantification can store or be sent to sheet and carry out entropy coding outward.
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, provide the example of a concrete numerical value to be described in further detail.
Due to prediction circuit, take 2 * 2 block of pixels and carry out work as unit, overall architecture be take such pixel cell as basis.Therefore only the block of pixels of 2 * 2 being enumerated to concrete numerical value describes.
Now suppose in block of pixels four pixels through reading with correlated-double-sampling after numerical value be respectively V[1,1]=1.3, V[1,2]=1.4, V[2,1]=1.6, V[2,2]=1.7, the pixel value V[1 of the first row, 1] and V[1,2] will first be sent in prediction circuit and process.They can be respectively transmitted in row level integrating circuit and sample circuit separately, after clock cycle in integrating circuit the magnitude of voltage at CC two ends be (V[1,1]+V[1,2])/4, C1 in two row levels storage circuits can be respectively to V[1, and 1] and V[1,2] store.Second clock cycle be when arriving, V[2,1] and V[2,2] can be sent in the same way in prediction circuit, after the clock cycle, in integrating circuit, the magnitude of voltage of CC is (V[1,1]+V[1,2]+V[2,1]+V[2,2])/4, this is the mean value of voltage in block of pixels, is predicted value, and the C2 in two row level storage circuits can be respectively to V[2,1] and V[2,2] store.Now, VCC=1.5 in integrating circuit, VC1=1.3, VC2=1.6 in first row memory circuit, VC1=1.4, VC2=1.7 in secondary series memory circuit.So far the work of prediction circuit completes, and next will carry out the work of asking for of residual value.
Four pixel values and predicted value do by being sent to respectively by row the operation that differs from row level analog subtracter separately, show that four residual value are respectively 0.2,0.1,0.1 and 0.2.Rank rear level ADC can carry out quantization operation to draw final predictive coding value by row to residual value.
Visible, the present invention can be dissolved into predictive coding operation in the sensing process of cmos image sensor, has greatly promoted image Compression efficiency.
Claims (3)
1. one kind for realizing the cmos image sensor structure of predictive-coded picture compression, it is characterized in that, cmos image sensor structure is specially, first the pixel value of reading from pel array is sent to correlated-double-sampling (correlated double sample, CDS) in circuit, carry out correlated-double-sampling to eliminate fixed pattern noise, next predictive coding circuit will carry out the operation of asking for of predicted value under the control of sequence circuit, try to achieve after predicted value and will utilize row level subtracter to try to achieve poor between predicted value and original pixel value, it is residual value, finally residual value is carried out to analog-to-digital conversion (AD) and just obtained final output encoder,
Predictive coding circuit be take 2 * 2 block of pixels and is carried out as unit, every two pixel two row share a predictive coding circuit, 2 * 2 block of pixels is sent in predictive coding circuit in accordance with the order from top to bottom successively, predictive coding circuit is combined by integrating circuit and memory circuit two parts, wherein integrating circuit is for averaged, i.e. predicted value; Memory circuit is for the pixel value with the unit's of classifying as storage 2 * 2 block of pixels; Row level subtracter is for asking difference operation in the hope of residual value to pixel value and predicted value.
2. the cmos image sensor structure of compressing for realizing predictive-coded picture as claimed in claim 1, is characterized in that, integrating circuit is by two sampling capacitance C that are connected respectively to two pixel columns
s, amplifier, sampling capacitance C
shomophase input control switch, sampling capacitance C
santi-phase input control switch, amplifier feedback capacity C
c, amplifier feedback capacity C
ccontrol switch, amplifier feedback switch, reference point position are to amplifier feedback capacity C
cbetween switch form.
3. as claimed in claim 1 for realizing the cmos image sensor structure of predictive-coded picture compression, it is characterized in that, memory circuit consists of two sampling capacitances, amplifier, sampling capacitance anti-phase input control switch, amplifier feedback capacity control switch, the amplifier feedback switch that are connected respectively to two pixel columns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410137993.7A CN103957365A (en) | 2014-04-08 | 2014-04-08 | CMOS image sensor structure for realizing predictive coding image compression |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410137993.7A CN103957365A (en) | 2014-04-08 | 2014-04-08 | CMOS image sensor structure for realizing predictive coding image compression |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103957365A true CN103957365A (en) | 2014-07-30 |
Family
ID=51334580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410137993.7A Pending CN103957365A (en) | 2014-04-08 | 2014-04-08 | CMOS image sensor structure for realizing predictive coding image compression |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103957365A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104796638A (en) * | 2015-04-20 | 2015-07-22 | 中国航天科技集团公司第九研究院第七七一研究所 | High-speed flow water output type correlated double-sampling circuit used for CMOS (complementary metal-oxide-semiconductor transistor) image sensor |
| CN106506999A (en) * | 2016-10-18 | 2017-03-15 | 天津大学 | TDI cmos image sensor FPN bearing calibrations based on match by moment |
| CN107872632A (en) * | 2016-09-22 | 2018-04-03 | 索尼公司 | Apparatus and method for the compression of P phase datas |
| CN112449125A (en) * | 2019-08-29 | 2021-03-05 | 天津大学青岛海洋技术研究院 | Image sensor reading circuit based on self-adaptive threshold adjustment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101212562A (en) * | 2006-12-28 | 2008-07-02 | 比亚迪股份有限公司 | Fixed pattern noise cancelling circuit for CMOS image sensor |
| US20090147089A1 (en) * | 2007-07-02 | 2009-06-11 | Artyom Tonkikh | Column noise reduction device and method thereof |
| CN102833494A (en) * | 2012-07-24 | 2012-12-19 | 天津大学 | Noise removing device of complementary metal oxide semiconductor (CMOS) digital pixel sensor based on predictive encoding |
-
2014
- 2014-04-08 CN CN201410137993.7A patent/CN103957365A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101212562A (en) * | 2006-12-28 | 2008-07-02 | 比亚迪股份有限公司 | Fixed pattern noise cancelling circuit for CMOS image sensor |
| US20090147089A1 (en) * | 2007-07-02 | 2009-06-11 | Artyom Tonkikh | Column noise reduction device and method thereof |
| CN102833494A (en) * | 2012-07-24 | 2012-12-19 | 天津大学 | Noise removing device of complementary metal oxide semiconductor (CMOS) digital pixel sensor based on predictive encoding |
Non-Patent Citations (1)
| Title |
|---|
| 赵士彬: "基于压缩感知的低功耗高效率CMOS图像传感器设计", 《传感技术学报》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104796638A (en) * | 2015-04-20 | 2015-07-22 | 中国航天科技集团公司第九研究院第七七一研究所 | High-speed flow water output type correlated double-sampling circuit used for CMOS (complementary metal-oxide-semiconductor transistor) image sensor |
| CN104796638B (en) * | 2015-04-20 | 2017-12-01 | 中国航天科技集团公司第九研究院第七七一研究所 | A kind of high speed flowing water output type correlated double sampling circuit for cmos image sensor |
| CN107872632A (en) * | 2016-09-22 | 2018-04-03 | 索尼公司 | Apparatus and method for the compression of P phase datas |
| CN107872632B (en) * | 2016-09-22 | 2020-05-01 | 索尼公司 | Apparatus and method for P-phase data compression |
| CN106506999A (en) * | 2016-10-18 | 2017-03-15 | 天津大学 | TDI cmos image sensor FPN bearing calibrations based on match by moment |
| CN112449125A (en) * | 2019-08-29 | 2021-03-05 | 天津大学青岛海洋技术研究院 | Image sensor reading circuit based on self-adaptive threshold adjustment |
| CN112449125B (en) * | 2019-08-29 | 2022-06-17 | 天津大学青岛海洋技术研究院 | Image sensor reading circuit based on self-adaptive threshold adjustment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103957411A (en) | Focal plane image compression device based on CMOS image sensor | |
| CN102595060B (en) | Analog accumulator capable of implementing time delay integration (TDI) function inside complementary metal-oxide semiconductor (CMOS) image sensor | |
| CN109005329B (en) | Pixel unit, image sensor and camera | |
| US9106859B2 (en) | Solid-state image pickup device with plurality of converters | |
| Park et al. | Low power CMOS image sensors using two step single slope ADC with bandwidth-limited comparators & voltage range extended ramp generator for battery-limited application | |
| US8969774B2 (en) | Conversion circuitry for reducing pixel array readout time | |
| CN103139500B (en) | Reading circuit and operation time sequence based on sigma-delta analog to digital converter (ADC) and used for imaging sensor | |
| CN102545902B (en) | Multistep single-ramp analog digital signal conversion device | |
| US10084470B2 (en) | Analogue-digital converter of non-binary capacitor array with redundant bit and its chip | |
| CN103957365A (en) | CMOS image sensor structure for realizing predictive coding image compression | |
| CN106209102A (en) | Mixed type two-layer configuration for full parellel successive approximation analog-digital converter | |
| WO2013131329A1 (en) | Low power consumption digital domain accumulating cmos-tdi image sensor | |
| CN106454164B (en) | Charge mixes cumulative type CMOS-TDI imaging sensor with number | |
| Chen et al. | A 12 pj/pixel analog-to-information converter based 816× 640 pixel cmos image sensor | |
| Yasue et al. | A 33Mpixel CMOS imager with multi-functional 3-stage pipeline ADC for 480fps high-speed mode and 120fps low-noise mode | |
| CN101533636B (en) | Low current signal amplifier | |
| CN103532553A (en) | Time domain ADC based on cycle time digital converter | |
| CN103686006B (en) | A kind of global formula exposure cmos image sensor based on compression sensing | |
| CN104243867A (en) | CMOS image sensor with high pixel and high frame rate and image collecting method | |
| CN108600579B (en) | Motion detection circuit and motion detection method applied to CIS | |
| CN100592634C (en) | Signal amplitude section divided charge redistribution successive approximation A/D converter | |
| Yue et al. | Data compression for image sensor arrays using a 15-bit two-step Sigma–Delta ADC | |
| CN105245798A (en) | CCD video compression measurement imaging system based on block-oriented compression sensing, and control method | |
| EP2629426A1 (en) | Device, system and method for analogue-to-digital conversion with noise shaping function | |
| TWI521885B (en) | Analog to digital conversion method and related analog to digital converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140730 |