CN104796638B - A kind of high speed flowing water output type correlated double sampling circuit for cmos image sensor - Google Patents
A kind of high speed flowing water output type correlated double sampling circuit for cmos image sensor Download PDFInfo
- Publication number
- CN104796638B CN104796638B CN201510188429.2A CN201510188429A CN104796638B CN 104796638 B CN104796638 B CN 104796638B CN 201510188429 A CN201510188429 A CN 201510188429A CN 104796638 B CN104796638 B CN 104796638B
- Authority
- CN
- China
- Prior art keywords
- operational amplifier
- switch
- signal
- electric capacity
- sampling circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a kind of high speed flowing water output type correlated double sampling circuit for cmos image sensor, including the first operational amplifier A 1 and the second operational amplifier A 2；The positive input of first operational amplifier A 1 and the second operational amplifier A 2 inputs the first biasing voltage signal VCM1 and the second biasing voltage signal VCM2 respectively；The negative input of first operational amplifier A 1 and the second operational amplifier A 2 connects the input VIN_ODD and VIN_EVEN of correlated double sampling circuit respectively, wherein, the signal being sampled is divided into odd number column signal and even number column signal, and the signal input part VIN_ODD and VIN_EVEN of correlated double sampling circuit are sent into respectively as input；First operational amplifier A 1 connects the output end OUT to form correlated double sampling circuit with the output end of the second operational amplifier A 2.The circuit in the case where master clock frequency is constant, can reach twice of master clock sample rate, and the circuit is also avoided that imbalance of the traditional structure during the foundation of operating point, improves sampling precision, and simple in construction, it is easy to accomplish.
Description
Technical field
The invention belongs to cmos image sensor field, and in particular to a kind of high speed flowing water for cmos image sensor
Output type correlated double sampling circuit.
Background technology
As the important electronic component for obtaining image information, cmos image sensor is numerous in photodetection and imaging etc.
Field is widely used.Due to systems such as CMOS technology compatibility is strong, low in energy consumption, wide dynamic range and reliability height
Row advantage, cmos image sensor are widely used to the skills such as astronomical surveing, digital camera, mobile phone, safety defense monitoring system, medical treatment
Art field.With requirement more and more higher of the machine system to systematic function, in the market is to high frame frequency, fireballing imaging sensor
Demand it is more and more stronger, the correlated double sampling circuit as imaging sensor important component is into the bottle for restricting this performance
Neck, therefore, how on the premise of circuit and control sequential complexity is not increased, the speed for improving correlated double sampling circuit is to work as
Previous popular research direction.
Photodiode in cmos image sensor converts optical signals into electric charge, and stores a charge in storage section
Point, then exported by a source follower, in order to weaken the noise of source follower, each pixel will be by bit line successively
Signal twice is exported, is once reset level signal, is once the optical signal on the basis of reset level, therefore cmos image passes
The reading form of sensor reading circuit generally use correlated-double-sampling (Correlated Double Sampling, CDS).It is i.e. first
By storage node reset to supply voltage, now source follower output reset level, and reset level Sampling hold is got off,
Then photogenerated charge caused by photodiode is transferred to memory node again, reading circuit is by under optical signal level Sampling hold
Come., can be by noise filtering when reset level and optical signal level are done into subtraction, here it is the principle of correlated-double-sampling.
As a rule correlated double sampling circuit is required for operational amplifier as core parts, and the gain of amplifier, response speed and builds
The precision of sampled signal can be influenceed between immediately, if optical signal level is ready for needing to carry out correlated-double-sampling, now
Amplifier is also not up to stable, so will result in that the signal errors of preceding several pixels is larger, and not enough accurately, this has had a strong impact on figure
As the quality of signal.
The content of the invention
It is an object of the invention to provide a kind of high speed flowing water output type correlated-double-sampling for cmos image sensor
Circuit, the defects of to overcome above-mentioned prior art to exist, the present invention can double sample rate, realize that high speed flowing water is defeated
Go out, imbalance of the traditional structure during the foundation of operating point can be avoided, improve sampling precision.
To reach above-mentioned purpose, the present invention adopts the following technical scheme that：
A kind of high speed flowing water output type correlated double sampling circuit for cmos image sensor, including the first operation amplifier
Device A1 and the second operational amplifier A 2；
The positive input of first operational amplifier A 1 and the second operational amplifier A 2 inputs the first bias voltage letter respectively
Number VCM1 and the second biasing voltage signal VCM2；The negative input of first operational amplifier A 1 and the second operational amplifier A 2 point
Not Lian Jie correlated double sampling circuit input VIN_ODD and signal input part VIN_EVEN, wherein, the signal being sampled is divided into
Odd number column signal and even number column signal, the signal input part VIN_ODD and letter of correlated double sampling circuit are sent into respectively as input
Number input VIN_EVEN；First operational amplifier A 1 connects to form correlated-double-sampling with the output end of the second operational amplifier A 2
The output end OUT of circuit；
The negative input of first operational amplifier A 1 and the signal input part VIN_ODD of correlated double sampling circuit are indirectly
There is the first electric capacity C1, it is in parallel between the negative input of the first operational amplifier A 1 and the output end of the first operational amplifier A 1 to set
There are first switch S1 and the second electric capacity C2, the output end of the first operational amplifier A 1 and the output end OUT of correlated double sampling circuit
Between be provided with second switch S2；
Between the negative input of second operational amplifier A 2 and the signal input part VIN_EVEN of correlated double sampling circuit
The 3rd electric capacity C3 is connected to, it is in parallel between the negative input of the second operational amplifier A 2 and the output end of the second operational amplifier A 2
Provided with the 3rd switch S3 and the 4th electric capacity C4, the output end of the second operational amplifier A 2 and the output end of correlated double sampling circuit
The 4th switch S4 is provided between OUT；
Wherein, first switch S1, the 4th switch S4 clock signal and control second switch S2, the 3rd is controlled to switch S3's
Clock signal is the cycle non-overlapping clock control signal of identical two-phase.
Further, between the output end of the negative input of the first operational amplifier A 1 and the first operational amplifier A 1 also
Parallel connection is provided with the 5th switch S5.
Further, between the output end of the negative input of the second operational amplifier A 2 and the second operational amplifier A 2 also
Parallel connection is provided with the 6th switch S6；Wherein, it is precondition clock signal to control the 5th switch S5, the 6th switch S6 clock signal.
Further, the first electric capacity C1 capacitance is identical with the 3rd electric capacity C3 capacitance.
Further, the second electric capacity C2 capacitance is identical with the 4th electric capacity C4 capacitance.
Further, the second electric capacity C2 capacitance is X times of the first electric capacity C1 capacitances, wherein, X is any real number.
Further, the 4th electric capacity C4 capacitance is X times of the 3rd electric capacity C3 capacitances, wherein, X is any real number.
Compared with prior art, the present invention has technique effect beneficial below：
The present invention, using streamline thought, sampling and amplification is exported on the premise of circuit system complexity is not increased
Concurrent process is carried out, and gives actual circuit structure and time sequence control structure, when upper circuit, which amplifies, to be exported,
Lower half of circuit sampling signal, when lower half of circuit amplification exports, upper circuit sampling signal, so circulate always past
It is multiple, in the case where master clock frequency is constant so that sampling output speed is doubled, and enhances the property of imaging sensor
Can, realize flowing water output.
Further, the 5th switch S5 and the 6th switch S6 are added in circuit of the invention, before sampling is not started,
5th switch S5 turns on the 6th switch S6 so that amplifier establishes working condition in advance, before soon sampling, by the 5th switch
The switch S6 shut-offs of S5 and the 6th, this avoid the problem of several circular errors are larger before sampling, are reduced due to amplifier
During itself is established, sampling error caused by gain deficiency is excessive, improves sampling precision, and implementation is simple, tool
There is practicality.
Further, the second electric capacity C2 capacitance is X times of the first electric capacity C1 capacitances, the 4th electric capacity C4 capacitance
It is X times of the 3rd electric capacity C3 capacitances, wherein, X is any real number, to meet the requirement of voltage amplification.
Brief description of the drawings
Fig. 1 is imaging sensor traditional sampling schematic diagram；
Fig. 2 is the timing diagram of imaging sensor traditional sampling mode；
Fig. 3 is the structure principle chart of the circuit of the present invention；
Fig. 4 is the timing diagram of controlling switch break-make in the present invention.
Embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings：
Referring to Fig. 3, a kind of high speed flowing water output type correlated double sampling circuit for cmos image sensor, including it is as follows
Component structure：
First operational amplifier A 1；
Second operational amplifier A 2；
First switch S1, its first end (left end) and the 5th switch S5 first end (left end), the first of the second electric capacity C2
End (left pole plate), the first electric capacity C1 the second end (right pole plate) and the negative input of the first operational amplifier A 1 are connected, its
Second end (right-hand member) and the 5th switch S5 the second end (right-hand member), the second electric capacity C2 the second end (right pole plate), second switch S2
First end (left end) and the output end B points of the first operational amplifier A 1 be connected；
Second switch S2, its first end (left end) and first switch S1 the second end (right-hand member), the second of the 5th switch S5
End (right-hand member), the second electric capacity C2 the second end (right pole plate) and the output end B points of the first operational amplifier A 1 are connected, and it second
End (right-hand member) is connected and as the output end of the correlated double sampling circuit with the second end (right-hand member) of the 4th switch；
3rd switch S3, its first end (left end) and the 6th switch S6 first end (left end), the first of the 4th electric capacity C4
End (left pole plate), the 3rd electric capacity C3 the second end (right pole plate) and the negative input of the second operational amplifier A 2 are connected, its
Second end (right-hand member) and the 6th switch S6 the second end (right-hand member), the 4th electric capacity C4 the second end (right pole plate), the 4th switch S4
First end (left end) and the output end D points of the second operational amplifier A 2 be connected；
4th switch S4, its first end (left end) and the 3rd switch S3 the second end (right-hand member), the second of the 6th switch S6
End (right-hand member), the 4th electric capacity C4 the second end (right pole plate) and the output end D points of the second operational amplifier A 2 are connected, and it second
End (right-hand member) is connected and as the output end of the correlated double sampling circuit with the second end (right-hand member) of second switch；
5th switch S5, its first end (left end) and first switch S1 first end (left end), the first of the second electric capacity C2
End (left pole plate), the first electric capacity C1 the second end (right pole plate) and the negative input of the first operational amplifier A 1 are connected, its
Second end (right-hand member) and first switch S1 the second end (right-hand member), the second electric capacity C2 the second end (right pole plate), second switch S2
First end (left end) and the output end B points of the first operational amplifier A 1 be connected；
6th switch S6, its first end (left end) and the 3rd switch S3 first end (left end), the first of the 4th electric capacity C4
End (left pole plate), the 3rd electric capacity C3 the second end (right pole plate) and the negative input of the second operational amplifier A 2 are connected, its
Second end (right-hand member) and the 3rd switch S3 the second end (right-hand member), the 4th electric capacity C4 the second end (right pole plate), the 4th switch S4
First end (left end) and the output end D points of the second operational amplifier A 2 be connected；
First electric capacity C1, its first end (left pole plate) and the signal input part VIN_ODD phases of the correlated double sampling circuit
Even, its second end (right pole plate) and first switch S1 first end (left end), the 5th switch S5 first end (left end), the second electricity
The reverse input end of the first end (left pole plate) and the first operational amplifier A 1 of holding C2 is connected；
Second electric capacity C2, first end (left end), fiveth switch S5 first end of its first end (left end) with first switch S1
(left end), the first electric capacity C1 the second end (right pole plate) and the negative input of the first operational amplifier A 1 are connected, and it second
(right-hand member) and the 5th is held to switch S5 the second end (right-hand member), first switch S1 the second end (right-hand member), the first of second switch S2
The output end B points of end (left end) and the first operational amplifier A 1 are connected；
3rd electric capacity C3, its first end (left pole plate) and the signal input part VIN_EVEN phases of the correlated double sampling circuit
Even, its second end (right pole plate) and the 3rd switch S3 first end (left end), the 6th switch S6 first end (left end), the 4th electricity
The negative input of the first end (left pole plate) and the second operational amplifier A 2 of holding C4 is connected；
4th electric capacity C4, first end (left end), sixth switch S6 first end of its first end (left end) with the 3rd switch S3
(left end), the 3rd electric capacity C3 the second end (right pole plate) and the negative input of the second operational amplifier A 2 are connected, and it second
The second end (right-hand member) of (right-hand member) and the 6th switch S6, the 3rd is held to switch S3 the second end (right-hand member), the first of the 4th switch S4
The output end D points of end (left end) and the second operational amplifier A 2 are connected.
The positive input of first operational amplifier A 1 connects input offset voltage signal (VCM1)；
The positive input of second operational amplifier A 2 connects input offset voltage signal (VCM2)；
First electric capacity C1 capacitance is identical with the 3rd electric capacity C3 capacitance；
Second electric capacity C2 capacitance is identical with the 4th electric capacity C4 capacitance；
Second electric capacity C2 capacitance is X times of the first electric capacity C1 capacitances, and X is any real number；
4th electric capacity C4 capacitance is X times of the 3rd electric capacity C3 capacitances, and X is any real number.
The implementation process of the present invention is described in further detail below：
Referring to Fig. 1 to Fig. 4, Fig. 1 is the simple diagram of the sampled signal of imaging sensor, it can be seen that for there is x
Multiply the imaging sensor face battle array of y pixel, when master clock cycle is T, read the time t of a width figure1For：
t1=xyT
Fig. 3 is the correlated double sampling circuit structure chart of the present invention, and the positive input of the first operational amplifier A 1 connects common mode
Bias voltage VCM1, the positive input of the second operational amplifier A 2 meets syntype bias voltage VCM2, VCM1 and VCM2 can be by base
Other bias sources such as reference voltage source or dc source provide.OUT is the output end of the correlated double sampling circuit of invention in figure.Will
The signal being sampled in Fig. 1 is divided into odd number column signal and even number column signal, and the correlation pair that the present invention is sent into respectively as input is adopted
The signal input part VIN_ODD and signal input part VIN_EVEN of sample circuit.
According to Fig. 4 timing diagram, first switch S1, the 4th switch S4 clock signal and control second switch are controlled in figure
S2, the 3rd switch S3 clock signal are the cycle non-overlapping clock control signal of identical two-phase, and T1=T2=T, i.e., main here
Clock cycle is also T, and high level turns on；It is precondition clock signal to control the 5th switch S5, the 6th switch S6 clock signal,
This switching function provides precondition mechanism, high level conducting for the correlated double sampling circuit of invention；In Fig. 4 VIN_ODD with
VIN_EVEN is the signal being sampled, and using digital circuit logic, its phase difference is opened.
When S1S4 signals are high, the first operational amplifier A 1 is connected in Unity-gain buffer pattern, now A points and B points
Voltage is identical with the voltage at VCM1 ends, is VVCM1, the first electric capacity C1 first end (left pole plate) is charged to VIN_ODD reset
Voltage V1, now upper circuit is sample phase；
When S1S4 signals are low, the switches of first switch S1 and the 4th S4 disconnects, first this part of operational amplifier A 1 electricity
Road is magnifying state, it can be seen from " empty short " of operational amplifier and " void is disconnected " principle and principle of charge conservation, without electric charge
The negative input of operational amplifier is flowed into, now, when VIN_ODD voltages change to V2 from V1, obtains equation below：
(V1-V2) C1=(VB-VVCM1)C2
That is B point voltages VBFor
VB=VVCM1+(V1-V2)C1/C2
Actually (V1-V2) is exactly photovoltage signal caused by photodiode.At the same time, S2S3 signals are height,
Second switch S2, the 3rd switch S3 are turned on, the voltage V of OUT terminal in Fig. 3OUT=VB, export the signal sampled, at this moment, the 3rd
S3 conductings are switched, the second operational amplifier A 2 is connected in Unity-gain buffer pattern, now voltage and VCM2 end of the C points with D points
Voltage is identical, is VVCM2, the 3rd electric capacity C3 first end (left pole plate) is charged to VIN_EVEN resetting voltage V3, and this is at present
Half of circuit is sample phase；
When S2S3 signals are low, second switch S2, the 3rd switch S3 disconnect, similarly, when VIN_EVEN voltages become from V3
When changing to V4, equation below is obtained：
(V3-V4) C3=(VD-VVCM2)C4
That is D point voltages VDFor
VD=VVCM2+(V3-V4)C3/C4
Here (V3-V4) is photovoltage signal caused by next photodiode.At the same time, S1S4 signals are
Height, first switch S1, the 4th switch S4 are turned on, the voltage V of OUT terminal in Fig. 3OUT=VD, export second signal sampled.
Here (C1/C2) and (C3/C4) value can select for a post meaning real number, to meet the requirement of voltage amplification.
Like this, when upper circuit, which amplifies, to be exported, lower half of circuit sampling signal, lower half of circuit amplifies defeated
When going out, upper circuit sampling signal, so move in circles always, now read the time t of a width figure2For：
t2=(xyT)/2
So sample rate is doubled, realizes flowing water output.
Among practical application, the first operational amplifier A 1 and the second operational amplifier A 2 are that finite gain, bandwidth are limited
Amplifier, the gain error of sampling is：
(C2+C1)/C2Av1
(C4+C3)/C4Av2
Here Av1For the multiplication factor of the first operational amplifier A 1, Av2For the multiplication factor of the second operational amplifier A 2.From
Upper two formula understands that after capacitance determines, the gain of amplifier is bigger, and sampling error is smaller, and precision is better.Related pair of in general is adopted
Before sampling is not started, all switches off sample circuit, before the switch S3 conductings of first switch S1 or the 3rd, amplifier A points
Or the indefinite state that B points are floating, now although amplifier has direct current biasing, but internal node does not reach real work
Quiescent point, if amplifier endophyte is larger, when first switch S1 or the 3rd switch S3 conducting after, amplifier need one
The fixed time reaches stable working condition, if this time reaches the several times in sampling period, during this period of time, fortune
Amplification gain deficiency, cause the signal voltage error of several preceding cycles output of sampling larger, influence the output of imaging sensor
Signal quality.
In the circuit of the present invention, the 5th switch S5 and the 6th switch S6 are added, its working method is shown in Fig. 4, do not started
Before sampling, the 5th switch S5 turns on the 6th switch S6 so that and amplifier establishes working condition in advance, before soon sampling,
5th switch S5 and the 6th switch S6 are turned off, this avoid the problem of several circular errors are larger before sampling, and
Implementation is simple, has practicality.
A kind of high speed flowing water output type correlated double sampling circuit for cmos image sensor of the present invention is not increasing
On the premise of circuit system complexity, using streamline thought, sampling and amplification output procedure are carried out parallel, and give reality
The circuit structure and time sequence control structure on border, in the case where master clock frequency is constant so that sampling output speed improves one
Times, enhance the performance of imaging sensor, the precondition switch of addition reduces established in itself due to amplifier during, gain is not
Sampling error is excessive caused by foot, improves sampling precision.
Described above is the preferred embodiments of the invention, it is noted that for those skilled in the art
For, on the premise of principle of the present invention is not departed from, some improvements and modifications can be also made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (7)
1. a kind of high speed flowing water output type correlated double sampling circuit for cmos image sensor, it is characterised in that including
One operational amplifier A 1 and the second operational amplifier A 2；
The positive input of first operational amplifier A 1 and the second operational amplifier A 2 inputs the first biasing voltage signal respectively
VCM1 and the second biasing voltage signal VCM2；The negative input of first operational amplifier A 1 and the second operational amplifier A 2 is distinguished
The signal input part VIN_ODD and signal input part VIN_EVEN of correlated double sampling circuit are connected, wherein, the signal being sampled point
For odd number column signal and even number column signal, respectively as the signal input part VIN_ODD and signal of input correlated double sampling circuit
Input VIN_EVEN signal；First operational amplifier A 1 connects to form related pair with the output end of the second operational amplifier A 2
The output end OUT of sample circuit；
Is connected between the negative input of first operational amplifier A 1 and the signal input part VIN_ODD of correlated double sampling circuit
One electric capacity C1, it is in parallel between the negative input of the first operational amplifier A 1 and the output end of the first operational amplifier A 1 to be provided with the
One switch S1 and the first electric capacity C2, between the output end of the first operational amplifier A 1 and the output end OUT of correlated double sampling circuit
Provided with second switch S2；
It is connected between the negative input of second operational amplifier A 2 and the signal input part VIN_EVEN of correlated double sampling circuit
3rd electric capacity C3, it is in parallel between the negative input of the second operational amplifier A 2 and the output end of the second operational amplifier A 2 to be provided with
3rd switch S3 and the 4th electric capacity C4, the output end of the second operational amplifier A 2 and the output end OUT of correlated double sampling circuit it
Between be provided with the 4th switch S4；
Wherein, first switch S1, the 4th switch S4 clock signal and control second switch S2, the 3rd switch S3 clock are controlled
Signal is the cycle non-overlapping clock control signal of identical two-phase.
A kind of 2. high speed flowing water output type correlated-double-sampling electricity for cmos image sensor according to claim 1
Road, it is characterised in that between the output end of the negative input of the first operational amplifier A 1 and the first operational amplifier A 1 also simultaneously
Connection is provided with the 5th switch S5.
A kind of 3. high speed flowing water output type correlated-double-sampling electricity for cmos image sensor according to claim 2
Road, it is characterised in that between the output end of the negative input of the second operational amplifier A 2 and the second operational amplifier A 2 also simultaneously
Connection is provided with the 6th switch S6；Wherein, it is precondition clock signal to control the 5th switch S5, the 6th switch S6 clock signal.
A kind of 4. high speed flowing water output type correlated-double-sampling electricity for cmos image sensor according to claim 1
Road, it is characterised in that the first electric capacity C1 capacitance is identical with the 3rd electric capacity C3 capacitance.
A kind of 5. high speed flowing water output type correlated-double-sampling electricity for cmos image sensor according to claim 1
Road, it is characterised in that the second electric capacity C2 capacitance is identical with the 4th electric capacity C4 capacitance.
A kind of 6. high speed flowing water output type correlated-double-sampling electricity for cmos image sensor according to claim 1
Road, it is characterised in that the second electric capacity C2 capacitance is X times of the first electric capacity C1 capacitances, wherein, X is any real number.
A kind of 7. high speed flowing water output type correlated-double-sampling electricity for cmos image sensor according to claim 1
Road, it is characterised in that the 4th electric capacity C4 capacitance is X times of the 3rd electric capacity C3 capacitances, wherein, X is any real number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510188429.2A CN104796638B (en) | 2015-04-20 | 2015-04-20 | A kind of high speed flowing water output type correlated double sampling circuit for cmos image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510188429.2A CN104796638B (en) | 2015-04-20 | 2015-04-20 | A kind of high speed flowing water output type correlated double sampling circuit for cmos image sensor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104796638A CN104796638A (en) | 2015-07-22 |
| CN104796638B true CN104796638B (en) | 2017-12-01 |
Family
ID=53561124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510188429.2A Active CN104796638B (en) | 2015-04-20 | 2015-04-20 | A kind of high speed flowing water output type correlated double sampling circuit for cmos image sensor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104796638B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106534729B (en) * | 2016-11-11 | 2019-06-11 | 中国电子科技集团公司第四十四研究所 | Programmable gain amplifier and reduction column fixed pattern noise method |
| EP3422581B1 (en) * | 2017-02-17 | 2021-02-17 | Shenzhen Goodix Technology Co., Ltd. | Correlated double sampling integrating circuit |
| CN108521549B (en) * | 2018-03-28 | 2020-08-25 | 西安微电子技术研究所 | Super large area array CMOS image sensor structure |
| CN111565032B (en) * | 2019-02-13 | 2023-11-10 | 上海耕岩智能科技有限公司 | Signal conversion circuit and signal readout circuit architecture |
| CN112600556A (en) * | 2020-12-09 | 2021-04-02 | 屹世半导体(上海)有限公司 | Sampling circuit based on clock control |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102821256A (en) * | 2011-06-08 | 2012-12-12 | 佳能株式会社 | Solid-state image pickup device and method of driving the same |
| CN103957411A (en) * | 2014-04-08 | 2014-07-30 | 天津大学 | Focal plane image compression device based on CMOS image sensor |
| CN103957365A (en) * | 2014-04-08 | 2014-07-30 | 天津大学 | CMOS image sensor structure for realizing predictive coding image compression |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI379515B (en) * | 2008-11-06 | 2012-12-11 | Novatek Microelectronics Corp | Correlated double sampling circuit |
| KR102074944B1 (en) * | 2013-06-18 | 2020-02-07 | 삼성전자 주식회사 | Programmable gain amplifier and devices having the same |
-
2015
- 2015-04-20 CN CN201510188429.2A patent/CN104796638B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102821256A (en) * | 2011-06-08 | 2012-12-12 | 佳能株式会社 | Solid-state image pickup device and method of driving the same |
| CN103957411A (en) * | 2014-04-08 | 2014-07-30 | 天津大学 | Focal plane image compression device based on CMOS image sensor |
| CN103957365A (en) * | 2014-04-08 | 2014-07-30 | 天津大学 | CMOS image sensor structure for realizing predictive coding image compression |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104796638A (en) | 2015-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104796638B (en) | A kind of high speed flowing water output type correlated double sampling circuit for cmos image sensor | |
| CN103297723B (en) | Imaging device, imaging system and driving method thereof | |
| CN101867687B (en) | A/d converter, solid-state image sensing device, and camera system | |
| CN102595060B (en) | Analog accumulator capable of implementing time delay integration (TDI) function inside complementary metal-oxide semiconductor (CMOS) image sensor | |
| US9185314B2 (en) | Mitigating the effects of signal overload in analog front-end circuits used in image sensing systems | |
| US8450673B2 (en) | Pixel circuit, imaging integrated circuit, and method for image information acquisition | |
| KR101798992B1 (en) | Sense amplifier with negative capacitance circuit and apparatuses including the same | |
| CN103002232A (en) | Imaging apparatus | |
| CN104836966B (en) | A kind of cmos image sensor column buffer signal integrity optimization circuit and its method | |
| CN105306845B (en) | A kind of correlated double sampling circuit for eliminating imbalance | |
| JP6100443B2 (en) | Amplifier adapted for CMOS imaging sensors | |
| CN102809436B (en) | Infrared array focal plane read-out circuit | |
| JP2006081189A (en) | Detection circuit for image sensor | |
| CN108391071A (en) | A kind of SPAD array class reading circuits using secondary Correlated Double Sampling | |
| CN104660923A (en) | Comparator circuit, imaging apparatus using the same, and method of controlling comparator circuit | |
| CN103533265A (en) | High-speed global shutter image sensor pixel and signal transfer control method thereof | |
| CN102905089B (en) | Photoelectric conversion apparatus, focus detecting apparatus, and imaging system | |
| CN202885976U (en) | Infrared focal-plane array read-out circuit | |
| CN101605201B (en) | Image sensor and column processing circuit thereof | |
| CN104349084A (en) | Photoelectric conversion apparatus and image pickup system | |
| WO2021128535A1 (en) | Pixel readout system of dual-modality bionic vision sensor | |
| CN103491320B (en) | Image sensing circuit and method | |
| TW202220202A (en) | Image sensor and image sensing method | |
| CN104168022B (en) | A kind of X ray CCD read-out systems based on discrete time increment type Σ Δs ADC | |
| CN104022759B (en) | A kind of high-precision single integrated narrow pulse peak holding circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |