CN113612713A - Chaos multiple access combines OFDM's safe communication system in 5G network - Google Patents
Chaos multiple access combines OFDM's safe communication system in 5G network Download PDFInfo
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Abstract
The invention relates to a chaotic multi-access OFDM (orthogonal frequency division multiplexing) combined safety communication system in a 5G network, wherein a sending end comprises a j path structure: the chaotic generator, the random bit generator, the multiplier and the mapper are sequentially connected, the mapper is connected with the subtracter through the two multipliers, and the subtracter is connected with the serial-parallel converter; the j serial-parallel converters are connected with an IFFT converter, and the IFFT converter is sequentially connected with a parallel-serial converter, a filter, a cyclic prefix and windowing device, a direct current biaser and a photoelectric modulator; the photoelectric modulator is connected with an erbium-doped fiber amplifier at a receiving end through an optical fiber, the erbium-doped fiber amplifier, the photoelectric detector, the direct current biaser, the cyclic prefix removing device, the filter, the serial-parallel converter and the FFT transformer are sequentially connected, and the FFT transformer is connected with a j-path structure: the FFT transformer is connected with the parallel-serial converter, and the parallel-serial converter is sequentially connected with the mapper, the parallel-serial converter, the correlator, the random bit generator and the chaos generator through two multipliers; the chaotic generator is connected with the transmitting end chaotic generator.
Description
Technical Field
The invention belongs to the technical field of secret communication and information safety in a 5G network, and particularly relates to a chaotic multi-access + OFDM (orthogonal frequency division multiplexing) safety communication system in the 5G network.
Background
Orthogonal Frequency Division Multiplexing (OFDM) is a technique using mutually orthogonal multiple subcarriers, in which information is first Quadrature Amplitude Modulated (QAM), then signals are serial-parallel converted and then modulated onto each subcarrier, the signals are converted into time domain signals by Inverse Fast Fourier Transform (IFFT), the received information is converted into frequency domain information by Fast Fourier Transform (FFT) at the receiving end, and the original information is demodulated by coherent demodulation and mapping. The chaos has good randomness, so that the chaos can be used for generating random bits, different high-speed random bits are multiplied by corresponding low-speed information, the power of the information is evenly distributed to a higher bandwidth, the information is subjected to QAM modulation, and subsequent OFDM modulation, and the chaos multiple access and OFDM communication can be realized. Based on the characteristics of OFDM, the invention combines the chaos multiple access with the chaos multiple access and applies the chaos multiple access to the technical field of communication, and provides a new broadband multiple access technical scheme.
Disclosure of Invention
Aiming at the current situation in the prior art, the invention provides a chaotic multi-access + OFDM (orthogonal frequency division multiplexing) secure communication system in a 5G network. The invention has the innovation that random bits are generated by utilizing the good randomness of chaos, so that the power of information is uniformly distributed to a higher bandwidth by multiplying each path of high-speed random bits by corresponding low-speed information, then QAM modulation is carried out on the information, serial-parallel conversion is carried out on the information, then the information is modulated to each subcarrier, and a signal is converted into a time domain signal by utilizing Inverse Fast Fourier Transform (IFFT); at a receiving end, the received information is converted into frequency domain information by using Fast Fourier Transform (FFT), then code division multiplexing information is demodulated by using coherent demodulation and mapping relation, and finally, the original information is recovered by related detection, thereby carrying out safe communication.
In order to achieve the purpose of the invention, the invention adopts the following technical scheme:
a chaos multiple access combines OFDM's safe communication system in 5G network, its sending end includes j way structure, each way structure is as follows: the chaotic generator, the first random bit generator, the first multiplier and the first mapper are sequentially connected, the first mapper is connected with the subtracter through two second multipliers, and the subtracter is connected with the serial-parallel converter; j series-parallel converters of the j-path structure are all connected with an IFFT converter, and the IFFT converter is sequentially connected with a first parallel-serial converter, a first filter, a first cyclic prefix importer, a first direct current biaser and a first photoelectric modulator; the first photoelectric modulator is connected with a first erbium-doped fiber amplifier at a receiving end through an optical fiber; in a receiving end, a first erbium-doped fiber amplifier, a first photoelectric detector, a second direct current biaser, a cyclic prefix removal device, a second filter, a serial-parallel converter and a first FFT converter are connected in sequence, the first FFT converter is connected with j paths of structures, and each path of structure is as follows: the first FFT converter is connected with a second parallel-serial converter, the second parallel-serial converter is respectively connected with an integrator through two third multipliers, the two integrators are connected with a second mapper, and the second mapper is sequentially connected with the third parallel-serial converter, a correlator, a second random bit generator and a chaos generator; the chaotic generator is connected with the chaotic generator at the transmitting end. Preferably, the chaotic generator is synchronized with a corresponding chaotic generator.
As a preferred scheme, the chaotic signal output by the chaotic generator is subjected to 8-bit sampling coding through the first random bit generator to generate high-speed random bits.
Preferably, at the transmitting end, the high-speed bit stream generated by the first random bit generator is multiplied by the low-speed information, so that the low-speed information is modulated onto the corresponding broadband high-speed bits, thereby implementing the hiding of the information.
As a preferred scheme, at a transmitting end, a first multiplier outputs high-speed wideband information, the high-speed wideband information is transmitted to a first mapper, various bit combinations are mapped into two symbol data according to a mapping rule of a gray code, edges are divided and multiplied by cos ω t and sin ω t, and then subtraction is performed through a subtracter to complete Quadrature Amplitude Modulation (QAM) so as to obtain a QAM symbol sequence. The transmitting end thus converts the transmitted digital signal into a mapping of subcarrier amplitudes.
Preferably, at the transmitting end, the symbol sequence formed by the first subtractor is converted into a parallel symbol stream by a serial-to-parallel converter, and the inverse fast fourier transform is performed by an IFFT converter to transform the spectral expression of the data into the time domain. Every N serial-to-parallel converted symbols are modulated by a different subcarrier.
Preferably, at the transmitting end, the time domain symbol output by the IFFT converter is converted into a serial signal by a first parallel-to-serial converter, the negative power portion is cut off by a first dc bias device through a first filter and a first cyclic prefix lead-in device, and the serial signal is converted into an optical signal by a first electro-optical modulator and transmitted through an optical fiber.
Preferably, at the receiving end, after the first EDFA amplifies the information, the first photodetector converts the optical signal into an electrical signal, the second dc biaser restores the negative power portion, the second filter filters the signal through the de-cyclic prefix device, and the serial-to-parallel converter converts the serial symbols into parallel symbols.
Preferably, at the receiving end, the frequency domain symbols output by the first FFT transformer are converted into j-path serial symbols (N symbols per path) by the second parallel-to-serial transformer. Each path of serial symbols is divided into two paths, multiplied by cos omega t and sin omega t respectively, and integrated, and the jth path obtains xj，yj；xj，yjThe corresponding bit combination is restored by the second mapper and then obtained by the third parallel-to-serial converterIs received by the receiver.
As a preferred scheme, at a receiving end, the chaotic signal output by the chaotic generator is subjected to 8-bit sampling coding through the second random bit generator to generate high-speed random bits.
Preferably, at the receiving end, the high-speed random bit and the recovered first path of spread spectrum sequence are subjected to cross-correlation operation by a cross-correlator, and when the cross-correlation coefficient is close to 1, the cross-correlation coefficient is judged to be 1, and when the cross-correlation coefficient is close to-1, the cross-correlation coefficient is judged to be 0.
The chaos multiple access + OFDM principle and process of the invention are as follows:
the 1 st chaotic generator is synchronous with the j +1 th chaotic generator, the 2 nd chaotic generator is synchronous with the j +2 th chaotic generator, …, and the j th chaotic generator is synchronous with the 2j th chaotic generator. The above is used as chaotic carrier for encryption and decryption.
The chaotic signal output by the 1 st chaotic generator is utilized to carry out 8-bit sampling coding on the chaotic signal through the 1 st random bit generator, and further high-speed random bits are generated; similarly, the chaotic signal output by the 2 nd chaotic generator carries out 8-bit sampling coding on the chaotic signal through the 2 nd random bit generator to generate high-speed random bits; …, respectively; and 8-bit sampling coding is carried out on the chaotic signal output by the jth chaotic generator through the jth random bit generator, so as to generate high-speed random bits. The high-speed bit stream generated by the 1 st random bit generator is multiplied by the low-speed information m1, the high-speed bit stream generated by the 2 nd random bit generator is multiplied by the low-speed information m2, …, and the high-speed bit stream generated by the jth random bit generator is multiplied by the low-speed information mj, so that the low-speed information is modulated onto the corresponding broadband high-speed bits, and the encryption of the information is realized.
The high-speed wideband information output by the 1 st multiplier is transmitted to the 1 st mapper, and various bit combinations are mapped into x according to the mapping rule of Gray code1,y1Dividing two symbol data into edge, multiplying by cos omega t and sin omega t, then subtracting by subtracter to obtain complex signal …, transmitting the high-speed wideband information output by jth multiplier to jth mapper according to Gray code mappingRule, mapping various bit combinations to xj，yjAnd dividing the two data into edges and multiplying the edges by cos omega t and sin omega t, and then subtracting the edges by a subtracter to obtain complex symbol data so as to complete Quadrature Amplitude Modulation (QAM) and obtain a QAM symbol sequence. The transmitting end thus converts the transmitted digital signal into a mapping of subcarrier amplitudes. The 1 st subtracter forms a symbol sequence, the 1 st serial-parallel converter converts the serial symbol sequence into a parallel symbol stream, and then adds a pilot training symbol. The symbol sequence formed by the 2 nd subtracter is converted into a parallel symbol stream by a 2 nd serial-parallel converter, and then pilot training symbols are added. … are provided. And converting the serial symbol sequence into a parallel symbol stream through a jth serial-parallel converter by the jth subtracter. The data is transformed from the spectral superposition to the time domain by performing an inverse fast fourier transform using the 1 st IFFT transformer, and then adding pilot training symbols. Every N serial-to-parallel converted symbols are modulated by a different subcarrier. The time domain symbol output by the 1 st IFFT converter is converted into a serial signal through the 1 st parallel-serial converter, a negative power part is cut off by a1 st direct current biaser through a1 st filter, a1 st cyclic prefix and a window adder, and the serial signal is converted into an optical signal through a1 st photoelectric modulator and transmitted in an optical fiber.
And when the signal reaches a receiving end, the 1 st EDFA is used for amplifying information, the 1 st photoelectric detector is used for converting an optical signal into an electric signal, the 2 nd direct current biaser is used for restoring a negative power part, the negative power part passes through a cyclic prefix removing device, then a 2 nd filter is used for filtering, and a j +1 th serial-parallel converter is used for converting serial symbols into parallel symbols. The 1 st FFT converter converts the time domain symbols into frequency domain symbols, and converts the frequency domain symbols into j paths of serial symbols (N symbols in each path) through j parallel-serial converters, and pilot training symbols are subtracted from each path. Each path of serial symbols is divided into two paths, multiplied by cos ω t and sin ω t, respectively, and integrated. The first path is reduced to x1,y1(ii) a …, respectively; j th way reduction place xj，yj。
Thus the symbol x1,y1The corresponding bit combination is restored by the j +1 mapper, …, way j xj,yjRestoring phases by a 2j mapperThe corresponding bit combinations. And then the bit stream spread by the corresponding original random bit is obtained through the parallel-serial converters of the j +2, the j +3, … and the 2j + 1.
The chaotic signal which is output by the (j +1) th chaotic generator and is synchronous with the (1) th chaotic generator carries out 8-bit sampling coding on the chaotic signal through the (j +1) th random bit generator, and further generates a high-speed random bit for decoding; …, respectively; and similarly, the 2j chaotic generator generates chaotic signals synchronous with the j chaotic generator, and the 2j random bit generator performs 8-bit sampling coding on the chaotic signals to generate high-speed random bits for decoding.
Performing cross-correlation operation on one information bit by using a cross-correlator on the j +1 path of high-speed random bits and the recovered first path of spread spectrum sequence, judging the cross-correlation coefficient to be 1 when the cross-correlation coefficient is close to 1, and judging the cross-correlation coefficient to be 0 when the cross-correlation coefficient is close to-1; …, respectively; and performing cross-correlation operation on one information bit by the cross-correlator on the 2j high-speed random bit and the recovered j spreading sequence, judging the bit to be 1 when the cross-correlation coefficient is close to 1, and judging the bit to be 0 when the cross-correlation coefficient is close to-1.
Compared with the prior art, the invention has the beneficial effects that:
the invention completes the safe communication of chaos multiple access + OFDM, and the safety is as follows: during decoding, the chaos is required to be synchronous, and the chaos is sensitive to circuit parameters and initial conditions, so that the safety of communication is ensured.
Drawings
Fig. 1 is a frame diagram of a chaotic multiple access + OFDM secure communication system in a 5G network according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a chaotic signal output by a first chaotic generator at a transmitting end according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a chaotic signal output by a j +1 th chaotic generator at a receiving end according to an embodiment of the present invention;
fig. 4 is a schematic diagram of OFDM subcarrier spectrum according to an embodiment of the present invention.
Fig. 5(a) shows the original signal sent in the first path, and fig. 5(b) shows the demodulated signal.
Wherein:
a1 st chaotic generator 1-1, a 2 nd chaotic generator 1-2, and … th chaotic generator 1-j;
1 st random bit generator 2-1, 2 nd random bit generator 2-2, …, jth random bit generator 2-j;
a1 st multiplier 3-1, a 2 nd multiplier 3-2, … and a jth multiplier 3-j;
the 1 st mapper 4-1, the 2 nd mapper 4-2, …, the jth mapper 4-j;
a j +1 th multiplier 3- (j +1), a j +2 th multiplier 3- (j +2), an … 3j-1 th multiplier 3- (3j-1) and a 3j th multiplier 3-3 j;
a1 st subtracter 5-1, a 2 nd subtracters 5-2, … and a jth subtracter 5-j;
a1 st serial-parallel converter 6-1, a 2 nd serial-parallel converter 6-2, … and a jth serial-parallel converter 6-j;
an IFFT converter 8, a1 st parallel-serial converter 9-1, a1 st filter 10-1, a1 st cyclic prefix device 11-1, a1 st direct current biaser 12-1 and a1 st photoelectric modulator 13; a1 st EDFA (erbium-doped fiber amplifier) 16, a1 st photoelectric detector 17, a 2 nd DC biaser 12-2, a cyclic prefix remover 11-2, a 2 nd filter 10-2, a j +1 th serial-parallel converter 6- (j +1) and a1 st FFT converter 18;
2 nd parallel-to-serial converters 9-2, … and j +1 th parallel-to-serial converter 9- (j + 1);
the 3j +1 th multiplier 3- (3j +1), … and the 5j multiplier 3-5 j;
1 st integrator 14-1, 2 nd integrators 14-2, …, 2j integrator 14-2 j;
a j +1 th mapper 4- (j +1), a j +2 th mapper 4- (j +2), …, a 2j th mapper 4-2 j;
a j +1 th random bit generator 2- (j +1), a j +2 th random bit generator 2- (j +2), …, a 2j random bit generator 2-2 j;
the j +1 th chaotic generator 1- (j +1), the j +2 th chaotic generator 1- (j +2), … and the 2j chaotic generator 1-2 j.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention, the following description will explain the embodiments of the present invention with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
The invention relates to a chaotic multi-access and OFDM (orthogonal frequency division multiplexing) secure communication system in a 5G network, which comprises a sending end and a receiving end, wherein the sending end and the receiving end are connected through an optical fiber.
Specifically, the transmitting end includes a1 st chaos generator, a 2 nd chaos generator, an … th chaos generator, a1 st random bit generator, a 2 nd random bit generator, …, a jth random bit generator, a1 st multiplier, a 2 nd multiplier, …, a 3 jth multiplier, a1 st mapper, a 2 nd mapper, …, a jth mapper, a1 st subtractor, a 2 nd subtractor, …, a jth subtractor, a1 st serial-to-parallel converter, a 2 nd serial-to-parallel converter, …, a jth serial-to-parallel converter, an IFFT converter, a1 st parallel-to-serial converter, a1 st filter, a1 st cyclic prefix device, a1 st dc offset device, and a1 st electro-optic modulator.
The receiving end comprises a 1EDFA (erbium-doped fiber amplifier), a1 st photoelectric detector, a 2 nd DC biaser, a de-circulation prefix device, a j +1 th serial-parallel converter, a1 st FFT converter, a 2 nd parallel-serial converter, …, a 2j +1 th parallel-serial converter, a 3j +1 th multiplier, …, a 5j multiplier, a1 st integrator, a 2 nd integrator, …, a 2j integrator, a j +1 th mapper, a j +2 th mapper, …, a 2j mapper, a1 st correlator, a 2 nd correlator, a j correlator, a 2j chaos generator, a j +1 th random bit generator, a j +2 th random bit generator, …, a 2j random bit generator, a j +1 th chaos generator, a j +2 th chaos generator, … and a 2j chaos generator which are connected in sequence.
The receiving end is connected with the transmitting end through an optical fiber.
The 1 st chaotic generator is synchronous with the j +1 th chaotic generator, the 2 nd chaotic generator is synchronous with the j +2 th chaotic generator, …, and the j th chaotic generator is synchronous with the 2j th chaotic generator. The chaotic signal output by the 1 st chaotic generator is utilized to carry out 8-bit sampling coding on the chaotic signal through the 1 st random bit generator, and further high-speed random bits are generated; similarly, the chaotic signal output by the 2 nd chaotic generator carries out 8-bit sampling coding on the chaotic signal through the 2 nd random bit generator to generate high-speed random bits; …, respectively; and 8-bit sampling coding is carried out on the chaotic signal output by the jth chaotic generator through the jth random bit generator, so as to generate high-speed random bits. The high-speed bit stream generated by the 1 st random bit generator is multiplied by the low-speed information m1, the high-speed bit stream generated by the 2 nd random bit generator is multiplied by the low-speed information m2, …, and the high-speed bit stream generated by the jth random bit generator is multiplied by the low-speed information mj, so that the low-speed information is modulated onto the corresponding broadband high-speed bits, and the encryption of the information is realized.
The high-speed wideband information output by the 1 st multiplier is transmitted to the 1 st mapper, and various bit combinations are mapped into x according to the mapping rule of Gray code1，y1Dividing the data of two symbols, multiplying the divided edges by cos ω t and sin ω t, subtracting the result by a subtracter to obtain a complex signal, adding a pilot training symbol, …, transmitting the high-speed wideband information output by the jth multiplier to the jth mapper, and mapping various bit combinations into x according to the mapping rule of Gray codesj，yjThe two data are divided and multiplied by cos omega t and sin omega t, then complex symbol data are obtained through subtraction of a subtracter, Quadrature Amplitude Modulation (QAM) is completed, a QAM symbol sequence is obtained, and then pilot training symbols are added. The transmitting end thus converts the transmitted digital signal into a mapping of subcarrier amplitudes. The 1 st subtracter forms a symbol sequence, the 1 st serial-parallel converter converts the serial symbol sequence into a parallel symbol stream, and then adds a pilot training symbol. The symbol sequence formed by the 2 nd subtractor is converted into a parallel symbol stream by the 2 nd serial-to-parallel converter and then added with a pilot training symbol, …, and the symbol sequence formed by the jth subtractor is converted into a parallel symbol stream by the jth serial-to-parallel converter and then added with a pilot training symbol. And performing inverse fast Fourier transform by using the 1 st IFFT transformer to transform the spectrum expression of the data to a time domain. Every N serial-to-parallel converted symbols are differently sub-carriedWave modulation. The time domain symbol output by the 1 st IFFT converter is converted into a serial signal through the 1 st parallel-serial converter, a negative power part is cut off by a1 st direct current biaser through a1 st filter and a1 st cyclic prefix leading-in device, and the serial signal is converted into an optical signal through the 1 st photoelectric modulator and transmitted in an optical fiber.
And when the signal reaches a receiving end, the 1 st EDFA is used for amplifying information, the 1 st photoelectric detector is used for converting an optical signal into an electric signal, the 2 nd direct current biaser is used for restoring a negative power part, the negative power part passes through a cyclic prefix removing device, then a 2 nd filter is used for filtering, and a j +1 th serial-parallel converter is used for converting serial symbols into parallel symbols. The 1 st FFT transformer converts the time domain symbols into frequency domain symbols, which are converted into j serial symbols (N symbols per path) by j parallel-to-serial converters. After subtracting the pilot training symbol from each path of serial symbols, dividing the symbols into two paths, respectively multiplying by cos ω t and sin ω t, and performing integration. The first path is reduced to x1，y1(ii) a …, respectively; j th way reduction place xj，yj. Thus the symbol x1，y1The corresponding bit combination is restored by the j +1 mapper, …, way j xj，yjThe corresponding bit combination is restored by the 2j mapper. And then the bit stream spread by the corresponding original random bit is obtained through the parallel-serial converters of the j +2, the j +3, … and the 2j + 1. The chaotic signal which is output by the (j +1) th chaotic generator and is synchronous with the (1) th chaotic generator carries out 8-bit sampling coding on the chaotic signal through the (j +1) th random bit generator, and further generates a high-speed random bit for decoding; …, respectively; and similarly, the 2j chaotic generator generates chaotic signals synchronous with the j chaotic generator, and the 2j random bit generator performs 8-bit sampling coding on the chaotic signals to generate high-speed random bits for decoding. Performing cross-correlation operation on one information bit by using a cross-correlator on the j +1 path of high-speed random bits and the recovered first path of spread spectrum sequence, judging the cross-correlation coefficient to be 1 when the cross-correlation coefficient is close to 1, and judging the cross-correlation coefficient to be 0 when the cross-correlation coefficient is close to-1; …, respectively; and performing cross-correlation operation on one information bit by the cross-correlator on the 2j high-speed random bit and the recovered j spreading sequence, judging the bit to be 1 when the cross-correlation coefficient is close to 1, and judging the bit to be 0 when the cross-correlation coefficient is close to-1.
As shown in fig. 1, a specific connection relationship between the chaotic multiple access and the OFDM secure communication system in the 5G network according to the embodiment of the present invention is as follows:
the transmitting end comprises a1 st chaotic generator 1-1, a 2 nd chaotic generator 1-2, a … th chaotic generator 1-j, a1 st random bit generator 2-1, a 2 nd random bit generator 2-2, …, a jth random bit generator 2-j, a1 st multiplier 3-1, a 2 nd multiplier 3-2, …, a 3 jth multiplier 3-3j, a1 st mapper 4-1, a 2 nd mapper 4-2, …, a jth mapper 4-j, a1 st subtracter 5-1, a 2 nd subtracter 5-2, …, a jth subtracter 5-j, a1 st serial-to-parallel converter 6-1, a 2 nd serial-to-parallel converter 6-2, …, a jth serial-to-parallel converter 6-j, an IFFT converter 8, a1 st parallel-to-serial converter 9-1, a jth serial-to-parallel converter, A1 st filter 10-1, a1 st cyclic prefix device 11-1, a1 st direct current biaser 12-1 and a1 st photoelectric modulator 13. Specifically, in fig. 1, the right port of the 1 st chaotic generator 1-1 at the transmitting end is connected to the left port of the 1 st random bit generator 2-1, the right port of the 1 st random bit generator 2-1 is connected to the left port of the 1 st multiplier 3-1, the right port of the 1 st multiplier 3-1 is connected to the left first and second ports of the 1 st mapper 4-1, the right first and second ports of the 1 st mapper 4-1 are respectively connected to the left ports of the 3- (j +1) th and 3- (j +2) th multipliers, the right ports of the 3- (j +1) th and 3- (j +2) th multipliers are respectively connected to the upper and lower ports of the 1 st subtractor 5-1, the right port of the 1 st subtractor 5-1 is connected to the left port of the 1 st serializer 6-1, and the right port of the 1 st serializer 6-1 is connected to the left port, Divided into N parallel symbols by the 1 st serial-to-parallel converter 6-1, and N ports on the right side of the 1 st serial-to-parallel converter 6-1 are connected to N ports on the left side of the IFFT transformer 8.
The right port of the 2 nd chaotic generator 1-2 is connected with the left port of the 2 nd random bit generator 2-2, the right port of the 2 nd random bit generator 2-2 is connected with the left port of the 2 nd multiplier 3-2, the right port of the 2 nd multiplier 3-2 is connected with the left first and second ports of the 2 nd mapper 4-2, the right first and second ports of the 2 nd mapper 4-1 are respectively connected with the left ports of the 3- (j +3) th and 3- (j +4) th multipliers, the right ports of the 3- (j +3) th and 3- (j +4) th multipliers are respectively connected with the upper and lower ports of the 2 nd subtractor 5-2, the right port of the 2 nd subtractor 5-2 is connected with the left port of the 2 nd serial-parallel converter 6-2, the right port of the 2 nd multiplier is connected with the left port of the 2 nd multiplier, Divided into N parallel symbols by the 2 nd serial-to-parallel converter 6-2, and the right N ports of the 2 nd serial-to-parallel converter 6-2 are connected to the left N ports of the IFFT transformer 8.
…。
And so on, the right port of the jth chaotic generator 1-j is connected with the left port of the jth random bit generator 2-j, the right port of the jth random bit generator 2-j is connected with the left port of the jth multiplier 3-j, the right port of the jth multiplier 3-j is connected with the left first and second ports of the jth mapper 4-j, the right first and second ports of the jth mapper 4-j are respectively connected with the left ports of the 3- (3j-1) and the 3-3j multipliers, the right ports of the 3- (3j-1) and the 3-3j multipliers are respectively connected with the upper and lower ports of the jth subtractor 5-j, the right port of the jth subtractor 5-j is connected with the left port of the jth serial-parallel converter 6-j, and the right port of the jth multiplier is connected with the left port of the jth multiplier 6-j, Is divided into N parallel symbols by a jth serial-parallel converter 6-j, and N ports on the right side of the jth serial-parallel converter 6-j are connected to N ports on the left side of an IFFT converter 8.
The right j × N ports of the IFFT converter 8 are connected to the left j × N ports of the 1 st parallel-to-serial converter 9-1, the 1 st parallel-to-serial converter 9-1 converts the parallel sequence into a serial sequence, the right port of the 1 st parallel-to-serial converter 9-1 is connected to the left port of the 1 st filter 10-1, the right port of the 1 st filter 10-1 is connected to the left port of the 1 st cyclic prefix unit 11-1, the right port of the 1 st cyclic prefix unit 11-1 is connected to the left port of the 1 st dc offset unit 12-1 to cut out negative symbols, the right port of the 1 st dc offset unit 12-1 is connected to the left port of the 1 st electro-optical modulator 13, and the 1 st electro-optical modulator 13 converts the electrical signal into an optical signal.
The optical signal is connected to the upper port of the 1 st EDFA16 at the receiving end through an optical fiber.
A receiving end including a 1EDFA (erbium doped fiber amplifier) 16, a1 st photodetector 17, a 2 nd DC biaser 12-2, a de-cyclic prefix device 11-2, a 2 nd filter 10-2, a j +1 th serial-parallel converter 6- (j +1), a1 st FFT converter 18, a 2 nd parallel-serial converter 9-2, …, a j +1 th parallel-serial converter 9- (j +1), a 3j +1 th multiplier 3- (3j +1), …, a 5j multiplier 3-5j, a1 st integrator 14-1, a 2 nd integrator 14-2, …, a 2j integrator 14-2j, a j +1 th mapper 4- (j +1), a j +2 th mapper 4- (j +2), …, a 2j th mapper 4-2j, a1 st correlator 15-2, a 2 nd direct current (EDFA), a 2 nd filter 10-2, a j +1 th serial-parallel converter 6- (j +1), a1 st FFT converter 18, a1 st FFT converter, a 2 nd (FFT converter, a1 st FFT converter 18-2, a 2 nd integrator, a 5 th multiplier 3-5 th multiplier, a1 st integrator 14-1, a 2, a1 st integrator, a 2 nd integrator, a 2 nd integrator, a 2 h integrator, a correlator, a 2 h integrator, a correlator, a 2 th integrator, a 2, a 3-th integrator, a 3-2, a 3-5 j-2, a 3-2-th integrator, a 3-2, a 3-th integrator, a 3-5-th integrator, a 3-5-th integrator, a 2, a mapper, a 3-2, a mapper, a 3-2, a 3, a mapper, a 2, a 3-2, a 3, a 2, a mapper, a 2, a 3, a mapper, a 3, a, The 2 nd correlator 15-2, the j th correlator 15-j, the j +1 th random bit generator 2- (j +1), the j +2 th random bit generator 2- (j +2), …, the 2j th random bit generator 2-2j, the j +1 th chaotic generator 1- (j +1), the j +2 th chaotic generator 1- (j +2), … and the 2j th chaotic generator 1-2 j.
Specifically, the lower port of the 1 st EDFA (erbium doped fiber amplifier) 16 is connected with the right port of the 1 st photodetector 17, the left port of the 1 st photodetector 17 is connected with the right port of the 2 nd dc biaser 12-2, the right port of the 2 nd dc biaser 12-2 is connected with the right port of the cyclic prefix remover 11-2, the left port of the cyclic prefix remover 11-2 is connected with the right port of the 2 nd filter 10-2, the left port of the 2 nd filter 10-2 is connected to the right port of the j +1 th serial-parallel converter 6- (j +1), the j +1 th serial-parallel converter 6- (j +1) converts the serial signal into a parallel signal, the left j × N port of the j +1 th serial-parallel converter is connected to the right j × N port of the 1 st FFT converter 18, and the left 1 of the 1 st FFT converter 18: the N port is connected with the right N port of the 2 nd parallel-serial converter 9-2, the output signal of the left port of the 2 nd parallel-serial converter 9-2 is divided into two paths which are respectively connected with the right two ports of the 3j +1 st multiplier 3- (3j +1) and the 3j +2 rd multiplier 3- (3j +2), the left two ports of the 3j +1 st multiplier 3- (3j +1) and the 3j +2 nd multiplier 3- (3j +2) are connected to the right two ports of the 1 st integrator 14-1 and the 2 nd integrator 14-2, the left two ports of the 1 st integrator 14-1 and the 2 nd integrator 14-2 are respectively connected to the right two ports of the j +1 th mapper 4- (j +1), and the mapper 4- (j +1) restores the first path of spread spectrum sequence. The left two ports of the j +1 mapper 4- (j +1) are connected with the right two ports of the j +2 parallel-serial converter 9- (j +2), the left port of the j +2 parallel-serial converter 9- (j +2) is connected with the right port of the 1 st correlator 15-1, the left port of the 1 st correlator 15-1 is connected with the right port of the j +1 st random bit generator 2- (j +1), and the left port of the j +1 st random bit generator 2- (j +1) is connected with the right port of the j +1 st chaotic generator 1- (j + 1).
…。
By analogy, the 1 st FFT transformer 18 left side (j-1) N + 1: the jN port is connected with the right N port of the j +1 th parallel-serial converter 9- (j +1), the output signal of the left port of the j +1 th parallel-serial converter 9- (j +1) is divided into two paths, which are respectively connected with the right two ports of the 5j-1 st multiplier 3- (5j-1) and the 5j multiplier 3-5j, the left two ports of the 5j-1 st multiplier 3- (5j-1) and the 5j multiplier 3-5j are connected with the right two ports of the 2j-1 st integrator 14- (2j-1) and the 2j integrator 14-2j, and the left two ports of the 2j-1 st integrator 14- (2j-1) and the 2j integrator 14-2j are respectively connected with the right two ports of the 2j mapper 4-2j, the left two ports of the, The mapper 4-2j restores the first path of spread spectrum sequence. The left two ports of the 2j mapper 4-2j are connected with the right two ports of the 2j +1 parallel-serial converter 9- (2j +1), the left port of the 2j +1 parallel-serial converter 9- (2j +1) is connected with the right port of the j correlator 15-j, the left port of the j correlator 15-j is connected with the right port of the 2j random bit generator 2-2j, and the left port of the 2j random bit generator 2-2j is connected with the right port of the 2j chaotic generator 1-2 j.
The left port of the 1 st chaotic generator 1-1 is connected with the left measurement port of the j +1 th chaotic generator 1-2j, the left port of the 2 nd chaotic generator 1-2 is connected … with the left measurement port of the j +2 th chaotic generator 1- (j +2), and the left port of the j chaotic generator 1-j is connected with the left measurement port of the 2j chaotic generator 1- (j + 1). The manner of use of the secure communication system of the present embodiment will be described below in conjunction with the above-described system configuration.
A1 st chaotic generator 1-1 is synchronous with a 2j chaotic generator 1-2j, a 2 nd chaotic generator 1-2 is synchronous with a 1- (j +2) th chaotic generator …, and the j th chaotic generator 1-j is synchronous with a j +1 th chaotic generator 1- (j + 1). The chaotic signal output by the 1 st chaotic generator 1-1 is subjected to 8-bit sampling coding through the 1 st random bit generator 2-1 to further generate high-speed random bits; the chaotic signal output by the 2 nd chaotic generator 1-2 is subjected to 8-bit sampling coding through the 2 nd random bit generator 2-2 to generate high-speed random bits; …, respectively; the chaotic signal output by the jth chaotic generator 1-j is subjected to 8-bit sampling coding through the jth random bit generator 2-j to generate high-speed random bits.
At the transmitting end, the high-speed bit stream generated by the 1 st random bit generator 2-1 is multiplied by the low-speed information m1 through the 1 st multiplier 3-1, the high-speed bit stream generated by the 2 nd random bit generator 2-2 is multiplied by the low-speed information m2 through the 2 nd multiplier 3-2, …, and the high-speed bit stream generated by the 2-j random bit generator is multiplied by the low-speed information mj through the j-th multiplier 3-j, so that the low-speed information is modulated onto the corresponding broadband high-speed bits, and the hiding of the information is realized. The high-speed wideband information output by the 1 st multiplier 3-1 is transmitted to the 1 st mapper 4-1, and various bit combinations are mapped into x according to the mapping rule of Gray code1，y1Dividing two symbol data into edges, multiplying the edges by cos omega t and sin omega t, subtracting the edges by a1 st subtracter 5-1 to obtain a complex signal, completing Quadrature Amplitude Modulation (QAM), obtaining a QAM symbol sequence, adding a pilot frequency training symbol, …, and so on, transmitting high-speed broadband information output by a jth multiplier 3-j to a jth mapper 4-j, and mapping various bit combinations into x according to the mapping rule of Gray codesj，yjThe two data are divided to multiply cos omegat and sin omegat, then complex symbol data are obtained through subtraction of a jth subtracter 5-j, Quadrature Amplitude Modulation (QAM) is completed, a QAM symbol sequence is obtained, and then pilot frequency training symbols are added. The transmitting end thus converts the transmitted digital signal into a mapping of subcarrier amplitudes. The 1 st subtractor 5-1 generates a symbol sequence, and the 1 st serial-to-parallel converter 6-1 converts the serial symbol sequence into a parallel symbol stream. The symbol sequence formed by the 2 nd subtractor 5-2 is converted into a parallel symbol stream by the 2 nd serial-to-parallel converter 6-2, …, and the symbol sequence formed by the jth subtractor 5-j is converted into a parallel symbol stream by the jth serial-to-parallel converter 6-j. The 1 st IFFT transformer 8 performs inverse fast fourier transform to transform the spectral representation of the data to the time domain. Every N serial-to-parallel converted symbols are modulated by a different subcarrier. The time domain symbol output by the first IFFT transformer 8 is converted into a serial signal by the 1 st parallel-to-serial converter 9-1, passed through the 1 st filter 10-1, the 1 st cyclic prefix introduction 11-1, the negative power portion is cut off by the 1 st dc biaser 12-1, passed through the 1 st photoelectric modulator 13,becomes an optical signal transmitted in the optical fiber.
The optical signal reaches the receiving end, the 1 st EDFA16 is used for amplifying information, the 1 st photoelectric detector 17 converts the optical signal into an electric signal, the 2 nd direct current biaser 12-2 restores the negative power part, the negative power part passes through the circulating prefix removing device 11-2 and then the 2 nd filter for filtering 10-2, and the serial symbol is converted into a parallel symbol through the j +1 th serial-parallel converter 6- (j + 1). The 1 st FFT transformer 18 converts the time domain symbols into frequency domain symbols, which are converted into j-way serial symbols (N symbols per way) by j parallel-to-serial transformers 9-2 to 9- (j + 1). Each path of serial symbols is divided into two paths, multiplied by cos ω t and sin ω t respectively, and integrated, and subtracted by the pilot training symbols, the first path is restored to x1,y1(ii) a …, respectively; j th way reduction place xj,yj. Thus the symbol x1,y1The corresponding bit combination is restored by the j +1 mapper 4- (j +1), …, the j-th path xj,yjThe corresponding bit combinations are restored by the 2j mappers 4-2 j. And then the bit streams spread by the corresponding original random bits are obtained through second, third, …, j +1 parallel-serial converters 9-2, 9-3 … and 9- (j +1), respectively. The chaotic signal which is output by the (j +1) th chaotic generator 1- (j +1) and is synchronous with the (1) th chaotic generator 1-j is subjected to 8-bit sampling coding through the (j +1) th random bit generator 2- (j +1) to further generate a high-speed random bit for decoding; …, respectively; and similarly, the 2j chaotic generators 1-2j generate chaotic signals synchronized with the 1-j chaotic generators 1-j, and the chaotic signals are subjected to 8-bit sampling coding through the 2-2j random bit generators to generate high-speed random bits for decoding. Performing cross-correlation operation on one information bit by using a cross-correlator on the j +1 path of high-speed random bits and the recovered first path of spread spectrum sequence, judging the cross-correlation coefficient to be 1 when the cross-correlation coefficient is close to 1, and judging the cross-correlation coefficient to be 0 when the cross-correlation coefficient is close to-1; …, respectively; and performing cross-correlation operation on one information bit by the cross-correlator on the 2j high-speed random bit and the recovered j spreading sequence, judging the bit to be 1 when the cross-correlation coefficient is close to 1, and judging the bit to be 0 when the cross-correlation coefficient is close to-1.
The above communication implementation process is briefly summarized as follows:
1. two chaos generators corresponding to the two transmitting and receiving ends are synchronous.
2. And obtaining random bits by using the chaotic signal, and spreading the information.
3. And carrying out QAM modulation on the spread spectrum information.
4. Adding pilot training symbols, performing Fourier transform by using IFFT after serial-parallel transformation, then performing parallel-serial transformation, and adding cyclic prefix.
5. And adding the direct current bias to cut off the part with the negative amplitude.
6. The electrical signal is converted to an optical signal using an electro-optical modulator.
7. The receiving end converts the optical signal into an electrical signal using a detector.
8. After the serial-parallel transformation, the FFT is used for Fourier transformation.
9. QAM demodulates to obtain spread spectrum signal, which uses random bit to de-spread.
While the preferred embodiments and principles of this invention have been described in detail, it will be apparent to those skilled in the art that variations may be made in the embodiments based on the teachings of the invention and such variations are considered to be within the scope of the invention.
Claims (10)
1. A chaos multiple access combines OFDM's safe communication system in 5G network, characterized by that:
the transmitting end comprises j paths of structures, and each path of structure is as follows: the chaotic generator, the first random bit generator, the first multiplier and the first mapper are sequentially connected, the first mapper is connected with the subtracter through two second multipliers, and the subtracter is connected with the serial-parallel converter; j series-parallel converters of the j-path structure are connected with an IFFT converter, and the IFFT converter is sequentially connected with a first parallel-serial converter, a first filter, a first cyclic prefix and windowing device, a first direct current biaser and a first photoelectric modulator; the first photoelectric modulator is connected with a first erbium-doped fiber amplifier at a receiving end through an optical fiber;
in a receiving end, a first erbium-doped fiber amplifier, a first photoelectric detector, a second direct current biaser, a cyclic prefix remover, a second filter, a serial-parallel converter and a first FFT transformer are connected in sequence, the first FFT transformer is connected with j paths of structures, and each path of structure is as follows: the first FFT transformer is connected with a second parallel-serial converter, the second parallel-serial converter is respectively connected with an integrator through two third multipliers, the two integrators are connected with a second mapper, and the second mapper is sequentially connected with the third parallel-serial converter, a correlator, a second random bit generator and a chaos generator; the chaotic generator is connected with the chaotic generator at the transmitting end.
2. The chaotic multi-access OFDM secure communication system of claim 1, wherein the chaotic generator is synchronized with a corresponding chaotic generator.
3. The chaotic multi-access OFDM secure communication system of claim 2, wherein the chaotic signal output by the chaotic generator is subjected to 8-bit sampling coding by the first random bit generator to generate high-speed random bits.
4. The chaotic multiple access with OFDM secure communication system of claim 3, wherein the high speed bit stream generated by the first random bit generator is multiplied by low speed information, and the low speed information is modulated onto the corresponding wideband high speed bits.
5. The chaotic multiple access OFDM secure communication system according to any one of claims 1 to 4, wherein the first multiplier outputs high-speed wideband information, transmits the high-speed wideband information to the first mapper, maps various bit combinations into two symbol data according to a mapping rule of Gray codes, multiplies edges by cos ω t and sin ω t, performs subtraction by a subtractor to complete Quadrature Amplitude Modulation (QAM), obtains a QAM symbol sequence, and adds a pilot training sequence.
6. The chaotic multiple access OFDM secure communication system of claim 5, wherein at the transmitting end, the symbol sequence formed by the subtracter converts the serial symbol sequence into a parallel symbol stream through a serial-to-parallel converter; performing inverse fast Fourier transform by using an IFFT converter, and converting a frequency spectrum expression of data into a time domain; every N serial-parallel converted symbols are modulated by different subcarriers; the time domain symbol output by the IFFT converter is converted into a serial signal through a first parallel-serial converter, passes through a first filter and a first cyclic prefix importer, cuts off a negative power part by using a first direct current biaser, and is converted into an optical signal through a first photoelectric modulator.
7. The chaotic multiple access OFDM secure communication system according to any one of claims 1 to 4, wherein at a receiving end, after information is amplified by the first erbium-doped fiber amplifier, an optical signal is converted into an electrical signal by the first photodetector, the negative power portion is restored by the second DC biaser, the negative power portion is passed through the de-cyclic prefixed device and then filtered by the second filter, and a serial symbol is converted into a parallel symbol by the serial-to-parallel converter.
8. The system according to claim 7, wherein at a receiving end, the frequency domain symbols output by the first FFT converter are converted into j serial symbols through the second parallel-to-serial converter, each of the N symbols is divided into two paths, each of the two paths is multiplied by cos ω t and sin ω t, the integration is performed, the pilot training sequence is subtracted, and the j path is obtained as xj,yj；xj，yjThe corresponding bit combination is restored through a second mapper, and then the bit stream spread by the corresponding random bit is obtained through a third parallel-to-serial converter.
9. The chaotic multi-access OFDM secure communication system as claimed in any of claims 1-4, wherein at the receiving end, the chaotic signal output by the chaotic generator is subjected to 8-bit sampling coding by the second random bit generator to generate high-speed random bits.
10. The system according to claim 9, wherein at the receiving end, the high-speed random bits and the recovered spreading sequence are cross-correlated by a cross-correlator, and when an information bit is cross-correlated, the cross-correlation coefficient is determined to be 1 when approaching 1, and is determined to be 0 when approaching-1.
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| 陈瑞兰;毕美华;付小松;卓先好;杨国伟;杨学林;: ""OFDM-PON系统中基于混沌映射的密钥保护和PAPR降低的加密算法"", 《光电子・激光》, no. 2018, pages 1167 - 1172 * |
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