CN113612672A - Asynchronous single-wire audio transmission circuit and audio transmission method - Google Patents
Asynchronous single-wire audio transmission circuit and audio transmission method Download PDFInfo
- Publication number
- CN113612672A CN113612672A CN202110892258.7A CN202110892258A CN113612672A CN 113612672 A CN113612672 A CN 113612672A CN 202110892258 A CN202110892258 A CN 202110892258A CN 113612672 A CN113612672 A CN 113612672A
- Authority
- CN
- China
- Prior art keywords
- slave
- host
- audio
- data
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 76
- 238000000034 method Methods 0.000 title claims abstract description 12
- 230000006854 communication Effects 0.000 claims abstract description 22
- 238000004891 communication Methods 0.000 claims abstract description 20
- 238000007906 compression Methods 0.000 claims abstract description 19
- 230000006835 compression Effects 0.000 claims abstract description 19
- 230000005236 sound signal Effects 0.000 claims abstract description 19
- 230000003595 spectral effect Effects 0.000 claims description 15
- 238000013139 quantization Methods 0.000 claims description 12
- 230000009466 transformation Effects 0.000 claims description 9
- 238000004364 calculation method Methods 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000013144 data compression Methods 0.000 claims description 3
- 238000001914 filtration Methods 0.000 claims description 3
- 238000001228 spectrum Methods 0.000 claims description 3
- 230000002457 bidirectional effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R3/00—Circuits for transducers, loudspeakers or microphones
Abstract
The invention discloses an asynchronous single-wire audio transmission circuit and an audio transmission method, wherein the transmission circuit comprises a host and a slave, and the host and the slave adopt single-wire communication for audio transmission; the host end compresses the dual-channel audio signal and transmits the dual-channel audio signal to the slave end through a single bus; the slave terminal decompresses the received data in real time to realize the reconstruction of audio signals, and finally outputs audio to the earphone through the CODEC; and the slave terminal compresses the single-channel microphone data and transmits the single-channel microphone data to the host through the single bus, and the host decompresses the single-channel microphone data in real time to realize reconstruction of the microphone signal. The invention improves the transmission rate through the accurate synchronization of the clock, reduces the audio transmission data volume through the audio compression, ensures the reliable transmission of data stream through a specific protocol, and finally can realize the 48K/16Bit bidirectional audio transmission.
Description
Technical Field
The invention relates to a communication circuit, in particular to an asynchronous single-wire audio transmission circuit and an audio transmission method.
Background
The collection, processing and transmission of acoustic data are important components of multimedia technology. Numerous digital audio systems have entered the consumer market, such as digital audio tapes, digital sound processors. For equipment and manufacturers, the standardized information transmission structure can improve the adaptability of the system. In the prior art, an I2S (Inter-IC Sound) bus is a bus standard established by philips for audio data transmission between digital audio devices, and the bus is dedicated to data transmission between audio devices and is widely used in various multimedia systems. However, in this method, audio transmission is realized by using a synchronous multiline method, and a separate audio interface needs to be provided.
Although digital audio transmission is typically accomplished through an I2S, USB, or other synchronous multi-wire interface circuit. However, due to some electronic devices, such as tablet computers, in order to reduce the complexity of the interface, a single bus interface is adopted externally. The traditional single bus interface can only realize simple data transmission, such as: mouse, keyboard. The prior art also has a circuit for transmitting audio by adopting a single wire, such as CN200910189301.2, which discloses a circuit for realizing single wire transmission of audio and video signals, but the circuit has a complex structure and complex signal processing means, so the realization cost is high. Aiming at the technical defects, the invention develops an asynchronous single-wire audio transmission circuit which can transmit audio signals besides a keyboard and a mouse, and has simple circuit structure, low cost and easy realization.
Disclosure of Invention
Aiming at the problems in the prior art, the invention aims to provide an asynchronous single-wire audio transmission circuit and an audio transmission method which realize audio bidirectional transmission by using a single bus and ensure the stability of data transmission, improve the transmission rate by accurately and synchronously clocking clocks, reduce the audio transmission data volume by audio compression, ensure the reliable transmission of data streams by a specific protocol and finally realize 48K/16Bit bidirectional audio transmission.
The invention provides an asynchronous single-wire audio transmission circuit, which comprises a host and a slave, wherein the host and the slave adopt single-wire communication for audio transmission; the host end compresses the dual-channel audio signal and transmits the dual-channel audio signal to the slave end through a single bus; the slave terminal decompresses the received data in real time to realize the reconstruction of audio signals, and finally outputs audio to the earphone through the CODEC; and the slave terminal compresses the single-channel microphone data and transmits the single-channel microphone data to the host through the single bus, and the host decompresses the single-channel microphone data in real time to realize reconstruction of the microphone signal.
Further, the audio is first compressed using an audio compression algorithm based on MLT transform and vector entropy coding before transmission of the audio, and decompressed after single-line transmission of the audio.
Furthermore, the host computer and the slave computer are both provided with a TX pin and an RX pin, and the circuits of the TX pin and the RX pin of the host computer are combined; the TX pin and the RX pin of the slave are combined through lines; the combined TX pin and RX pin of the host and the TX pin and RX pin of the slave are respectively connected by using a TRX single wire, a first resistor is arranged at one end of the TX pin of the host, and a second resistor is arranged at one end of the TX pin of the slave, so that single-wire communication between the host and the slave is realized; in the communication process, a TX pin of a host is in a DISABLE state by default, IO is configured as input, RX is in an ENABLE state, and TX/RX of a slave is configured as the ENABLE state.
Further, the resistance value of the first resistor is set to be one tenth of the resistance value of the second resistor, and the sum of the resistance values of the first resistor and the second resistor is set to be within the range of 2.7K to 3.3K, so that the master-slave priority of the two communication parties is set, the driving capability of a TX pin of the host is larger than that of a TX pin of the slave, and when the host and the slave send data simultaneously, a signal on a TRX single wire is controlled by the host to ensure that the slave can receive a signal of the host; when the host does not need to send data, the TX pin of the host is set to be in an input high-impedance state by software, the slave can send data to the host through the second resistor with weak driving capability, when the host has data to be sent to the slave, the TX pin of the host is set to be output, and the data is directly sent to the slave without considering the level state of the TX pin of the slave due to the fact that the first resistor at the host end is small and the driving capability is strong.
Further, the sum of the resistances of the first resistor and the second resistor is equal to 3K.
Further, a transmission protocol is set, the transmission protocol ensures that different types of data are sent to the other side, and the types of data include: preamble, command, length, data, and/or check; the RX signals at the host side are simultaneously transmitted to the TIMER or PWM module inside the chip, and each data packet starts with leading 0x 55.
Further, an audio compression algorithm based on MLT transformation and vector entropy coding is adopted to obtain an audio compression ratio of 16:1/10: 1.
Further, the audio compression algorithm based on MLT transform and vector entropy coding specifically comprises the following steps:
firstly, converting a time domain digital voice signal collected by a microphone into a frequency domain spectral coefficient by adopting MLT frequency domain conversion; then, RMS quantization weight calculation is adopted, the frequency domain spectral coefficients are used as the RMS of the grouping calculation signals, and the frequency domain component weight is calculated through the grouping RMS; distributing optimal grouping bits, and obtaining the optimal grouping bits according to the grouping signal frequency domain component weight and the set bit rate parameter; carrying out vector quantization on the grouped frequency domain voice signals to generate grouped vector quantization coefficients; and carrying out Huffman coding on the grouped vector quantization coefficients to complete data compression.
Further, the PCM time domain audio data of the short time frame is converted into MLT frequency domain spectral coefficients by adopting modulation aliasing transformation and MLT transformation, and the MLT frequency domain spectral coefficients are grouped according to frequency domain correlation; the PCM time domain audio data is firstly subjected to 50% data overlapping and mixing processing, then subjected to anti-aliasing filtering to prevent spectrum overflow, and then subjected to DCT-IV transformation to transform the time domain data into frequency domain spectral coefficients.
On the other hand, the invention also provides an asynchronous single-wire audio transmission method which utilizes the asynchronous single-wire audio transmission circuit to realize audio transmission; the host end compresses the dual-channel audio signal and transmits the dual-channel audio signal to the slave end through a single bus; the slave terminal decompresses the received data in real time to realize the reconstruction of audio signals, and finally outputs audio to the earphone through the CODEC; and the slave terminal compresses the single-channel microphone data and transmits the single-channel microphone data to the host through the single bus, and the host decompresses the single-channel microphone data in real time to realize reconstruction of the microphone signal.
The asynchronous single-wire audio transmission circuit and the audio transmission method can reduce the complexity of an interface and ensure the stability of data transmission. The master-slave priority of the two communication parties is realized by setting R1 and R2 with different resistance values for the master machine and the slave machine, so that the driving capability of the TX pin of the master machine is larger than that of the TX pin of the slave machine. The stability of data transmission can be ensured while single-wire communication is realized through a simplified circuit form.
Drawings
FIG. 1 illustrates a schematic block diagram of an asynchronous single-wire audio transmission circuit and method according to the present invention;
fig. 2 shows a transmission protocol and clock accurate synchronization diagram of an asynchronous single-wire audio transmission circuit and method according to the invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
The traditional single bus interface can only realize simple data transmission, such as: mouse, keyboard. In order to transmit audio by using a single bus, the invention develops an asynchronous single-wire audio transmission circuit, the specific structure of which is shown in fig. 1, wherein an MCU in the asynchronous single-wire audio transmission circuit comprises a host and a slave, the host and the slave are both provided with a TX pin and an RX pin, the TX pin of the host is connected with one end of a first resistor R1, and the other end of the first resistor R1 is combined with the RX pin of the host; on the other side of the circuit, a TX pin of the slave is connected with one end of a second resistor R2, and the circuit on the other end of the second resistor R2 is combined with the circuit of an RX pin of the slave; and a single line (called as a TRX line) is used for respectively connecting the combined TX pin and RX pin of the host machine and the TX pin and RX pin of the slave machine.
The two TX/RX wires are combined into one TRX wire to realize single-wire communication. The resistance value of the resistor R1 is one tenth of that of the resistor R2, the sum of the resistance values of the resistors R1+ R2 is in the range of 2.7K to 3.3K, and the sum of the resistance values of the resistors R1+ R2 is preferably equal to 3K, so that the single-bus circuit can be driven by the master and the slave IO only through small driving capability. The IO is configured as input when the TX pin of the host does not send data and is in a DISABLE state, and the IO is configured as output when the TX pin sends data and is in an ENABLE state. The TX pin of the slave is always in the ENABLE state. The RX of the master and the slave is always in an ENABLE state.
When the host needs to send a signal to the slave, the TX pin is enabled, and then data is sent. Since the resistance of R1 is only one tenth of that of R2, TRX is controlled by the master TX no matter what state the slave TX is in.
When the slave needs to send a signal to the master, the RX of the slave can also receive the TRX signal while sending the signal. The slave can judge whether the data is successfully transmitted according to the received RX signal.
The truth table of the signal level state of each pin is as follows:
a schematic diagram of the transmission protocol and the clock fine synchronization is shown in fig. 2. The transmission protocol ensures that different types of data are reliably transmitted to the other side, and the types of data comprise: preamble (SYNC), Command (Command), Length (Length), Data (Data), and/or check (CheckSum).
The RX signals at the host side are simultaneously transmitted to modules capable of capturing, such as TIMER or PWM, inside the chip, and each data packet starts with leading 0x 55. TIMER or PWM captures the time of the level change of the preamble in real time (T0\ T1\ T2 and the like), and calculates the baud rate error of the signals sent by the slave relative to the master. The host-side PLL (fractional PLL) is dynamically adjusted according to the baud rate relative error. And the PLL adjustment enables the baud rate at the host end to be adjusted, and finally the baud rate of the host is accurately synchronized with the baud rate of the slave.
For the stability of audio transmission, firstly, compression processing is carried out before transmission, and an audio compression ratio of 16:1/10:1 can be realized by adopting an audio compression algorithm based on MLT transformation and vector entropy coding. The host end compresses the two-channel audio signal and transmits the two-channel audio signal to the slave end through the single bus. The slave terminal decompresses the received data in real time to realize the reconstruction of the audio signal, and finally outputs the audio to the earphone through the CODEC. And similarly, the slave terminal compresses the single-channel microphone data, transmits the single-channel microphone data to the host through the single bus, decompresses the single-channel microphone data in real time at the host, realizes reconstruction of the microphone signal, and finally transmits the microphone data to the PAD. The key point of the invention is that the audio is transmitted by a single bus, the original audio, the data volume of 48K/16Bit double-track is as follows: 48000 × 16 × 2 ═ 1.536 MBit/S; single buses cannot run at such high speeds, so compression is required, such as: the data size became 153.6KBit/S after 10:1 compression; but the compression can lose the tone quality, and the higher the compression ratio, the worse the tone quality; so 16:1 or 10 can be selected according to different user requirements: 1.
the audio compression algorithm based on MLT transform and vector entropy coding specifically comprises the following steps:
firstly, converting a time domain digital voice signal collected by a microphone into a frequency domain spectral coefficient by adopting MLT frequency domain conversion; then, RMS quantization weight calculation is adopted, the frequency domain spectral coefficients are used as the RMS of the grouping calculation signals, and the frequency domain component weight is calculated through the grouping RMS; distributing optimal grouping bits, and obtaining the optimal grouping bits according to the grouping signal frequency domain component weight and the set bit rate parameter; carrying out vector quantization on the grouped frequency domain voice signals to generate grouped vector quantization coefficients; and carrying out Huffman coding on the grouped vector quantization coefficients to complete data compression.
Adopting modulation aliasing transformation, converting PCM time domain audio data of a short time frame into MLT frequency domain spectral coefficients through MLT transformation, and grouping the MLT frequency domain spectral coefficients according to frequency domain correlation; the PCM time domain audio data is firstly subjected to 50% data overlapping and mixing processing, then subjected to anti-aliasing filtering to prevent spectrum overflow, and then subjected to DCT-IV transformation to transform the time domain data into frequency domain spectral coefficients.
The two resistors R1 and R2 of the circuit have two main functions, the first one is to protect the TX pins of the MCU of both communication sides from level conflict and IO. On the premise of not increasing the resistance, if the TX/RX pins of the two MCUs are directly connected together, a situation that the TX pin of the host computer is at a high level and the TX pin of the slave computer is at a low level may occur, and this situation may cause IO overload damage of the MCUs. The second is that the master-slave priority of both communication parties can be set, the resistance R1 of the master MCU is small, the driving capability is strong, and the resistance R2 of the slave is large, and the driving capability is weak. When the host does not need to send data, the TX pin of the host is set to be in an input high-impedance state by software, the slave can send data to the host through a resistor with weak driving capability, when the host has data to be sent to the slave, the TX pin of the host is set to be output, and the host can directly send data to the slave without concerning the level state of the TX pin of the slave due to small resistance at the end of the host and strong driving capability.
When the slave TX is 0 and the TX signal of the master is 1, the signal is divided by R1 and R2, and the voltage is R2/(R1+ R2), because R2> R1, the voltage is greater than 1/2VDD, and the RX signal value of the slave is 1. In practical application, if the high level threshold of the RX signal of the slave is greater than 1/2VDD, the resistance of R1/R2 can be adjusted to achieve reliable signal transmission. When the TX signal of the master is 0, the slave RX signal level is 0.
When the slave TX is 1 and the master TX signal is 0, the voltage on the TRX is equivalent to VDD and is divided by R2 and R1, and the voltage value is R1/(R1+ R2), because R2> R1, the voltage is less than 1/2VDD, and the RX signal value of the slave is 0. In practical application, if the RX low level signal threshold of the slave is smaller than 1/2VDD, the resistance of R1/R2 can be adjusted to realize reliable signal transmission. When the TX signal of the master is 0, the slave RX signal level is 0.
The RX signal at the host end is simultaneously connected to the pins which can capture signals, such as TIMER or PWM and the like on the host, the time of level change on the pins is captured in real time, and the baud rate of signals sent by the slave is calculated according to the time of the level change, so that the system clock or the baud rate of the serial port of the host is adjusted to adapt to the signals of the slave, the communication reliability is improved, and the problems that the baud rate needs to be fixed in advance and the clock errors of two communication parties cannot be too large in asynchronous serial port communication are solved.
The two-party communication is firstly initiated by the slave and sends 0X55 data at the head of the data, and according to the data format standard of UART, several continuous data pulses with equal width appear on the TRX line. Because the RX pin of the host is also connected with modules with clock acquisition functions such as TIMER or PWM and the like, the time length T0\ T1\ T2 … of output pulse is measured by the clock acquisition modules, and the CPU of the host calculates the accurate baud rate of the slave according to the time of T0\ T1\ T2. And the PLL configuration and the UART configuration of the host are adjusted according to the baud rate, so that the baud rate of the host is matched with that of the slave. The invention has the characteristics that the host computer simultaneously adjusts the PLL setting and the UART setting according to the captured pulse time, thereby avoiding the problem that the host computer can not realize the master-slave baud rate synchronization by independently adjusting the UART setting under some conditions because the slave clock is special or the slave clock has deviation. The adjustment range is wider and the precision is higher. The PLL at the host end is a fractional frequency division PLL, and can output a more accurate system clock according to the requirement.
The invention can make two MCUs with standard two-wire asynchronous serial ports realize single-wire data communication transmission audio by adding part of circuits. Original two TX/RX wires are combined into one TRX wire, and single-wire communication is achieved.
The RX signal of the host end is simultaneously connected to a terminal capable of capturing signals, such as TIMER or PWM, on the host, and the like, and is used for capturing the time of level change on the terminal and calculating the baud rate of signals sent by the slave through the time of the level change, so that the system clock of the host or the baud rate of a serial port is adjusted to adapt to the signals of the slave, and the communication reliability is improved. The invention improves the transmission rate through the accurate synchronization of the clock, reduces the audio transmission data volume through the audio compression, ensures the reliable transmission of data stream through a specific protocol, and finally can realize the 48K/16Bit bidirectional audio transmission.
Claims (10)
1. The asynchronous single-wire audio transmission circuit is characterized by comprising a host and a slave, wherein the host and the slave are in audio transmission by adopting single-wire communication; the host end compresses the dual-channel audio signal and transmits the dual-channel audio signal to the slave end through a single bus; the slave terminal decompresses the received data in real time to realize the reconstruction of audio signals, and finally outputs audio to the earphone through the CODEC; and the slave terminal compresses the single-channel microphone data and transmits the single-channel microphone data to the host through the single bus, and the host decompresses the single-channel microphone data in real time to realize reconstruction of the microphone signal.
2. The asynchronous single-wire audio transmission circuit of claim 1, wherein audio is first compressed using an audio compression algorithm based on MLT transform and vector entropy coding before transmission and decompressed after transmission of the single-wire audio.
3. The asynchronous single wire audio transmission circuit of claim 2, wherein the host and the slave have a TX pin and an RX pin, and the TX pin and the RX pin of the host are combined by a circuit; the TX pin and the RX pin of the slave are combined through lines; the combined TX pin and RX pin of the host and the TX pin and RX pin of the slave are respectively connected by using a TRX single wire, a first resistor is arranged at one end of the TX pin of the host, and a second resistor is arranged at one end of the TX pin of the slave, so that single-wire communication between the host and the slave is realized; in the communication process, a TX pin of a host is in a DISABLE state by default, IO is configured as input, RX is in an ENABLE state, and TX/RX of a slave is configured as the ENABLE state.
4. The asynchronous single-wire audio transmission circuit according to claim 3, wherein the resistance of the first resistor is set to one tenth of the resistance of the second resistor and the sum of the resistances of the first resistor and the second resistor is set to be in a range of 2.7K to 3.3K, so as to set the master-slave priority of both communication parties, so that the driving capability of the TX pin of the master is greater than that of the TX pin of the slave, and when the master and the slave simultaneously transmit data, the signal on the TRX single wire is controlled by the master to ensure that the slave can receive the signal of the master; when the host does not need to send data, the TX pin of the host is set to be in an input high-impedance state by software, the slave can send data to the host through the second resistor with weak driving capability, when the host has data to be sent to the slave, the TX pin of the host is set to be output, and the data is directly sent to the slave without considering the level state of the TX pin of the slave due to the fact that the first resistor at the host end is small and the driving capability is strong.
5. The asynchronous single wire audio transmission circuit of claim 4, wherein the sum of the resistances of the first and second resistors is equal to 3K.
6. The asynchronous single-wire audio transmission circuit according to any of claims 1 to 5, wherein a transmission protocol is provided, said transmission protocol ensuring that different types of data are transmitted to each other, the types of data comprising: preamble, command, length, data, and/or check; the RX signals at the host side are simultaneously transmitted to the TIMER or PWM module inside the chip, and each data packet starts with leading 0x 55.
7. The asynchronous single line audio transmission circuit of any of claims 1 to 5, wherein an audio compression ratio of 16:1/10:1 is obtained using an audio compression algorithm based on MLT transform and vector entropy coding.
8. Asynchronous single-wire audio transmission circuit according to claim 7, characterized in that said audio compression algorithm based on MLT transform and vector entropy coding comprises in particular the steps of:
firstly, converting a time domain digital voice signal collected by a microphone into a frequency domain spectral coefficient by adopting MLT frequency domain conversion; then, RMS quantization weight calculation is adopted, the frequency domain spectral coefficients are used as the RMS of the grouping calculation signals, and the frequency domain component weight is calculated through the grouping RMS; distributing optimal grouping bits, and obtaining the optimal grouping bits according to the grouping signal frequency domain component weight and the set bit rate parameter; carrying out vector quantization on the grouped frequency domain voice signals to generate grouped vector quantization coefficients; and carrying out Huffman coding on the grouped vector quantization coefficients to complete data compression.
9. The asynchronous single line audio transmission circuit of claim 8, wherein PCM time domain audio data of short time frames are converted into MLT frequency domain spectral coefficients by MLT transform using modulation aliasing transform, the MLT frequency domain spectral coefficients are grouped by frequency domain correlation; the PCM time domain audio data is firstly subjected to 50% data overlapping and mixing processing, then subjected to anti-aliasing filtering to prevent spectrum overflow, and then subjected to DCT-IV transformation to transform the time domain data into frequency domain spectral coefficients.
10. An asynchronous single-wire audio transmission method, characterized in that, it uses the asynchronous single-wire audio transmission circuit of claims 1-9 to realize the audio transmission; the host end compresses the dual-channel audio signal and transmits the dual-channel audio signal to the slave end through a single bus; the slave terminal decompresses the received data in real time to realize the reconstruction of audio signals, and finally outputs audio to the earphone through the CODEC; and the slave terminal compresses the single-channel microphone data and transmits the single-channel microphone data to the host through the single bus, and the host decompresses the single-channel microphone data in real time to realize reconstruction of the microphone signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110892258.7A CN113612672A (en) | 2021-08-04 | 2021-08-04 | Asynchronous single-wire audio transmission circuit and audio transmission method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110892258.7A CN113612672A (en) | 2021-08-04 | 2021-08-04 | Asynchronous single-wire audio transmission circuit and audio transmission method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113612672A true CN113612672A (en) | 2021-11-05 |
Family
ID=78306866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110892258.7A Pending CN113612672A (en) | 2021-08-04 | 2021-08-04 | Asynchronous single-wire audio transmission circuit and audio transmission method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113612672A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112948308A (en) * | 2021-02-05 | 2021-06-11 | 杭州微纳科技股份有限公司 | Asynchronous single-wire communication interface circuit |
| CN115033508A (en) * | 2022-06-21 | 2022-09-09 | 珠海昇生微电子有限责任公司 | Single-wire bidirectional direct communication circuit and method between PADs in chip |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008061006A (en) * | 2006-08-31 | 2008-03-13 | Aiphone Co Ltd | Intercom device |
| US20090086983A1 (en) * | 2007-09-27 | 2009-04-02 | Lear Corporation Gmbh | Method and system for transmitting audio signals |
| CN101820372A (en) * | 2010-03-17 | 2010-09-01 | 浙江大学 | TDM (Time Division Multiplexing) single-bus communication system of power supply, data signals and audio analog signals |
| KR20110049050A (en) * | 2009-11-04 | 2011-05-12 | 주식회사 아이닉스 | Method and apparatus for transmitting audio and video signal by one transmitting line |
| CN102111602A (en) * | 2009-12-23 | 2011-06-29 | 康佳集团股份有限公司 | Circuit for realizing single wire transmission of audio and video signals |
| US20130124763A1 (en) * | 2011-10-05 | 2013-05-16 | Analog Devices, Inc. | Methods for Discovery, Configuration, and Coordinating Data Communications Between Master and Slave Devices in a Communication System |
| CN203661051U (en) * | 2013-12-15 | 2014-06-18 | 郑州新力光电技术有限公司 | Unibus-based half-duplex voice intercommunication apparatus |
| CN105068480A (en) * | 2015-08-07 | 2015-11-18 | 任军军 | Audio signal/ data unibus multiplexing intelligent pickup system |
| CN105957533A (en) * | 2016-04-22 | 2016-09-21 | 杭州微纳科技股份有限公司 | Speech compression method, speech decompression method, audio encoder, and audio decoder |
| CN106101903A (en) * | 2016-08-09 | 2016-11-09 | 杭州纳雄科技有限公司 | Numeral headset, headset system and control method thereof |
| CN107333339A (en) * | 2017-05-16 | 2017-11-07 | 恒玄科技（上海）有限公司 | Audio data transmission method and double wireless headsets between a kind of pair of wireless headset |
| CN110650421A (en) * | 2018-06-26 | 2020-01-03 | 深圳市智汇声科技有限公司 | Hearing assistance system and host and slave thereof |
| CN112637438A (en) * | 2020-12-17 | 2021-04-09 | 中科上声（苏州）电子有限公司 | Single-line transmission-based entrance guard double-end intercom method and system |
| CN112948308A (en) * | 2021-02-05 | 2021-06-11 | 杭州微纳科技股份有限公司 | Asynchronous single-wire communication interface circuit |
-
2021
- 2021-08-04 CN CN202110892258.7A patent/CN113612672A/en active Pending
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008061006A (en) * | 2006-08-31 | 2008-03-13 | Aiphone Co Ltd | Intercom device |
| US20090086983A1 (en) * | 2007-09-27 | 2009-04-02 | Lear Corporation Gmbh | Method and system for transmitting audio signals |
| KR20110049050A (en) * | 2009-11-04 | 2011-05-12 | 주식회사 아이닉스 | Method and apparatus for transmitting audio and video signal by one transmitting line |
| CN102111602A (en) * | 2009-12-23 | 2011-06-29 | 康佳集团股份有限公司 | Circuit for realizing single wire transmission of audio and video signals |
| CN101820372A (en) * | 2010-03-17 | 2010-09-01 | 浙江大学 | TDM (Time Division Multiplexing) single-bus communication system of power supply, data signals and audio analog signals |
| US20130124763A1 (en) * | 2011-10-05 | 2013-05-16 | Analog Devices, Inc. | Methods for Discovery, Configuration, and Coordinating Data Communications Between Master and Slave Devices in a Communication System |
| CN203661051U (en) * | 2013-12-15 | 2014-06-18 | 郑州新力光电技术有限公司 | Unibus-based half-duplex voice intercommunication apparatus |
| CN105068480A (en) * | 2015-08-07 | 2015-11-18 | 任军军 | Audio signal/ data unibus multiplexing intelligent pickup system |
| CN105957533A (en) * | 2016-04-22 | 2016-09-21 | 杭州微纳科技股份有限公司 | Speech compression method, speech decompression method, audio encoder, and audio decoder |
| CN106101903A (en) * | 2016-08-09 | 2016-11-09 | 杭州纳雄科技有限公司 | Numeral headset, headset system and control method thereof |
| CN107333339A (en) * | 2017-05-16 | 2017-11-07 | 恒玄科技（上海）有限公司 | Audio data transmission method and double wireless headsets between a kind of pair of wireless headset |
| CN110650421A (en) * | 2018-06-26 | 2020-01-03 | 深圳市智汇声科技有限公司 | Hearing assistance system and host and slave thereof |
| CN112637438A (en) * | 2020-12-17 | 2021-04-09 | 中科上声（苏州）电子有限公司 | Single-line transmission-based entrance guard double-end intercom method and system |
| CN112948308A (en) * | 2021-02-05 | 2021-06-11 | 杭州微纳科技股份有限公司 | Asynchronous single-wire communication interface circuit |
Non-Patent Citations (1)
| Title |
|---|
| 雷学堂等: "基于单片机实现的单总线病房对讲系统", 《山东理工大学学报(自然科学版)》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112948308A (en) * | 2021-02-05 | 2021-06-11 | 杭州微纳科技股份有限公司 | Asynchronous single-wire communication interface circuit |
| CN115033508A (en) * | 2022-06-21 | 2022-09-09 | 珠海昇生微电子有限责任公司 | Single-wire bidirectional direct communication circuit and method between PADs in chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101578472B1 (en) | Systems and methods for duplex communication | |
| US9448959B2 (en) | Two-wire communication protocol engine | |
| CN113612672A (en) | Asynchronous single-wire audio transmission circuit and audio transmission method | |
| WO2020239109A1 (en) | Mipi d-phy transmission circuit and device | |
| CN100418335C (en) | Data transfer control device and electronic instrument | |
| US10645553B2 (en) | Method and apparatus for processing signal in a mobile device | |
| JP2003005874A (en) | Card interface | |
| WO2020151445A1 (en) | Data transmission apparatus, device, and system, and data reception apparatus and device | |
| CN110336970A (en) | A kind of circuit and its signal synthesis method of multiple signals interface | |
| CN101951499B (en) | Network camera | |
| US11768786B2 (en) | Connection interface conversion chip, connection interface conversion device and operation method | |
| US7546518B2 (en) | Received data compensating device | |
| CN201781582U (en) | Network camera | |
| WO2010139273A1 (en) | Method, device and system for multiplexing and demultiplexing multi-channel signals | |
| JP2023553613A (en) | Systems and techniques for line diagnostics | |
| CN206442460U (en) | A kind of Portable HDMI video capture device based on FPGA | |
| CN106791547B (en) | Portable HDMI video acquisition device and method based on FPGA | |
| CN111258946A (en) | Communication method of GTX and TLK2711 series chips | |
| CN205123876U (en) | Medical camera signal switchover control board | |
| CN219372491U (en) | Signal transmission structure and endoscope system based on FPGA | |
| CN217522832U (en) | UWB-based low-delay lossless digital audio transmission unit, system and electronic equipment | |
| CN219329775U (en) | Long-distance communication circuit for MIPI camera | |
| CN219875937U (en) | communication circuit | |
| CN216981995U (en) | Circuit for reducing SDI output signal jitter | |
| CN108710481B (en) | USB wired co-screen system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20211105 |