CN113611704A - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
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- CN113611704A CN113611704A CN202110031071.8A CN202110031071A CN113611704A CN 113611704 A CN113611704 A CN 113611704A CN 202110031071 A CN202110031071 A CN 202110031071A CN 113611704 A CN113611704 A CN 113611704A
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- semiconductor layer
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- semiconductor
- region
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 116
- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 230000015654 memory Effects 0.000 claims abstract description 92
- 239000000758 substrate Substances 0.000 claims description 21
- 125000006850 spacer group Chemical group 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 abstract description 16
- 238000005530 etching Methods 0.000 abstract description 9
- 238000002513 implantation Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 152
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention discloses a method for manufacturing a semiconductor structure. A memory cell is formed on the memory region and a first semiconductor layer is formed on the memory region and the logic device region and covers the memory cell. A cover layer is formed on the first semiconductor layer on the logic device region, and a second semiconductor layer is formed on the memory region and the logic device region and covers the cover layer. A planarization process is performed to remove a portion of the second semiconductor layer and a portion of the first semiconductor layer until the masking layer and the memory cell are exposed. And performing an etching back process on the second semiconductor layer and the first semiconductor layer on the memory region by using the masking layer as a mask. The masking layer is removed, and then an implantation process is performed on the first semiconductor layer on the memory region and the logic device region.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a method for fabricating a semiconductor structure including an embedded memory.
Background
A non-volatile memory (non-volatile memory) is a memory element used for storing structural data, program data, etc. in various electronic devices, wherein a flash memory has the advantages of being capable of performing operations such as storing, reading, and erasing data for many times, and the stored data will not disappear after power is turned off, and is a non-volatile memory (non-volatile memory) element widely used in personal computers and electronic devices.
In order to meet the requirements of reducing the cost and simplifying the manufacturing process steps, a trend of integrating a memory cell (memory cell) and a logic circuit element on the same chip is gradually becoming a trend, which is called an embedded flash memory. How to integrate and fabricate memory cells and logic circuit devices is an important issue in the art.
Disclosure of Invention
The present invention is directed to a method for fabricating a semiconductor structure integrated with an embedded memory and a logic circuit device.
The embodiment of the invention discloses a manufacturing method of a semiconductor structure, which comprises the following steps. First, a substrate is provided, which includes a memory area and a logic device area. Then, a memory cell is formed on the memory region of the substrate. Then, a first semiconductor layer is formed on the memory area and the logic element area and covers the memory unit. Then, a cover layer is formed on the first semiconductor layer on the logic device region, and a second semiconductor layer is formed on the memory region and the logic device region and covers the cover layer. Then, a planarization process is performed to remove a portion of the second semiconductor layer and a portion of the first semiconductor layer until the masking layer and the memory cell are exposed, and an etch-back process is performed on the second semiconductor layer and the first semiconductor layer on the memory region using the masking layer as a mask. After the etching back process, the covering layer is removed, and then an injection process is performed on the first semiconductor layer on the memory region and the logic element region.
Drawings
Fig. 1 to 9 are schematic cross-sectional views of a semiconductor structure at different steps of a manufacturing process according to an embodiment of the present invention;
FIG. 10 is a flowchart illustrating a method of fabricating a semiconductor structure according to one embodiment of the present invention.
Description of the main elements
10 base
10A memory area
10B logic element area
12 isolation structure
14 active (active) region
16 dielectric layer
20 memory cell
22 floating gate
24 dielectric layer
24a oxide layer
24b nitride layer
24c oxide layer
26 control grid
28 hard mask layer
29 spacer
30 first semiconductor layer
32 cover layer
34 second semiconductor layer
36 patterned photoresist layer
38 patterned photoresist layer
30A gate structure
30B character line
30C erase gate
E junction
H1 step difference
H2 step difference
H3 step difference
H4 step difference
P1 planarization process
P2 etch-back process
P3 implantation process
200 method
202 step
206 step
212 step
214 step
216 step
218 step
Detailed Description
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below. The accompanying drawings are all schematic and not drawn to scale, and the same or similar features are generally described with the same reference numerals. The embodiments and figures described herein are for reference and illustration purposes only and are not intended to be limiting of the invention. The scope of coverage of this patent is defined by the claims. The scope of the invention is to be considered as the same as the scope of the claims.
Fig. 1-9 are cross-sectional views of a semiconductor structure at various steps of a fabrication process according to an embodiment of the invention. FIG. 10 is a flowchart illustrating a method of fabricating a semiconductor structure according to one embodiment of the present invention. For ease of understanding, the following description will make simultaneous reference to the semiconductor structures shown in fig. 1 to 7 with respect to the fabrication method shown in fig. 10.
Referring to fig. 10, a method 200 for fabricating a semiconductor structure according to an embodiment of the invention first proceeds to step 202, where a substrate including a memory region and a logic device region is provided. Next, in step 204, a memory cell is formed on the memory region of the substrate. Then, in step 206, a first semiconductor layer is formed on the memory region and the logic device region and covers the memory cell.
As shown in fig. 1, the substrate 10 may be a substrate made of a semiconductor material, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The substrate 10 includes a memory area 10A and a logic element area 10B. A plurality of isolation structures 12 (e.g., shallow trench isolation structures) may be disposed in the substrate 10, so as to divide the memory region 10A and the logic device region 10B of the substrate 10 into a plurality of active regions 14. The active regions 14 are regions for fabricating semiconductor devices, such as transistors or memories, respectively. The isolation structure 12 may comprise an insulating material, such as silicon oxide or silicon nitride. The surface of each active region 14 of the substrate 10 may be covered by a dielectric layer 16, such as silicon oxide or other dielectric material. Although not shown, it is understood that in some embodiments, the dielectric layer 16 may have different thicknesses over different active regions 14. As shown in fig. 1, the substrate 10 may include a plurality of well regions 16, and the well regions 16 may have appropriate concentrations of dopants according to device requirements, and may have N-type or P-type conductivity types, respectively.
The memory cells 20 may be formed on the memory region 10A of the substrate 10 by a semiconductor fabrication process such as, but not limited to, thin film deposition, photolithography, etching, and the like. It should be understood that a plurality of memory cells 20 may be disposed on the memory area 10A, and only one of the memory cells 20 is shown in the figure for simplicity. According to an embodiment of the present invention, the memory cell 20, such as a flash memory (flash memory) cell, may include a floating gate 22 disposed on the substrate 10, a control gate 26 disposed on the floating gate 22, a hard mask layer 28 disposed on the control gate 22, and a dielectric layer 24 disposed between the floating gate 22 and the control gate 26.
The floating gate 22c and the control gate 26 may comprise a semiconductor material, such as polysilicon, in accordance with an embodiment of the present invention. Hard mask layer 28 may comprise a dielectric material, such as silicon nitride. The dielectric layer 24 may be selected to include a single layer or a multiple layer structure depending on the design of the memory cell 20. In the present embodiment, the dielectric layer 24 includes a multi-layer structure, and is composed of an oxide layer 24a, an oxide layer 24c, and a nitride layer 24b interposed therebetween, so the dielectric layer 24 may also be referred to as an oxide-nitride-oxide (ONO) dielectric layer. The oxide layer 24a and the oxide layer 24c are, for example, silicon oxide layers, and the nitride layer 24b is, for example, a silicon nitride layer, but not limited thereto. The spacers 29 may comprise a dielectric material such as, but not limited to, silicon oxide or silicon nitride, and may comprise a multi-layer structure.
The first semiconductor layer 30 is a polysilicon layer formed on the substrate 10 by a deposition process, for example. Since the memory area 10A is provided with the memory cell 20, there is a step difference H1 between the surface of the first semiconductor layer 30 in the memory area 10A (e.g., the surface of the first semiconductor layer 30 covering the memory cell 20) and the surface of the first semiconductor layer 30 covering the logic element area 10B.
Please refer to fig. 10. The method 200 continues with block 208 in which a cap layer is formed on the first semiconductor layer over the logic device region.
As shown in fig. 2, after the first semiconductor layer 30 is formed, a cover layer 32 is formed to cover the first semiconductor layer 30 in the logic device region 10B and expose the first semiconductor layer 30 in the memory region 10A. The masking layer 32 may be formed, for example, by depositing a masking layer material on the substrate 10 to cover the memory region 10A and the logic device region 10B globally, and then performing a patterning process (e.g., a photolithography and etching process) on the masking layer material to remove the masking layer material on the memory region 10A, so as to obtain the masking layer 32 shown in fig. 2. The capping layer 32 includes a material different from that of the first semiconductor layer 30, and has to have an etching selectivity with respect to the first semiconductor layer 30. According to one embodiment of the present invention, the capping layer 32 comprises silicon oxide.
Please refer to fig. 10. The method 200 continues with step 210 in which a second semiconductor layer is formed over the memory region and the logic device region and covers the cap layer.
As shown in fig. 3, the second semiconductor layer 34 entirely covers the first semiconductor layer 30 in the memory area 10A and the logic element area 10B of the substrate 10 and the cap layer 32 in the logic element area 10B. The second semiconductor layer 34 preferably comprises the same material as the first semiconductor layer 30, such as a polysilicon layer formed by a deposition process. There will be a step difference H2 between the second semiconductor layer 34 overlying the first semiconductor layer 30 in the memory region 10A and the second semiconductor layer 34 overlying the cap layer 32 in the logic element region 10B. Since the logic element region 10B is provided with the cover layer 32, the step difference H2 is smaller than the step difference H1.
Please refer to fig. 10. The method 200 continues with block 212 in which a planarization process is performed to remove a portion of the second semiconductor layer until the cap layer and the memory cell are exposed.
As shown in fig. 4, after forming the second semiconductor layer 34, a planarization process P1 is performed on the second semiconductor layer 34 to remove a portion of the second semiconductor layer 34 and a portion of the first semiconductor layer 30 until the surface of the cap layer 32 and the top surface of the memory cell 20 (e.g., the top surface of the hard mask layer 28) are exposed. In accordance with an embodiment of the present invention, the planarization process P1 is, for example, a Chemical Mechanical Polishing (CMP) process using the capping layer 32 as a polishing stop layer. After the planarization process P1, as shown in fig. 4, the remaining second semiconductor layer 34 is located outside the first semiconductor layer 30 on both sides of the memory cell 20, covering a portion of the first semiconductor layer 30. In other words, the first semiconductor layer 30 adjacent to the two sides of the memory cell 20 is exposed from the surface of the second semiconductor layer 34, and has an interface E with the second semiconductor layer 34. After the planarization process P1, the exposed surface of the first semiconductor layer 30 and the surface of the second semiconductor layer 34 in the memory region 10A are substantially flush with the top surface of the memory cell 20, and have a step H3 with the surface of the remaining cap layer 32 in the logic device region 10B. Step H3 is less than step H2 and is also less than step H1.
Please refer to fig. 10. The method 200 continues with step 214 in which an etch-back process is performed on the second semiconductor layer and the first semiconductor layer on the memory region using the masking layer as a mask.
As shown in fig. 5, after the planarization process P1, the masking layer 32 is used as an etching mask to etch back the second semiconductor layer 34 and the first semiconductor layer 30 in the memory region 10A, such as an anisotropic dry etching process P2. According to some embodiments of the present invention, the etch-back process P2 completely removes the second semiconductor layer 34 and a portion of the first semiconductor layer 30 until the surfaces of the first semiconductor layer 30 adjacent to the two sides of the memory cell 20 are flush with or lower than the surface of the first semiconductor layer 30 in the logic element region 10B. According to an embodiment of the present invention, the surface of the first semiconductor layer 30 adjacent to the two sides of the memory cell 20 is lower than the surface of the first semiconductor layer 30 in the logic device region 10B after the etch-back process P2, and has a step H4.
Please refer to fig. 10. The method 200 continues with step 216 in which the masking layer is removed. As shown in fig. 6, after the etch-back process P2, the cover layer 32 may be removed by a dry etching or wet etching process that is selective to the first semiconductor layer 30, the spacers 29, and the hard mask layer 28, thereby exposing the first semiconductor layer 30 in the logic device region 10B.
Please refer to fig. 10. The method 200 continues with block 218 in which an implantation process is performed on the first semiconductor layer over the memory region and the logic device region.
As shown in fig. 7, after the masking layer 32 is removed, a patterned photoresist layer 36 may be selectively formed to cover a portion of the first semiconductor layer 30, and then an implantation process P3 is performed using the patterned photoresist layer 36 as an implantation mask to implant dopants (e.g., carbon or other suitable dopants) into the portion of the first semiconductor layer 30 not covered by the patterned photoresist layer 36, so as to adjust the properties of the portion of the first semiconductor layer 30, such as adjusting the conductivity, or adjusting the threshold voltage of a semiconductor device including a gate structure fabricated from the portion of the first semiconductor layer 30.
Subsequently, as shown in fig. 8 and 9, after removing the patterned photoresist layer 36, a patterning process (e.g., a photolithography and etching process) may be performed on the first semiconductor layer 30 to pattern the first semiconductor layer 30 in the memory area 10A into the word lines 30B and to pattern the first semiconductor layer 30 in the logic device area 10B into a plurality of gate structures 30A. The method of patterning the first semiconductor layer 30 may, for example, form a patterned photoresist layer 38 covering a portion of the first semiconductor layer 30, then etch and remove the first semiconductor layer 30 exposed from the patterned photoresist layer, transfer the pattern of the patterned photoresist layer 38 into the first semiconductor layer 30, and then remove the patterned photoresist layer 38. The word line 30B is located on one side of the memory cell 20, and is separated from the floating gate 22 by the spacer 29 without direct contact, for controlling data writing of the memory cell 20. According to an embodiment of the present invention, an erase gate 30C may also be formed on the other side of the memory cell 20 opposite to the word line 30B by patterning the first semiconductor layer 30 for controlling data erase of the memory cell 20. The gate structures 30A are respectively located on the corresponding active regions 14, and in some embodiments, the gate structures 30A may be channel control gates of logic circuit elements such as transistors.
In summary, one of the features of the present invention is that the masking layer 32 is used as a polishing stop layer and the second semiconductor layer 34 is used as a polishing sacrificial layer to perform a planarization process P1 to obtain a preliminary planarization result, the step H1 (see fig. 1) between the memory region 10A and the logic device region 10B is reduced to the step H3 (see fig. 4), and then the masking layer 32 is used as an etching mask to perform an etch-back process P2 on the semiconductor layers (including the first semiconductor layer 30 and the second semiconductor layer 34) of the memory region 10A, so as to further adjust the step H3 between the memory region 10A and the logic device region 10B, for example, the step H3 is further adjusted to the step H4 (see fig. 5).
Another feature of the present invention is that the dopant (e.g., carbon) that is expected to be implanted into the first semiconductor layer 30 is not implanted into the first semiconductor layer 30 until after the etch back process P2 and the cap layer is removed. Therefore, the material compositions of the first semiconductor layer 30 and the second semiconductor layer 34 etched in the etch-back process P2 are relatively close, which can reduce the problem of etching residues (especially easily generated at the boundary E) generated after the etch-back process P2.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.
Claims (10)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a memory area and a logic element area;
forming a memory cell on the memory region;
forming a first semiconductor layer on the memory region and the logic device region and covering the memory cell;
forming a cover layer on the first semiconductor layer on the logic device region;
forming a second semiconductor layer on the memory region and the logic device region and covering the cap layer;
performing a planarization process to remove a portion of the second semiconductor layer and a portion of the first semiconductor layer until the cover layer and the memory cell are exposed;
taking the cover layer as a mask, and carrying out an etch-back manufacturing process on the second semiconductor layer and the first semiconductor layer on the memory region;
removing the mask layer; and
after removing the covering layer, the first semiconductor layer on the memory area and the logic element area is processed by injection process.
2. The method of claim 1, wherein the memory cell comprises:
a floating gate;
a control gate disposed on the floating gate;
a hard mask layer disposed on the control gate; and
a dielectric layer disposed between the floating gate and the control gate.
3. The method according to claim 2, wherein the dielectric layer is an oxide-nitride-oxide dielectric layer.
4. The method of claim 2, wherein said hard mask layer comprises silicon nitride.
5. The method of claim 2, wherein the memory cell further comprises a pair of spacers disposed on sidewalls of the floating gate, the control gate, the hard mask layer and the dielectric layer.
6. The method according to claim 1, wherein the first and second semiconductor layers comprise polysilicon.
7. The method of claim 1, wherein said capping layer comprises silicon oxide.
8. The method of claim 1, wherein said etch-back process completely removes said second semiconductor layer.
9. The method as claimed in claim 1, wherein after the etch-back process, the thickness of the first semiconductor layer in the memory region is less than the thickness of the first semiconductor layer in the logic device region.
10. The method of fabricating a semiconductor structure according to claim 1, further comprising:
the first semiconductor layer is patterned to form word lines in the memory region and a gate structure in the logic device region.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110031071.8A CN113611704B (en) | 2021-01-11 | 2021-01-11 | Method for manufacturing semiconductor structure |
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| CN202110031071.8A CN113611704B (en) | 2021-01-11 | 2021-01-11 | Method for manufacturing semiconductor structure |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101174593A (en) * | 2006-11-02 | 2008-05-07 | 力晶半导体股份有限公司 | Production method for grid-separating flash memory |
| CN106158862A (en) * | 2015-04-28 | 2016-11-23 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
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- 2021-01-11 CN CN202110031071.8A patent/CN113611704B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101174593A (en) * | 2006-11-02 | 2008-05-07 | 力晶半导体股份有限公司 | Production method for grid-separating flash memory |
| CN106158862A (en) * | 2015-04-28 | 2016-11-23 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
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