CN113611698B - Semiconductor structure and layout thereof - Google Patents

Semiconductor structure and layout thereof Download PDF

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Publication number
CN113611698B
CN113611698B CN202011201934.3A CN202011201934A CN113611698B CN 113611698 B CN113611698 B CN 113611698B CN 202011201934 A CN202011201934 A CN 202011201934A CN 113611698 B CN113611698 B CN 113611698B
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gate
semiconductor
pattern
structures
patterns
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CN113611698A (en
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张维峻
张幼弟
黄清俊
谈文毅
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United Semi Integrated Circuit Manufacture Xiamen Co ltd
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United Semi Integrated Circuit Manufacture Xiamen Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a semiconductor structure and a layout thereof, wherein the semiconductor layout comprises a substrate pattern surrounding an isolation region pattern, a plurality of dummy patterns positioned in the isolation region pattern, a plurality of gate patterns positioned in the isolation region pattern and passing through between the dummy patterns, and a plurality of resistor patterns positioned in the isolation region pattern and overlapped with the gate patterns.

Description

Semiconductor structure and layout thereof
Technical Field
The present invention relates to a semiconductor structure and a layout thereof, and more particularly, to a semiconductor structure including an embedded resistor structure and a semiconductor layout including an embedded resistor pattern.
Background
In advanced semiconductor technology, a system-on-a-chip (SOC) integrates various analog signal circuits, digital signal circuits, and mixed signal circuits into a single chip, which can reduce production cost, increase performance, and reduce power consumption. Products such as personal computers, driving recorders, televisions, mobile phones and the like are all benefited from the design and realization of a system single chip. The system-on-a-chip often includes passive components such as embedded resistors (embedded resistor) for voltage power regulation to enable smooth operation of the circuit. How to successfully integrate and manufacture the embedded resistor in the chip is a subject of active research in the field.
Disclosure of Invention
In order to achieve the above objective, the present invention provides a semiconductor structure including an embedded resistor structure and a semiconductor layout for manufacturing the semiconductor structure, which can improve the manufacturing process margin of the semiconductor structure and the product yield.
An embodiment of the invention provides a semiconductor layout, which comprises a substrate pattern surrounding an isolation region pattern, a plurality of dummy patterns in the isolation region pattern, a plurality of gate patterns in the isolation region pattern and passing through between the dummy patterns, and a plurality of resistor patterns in the isolation region pattern and overlapping the gate patterns.
Another embodiment of the present invention provides a semiconductor structure comprising a substrate including an isolation structure surrounding a plurality of island structures. An interlayer dielectric layer is disposed on the substrate. A plurality of first gate structures are located in the interlayer dielectric layer and on the isolation structures. A plurality of resistive structures are located on the interlayer dielectric layer and aligned with each of the gate structures, respectively, wherein the plurality of gate structures and the plurality of resistive structures comprise different materials.
Drawings
FIG. 1 is a schematic plan view of a semiconductor layout according to an embodiment of the present invention;
FIG. 1A is an enlarged plan view of an area A of the semiconductor layout of FIG. 1;
FIG. 1B is an enlarged schematic plan view of an area B of the semiconductor layout of FIG. 1;
FIG. 2 is a schematic plan view of a semiconductor layout according to an embodiment of the present invention;
FIG. 3 is a schematic plan view of a semiconductor layout according to an embodiment of the present invention;
FIG. 4 is a schematic plan view of a semiconductor layout according to an embodiment of the present invention;
FIG. 5 is a schematic plan view of a semiconductor structure according to an embodiment of the present invention;
fig. 6A is an enlarged plan view of region a of the semiconductor structure of fig. 5;
fig. 6B is an enlarged plan view of region B of the semiconductor structure of fig. 5;
FIG. 7A is a schematic cross-sectional view taken along the line I-I' shown in FIG. 6A through the semiconductor structure;
FIG. 7B is a schematic cross-sectional view of the semiconductor structure taken along line II-II' of FIG. 6B;
FIG. 8A is a schematic cross-sectional view taken along the line I-I' shown in FIG. 6A through the semiconductor structure; fig. 8B is a schematic cross-sectional view taken through the semiconductor structure along the line II-II' shown in fig. 6B.
Description of the main reference signs
102. Base pattern
104. Resistance mark region
106. Dummy pattern
107. Active (active) region pattern
108. Isolation region pattern
110. Gate pattern
111. Gate pattern
112. Resistor pattern
202. Substrate
206. Island-like structure
208. Isolation structure
210. Active region
212. Grid body
213. Spacer wall
214. Work function metal layer
215. Low resistance metal
230. Interlayer dielectric layer
232. Etching stop layer
100a semiconductor layout
100b semiconductor layout
100c semiconductor layout
100d semiconductor layout
200a semiconductor structure
200b semiconductor structure
234a resistor layer
234b hard mask layer
Region A
Region B
D1 First direction
D2 Second direction
D3 Third direction of
G grid structure
G' grid structure
I-I' tangent
II-II' tangent
RS1 grid structure
RS1' gate structure
RS2 resistor structure
S/D source/drain region
Detailed Description
The following description sets forth the preferred embodiments of the present invention and, together with the accompanying drawings, provides a further understanding of the invention, and further details of the construction and the efficacy achieved by the invention, as will be apparent to those of ordinary skill in the art to which the invention pertains. It is to be understood that the following exemplary embodiments may be substituted, rearranged, and mixed in order to accomplish other embodiments without departing from the spirit of the present disclosure.
In order to facilitate the reader's understanding and the brevity of the drawings, the various drawings in this disclosure depict only a portion of the display device, and the specific elements of the drawings are not drawn to actual scale. Furthermore, the number and size of the elements in the drawings are illustrative only and are not intended to limit the scope of the present disclosure. In the drawings, the same or similar elements may be denoted by the same reference numerals. The relative positions of the relative elements in the figures are described herein, and those skilled in the art should understand that they refer to the relative positions of the objects, and thus all may be inverted to present the same components, which are all within the scope of the disclosure.
Fig. 1, 1A and 1B are schematic plan views of a semiconductor layout 100a according to an embodiment of the invention, wherein fig. 1A is an enlarged schematic plan view of a region a of the semiconductor layout 100a, and fig. 1B is an enlarged schematic plan view of a region B of the semiconductor layout 100 a.
The semiconductor layout 100a is an integrated circuit chip (chip) design layout that can be stored and read by a computer system, and includes a plurality of pattern layers for defining a stacked structure of the integrated circuit chip. According to an embodiment of the present invention, the region a of the semiconductor layout 100a is, for example, a passive (inactive) device region including an embedded resistor pattern, and the region B is, for example, an active device region including a transistor, which do not overlap.
Referring to fig. 1A, a region a of the semiconductor layout 100a may include a base pattern 102, an isolation region pattern 108 surrounded by the base pattern 102, a plurality of dummy patterns 106, a plurality of gate patterns 110, and a plurality of resistor patterns 112.
It should be noted that, in a plan view, the shape of the isolation region pattern 108 and the edge thereof are completely surrounded by the substrate pattern 102 are illustrated for the purpose of illustration, and the present invention is not limited thereto. In other embodiments, the isolation region pattern 108 may have a different shape and only a portion of the edge is surrounded by the base pattern 102. In some embodiments, the semiconductor layout 100a further includes a resistive marking region 104 for marking the resistive area of the area a. In some embodiments, the extent of the isolation region pattern 108 of region a substantially overlaps the extent of the resistive marker region 104.
The dummy patterns 106 are located in the isolation region patterns 108, are arranged in an array along the first direction D1 and the second direction D2, and are spaced apart from the edges of the isolation region patterns 108 by a distance, and do not overlap on the edges of the isolation region patterns 108. In some embodiments, the first direction D1 and the second direction D2 are perpendicular to each other. The shape of the dummy pattern 106 may include a rectangle, but is not limited thereto. In some embodiments, the total area of the dummy pattern is greater than 0% and less than 50% of the area of the resistive marker region 104.
The gate patterns 110 are located in the isolation region patterns 108, extend along the first direction D1 and are arranged in parallel along the second direction D2, passing between the dummy patterns 106. The dummy pattern 106 is spaced apart from the edge of the gate pattern 110 by a distance, and the two do not overlap.
The resistive pattern 112 is located in the isolation region pattern 108, extends along the first direction D1 and is arranged in parallel along the second direction D2, passes between the dummy patterns 106, and overlaps the gate pattern 110. In some embodiments, the resistive pattern 112 and the gate pattern 110 may be entirely overlapped.
Referring to fig. 1B, the region B may include a substrate pattern 102, an isolation region pattern 108 surrounded by the substrate pattern 102, an active region pattern 107 surrounded by the isolation region pattern 108, and a gate pattern 111 overlapping the active region pattern 107. The gate pattern 111 extends (e.g., along the first direction D1) across the active region pattern 107.
It should be noted that, the base pattern 102, the isolation region pattern 108 and the dummy pattern 106 of the region a, and the base pattern 102, the isolation region pattern 108 and the active region pattern 107 of the region B are all the same pattern layer belonging to the semiconductor layout 100a, and are output to the same photomask (e.g., base pattern photomask) for patterning the base of the semiconductor structure (e.g., the base 202 of the semiconductor structure 200a of fig. 7A). The gate pattern 110 of region a and the gate pattern 111 of region B belong to the same pattern layer of the semiconductor layout 100a and are output to the same photomask (e.g., gate pattern photomask) for patterning a layer of gate material on the semiconductor structure substrate. The resistive pattern 112 of region a will be output to yet another photomask (e.g., a resistive pattern photomask) for patterning a layer of resistive material of the semiconductor structure.
Referring to fig. 2, 3 and 4, a schematic plan view of a semiconductor layout according to some embodiments of the present invention is illustrated, wherein the layout of the dummy patterns 106 can be adjusted according to the design or manufacturing process requirements. For example, as shown in fig. 2, the edges of the dummy patterns 106 of the semiconductor layout 100b and the edges of the partial gate patterns 110 and the resistive patterns 112 may be overlapped and cut. As shown in fig. 3, the dummy patterns 106 of the semiconductor layout 100c may be aligned along the first direction D1 and staggered along the second direction D2. As shown in fig. 4, the dummy patterns 106 of the semiconductor layout 100D may extend along the extending direction (e.g., the first direction D1) of the gate patterns 110, have substantially the same length as the gate patterns 110, and are staggered with the gate patterns 110 along the second direction D2.
Please refer to fig. 5, 6A, 6B, 7A and 7B. Fig. 5 is a schematic plan view of a semiconductor structure 200a according to an embodiment of the invention, fig. 6A and 6B are enlarged schematic plan views of a region a and a region B of fig. 5, respectively, fig. 7A is a schematic sectional view along a line I-I 'shown in fig. 6A, and fig. 7B is a schematic sectional view along a line II-II' shown in fig. 6B. It should be noted that, for simplicity of illustration, some structures of fig. 7A and 7B (e.g., interlayer dielectric layer 230 and etch stop layer 232) are not shown in fig. 5, 6A and 6B. The semiconductor structure 200a is fabricated, for example, by a semiconductor fabrication process using a set of photomasks including the pattern of the semiconductor layout 100a shown in fig. 1, 1A and 1B.
As shown in fig. 5, the semiconductor structure 200a includes a substrate 202, such as, but not limited to, a silicon substrate, a silicon-on-insulator (SOI) substrate, or other suitable semiconductor substrate. In some embodiments, the substrate is, for example, a silicon wafer. At least region a and region B are defined on the substrate 202. Region a is, for example, a passive device region including an embedded resistor structure, and region B is, for example, an active device region including a transistor, which do not overlap.
As shown in fig. 6A and 7A, the region a of the semiconductor structure 200a includes a substrate 202, an isolation structure 208 surrounded by the substrate 202, a plurality of island-like structures 206 disposed within the isolation structure 208 and surrounded by the isolation structure 208, an interlayer dielectric layer 230 disposed on the substrate 202, a plurality of gate structures RS1 (first gate structures) disposed in the interlayer dielectric layer 230, and a plurality of resistor structures RS2 disposed directly above the gate structures RS1. In some embodiments, the shape of the island structure 206 may include a rectangle in plan view, and be arranged in an array along the first direction D1 and the second direction D2. Island 206 is separated from substrate 202 by isolation structures 208 and is not in direct contact. In some embodiments, the semiconductor structure 200a may include an etch stop layer 232 on the interlayer dielectric layer 230 and covering the gate structure RS1.
As shown in fig. 6B and 7B, the region B includes the substrate 202, another isolation structure 208 surrounded by the substrate 202, an active region 210 surrounded by the isolation structure 208, an interlayer dielectric layer 230 on the substrate 202, a gate structure G (second gate structure) disposed in the interlayer dielectric layer 230 and located on the active region 210, and source/drain regions S/D located in the active region 210 at both sides of the gate structure G. In some embodiments, the gate structure G extends (e.g., along the first direction D1) across the active region 110. In some embodiments, the etch stop layer 232 extends onto the interlayer dielectric layer 230 of region B and covers the gate structure G.
It should be noted that, in the plan view, the shape of the isolation structure 208 and the edge thereof of the region a and the region B shown in fig. 6A and 6B are shown as being completely surrounded by the substrate 202 for illustration purposes, and the present invention is not limited thereto. In other embodiments, the isolation structures 208 may have different top-down shapes and only a portion of the edges are surrounded by the base 202.
The isolation structures 208, island structures 206, and active regions 210 of region a and region B are formed simultaneously on the substrate 202 by the same fabrication process. For example, a photolithography and etching process may be performed using a substrate pattern photomask including the substrate pattern 102, the isolation region pattern 108 and the dummy pattern 106 of the region a of fig. 1A and the substrate pattern 102, the isolation region pattern 108 and the active region pattern 107 of the region B of fig. 1B, transferring the pattern of the photomask into the substrate 202 to form the insulation trench, defining the island structure 206 and the active region 210, depositing a layer of an insulation material (e.g., silicon oxide) on the substrate 202 to fill the insulation trench, and performing a Chemical Mechanical Polishing (CMP) process to remove the excess insulation material outside the insulation trench, thereby obtaining the isolation structure 208 as shown in fig. 7A and 7B.
The gate structure RS1 (first gate structure) and the gate structure G (second gate structure) are located in the interlayer dielectric layer 230 in the region a and the region B, respectively. The gate structure RS1 is located mainly on the isolation structure 208 and between the island structures 206. The gate structure G is located mainly on the active region 210 and extends across the active region 210 and partially on the isolation structure 208. The gate structures RS1 and G respectively include a gate body 212 and spacers 213 disposed on both sides of the gate body 212. Preferably, the gate structures RS1 and G have substantially the same height, and the top surfaces of the two structures are flush with each other.
In some embodiments, the gate structure RS1 and the resistor structure RS2 may be used as embedded resistors of the semiconductor structure 200a, respectively. In other embodiments, the gate structure RS1 may be an electrically floating (floating) dummy structure that is not electrically connected to other components.
The gate structure RS1 and the gate structure G may be simultaneously formed on the substrate 202 through the same manufacturing process. For example, a photolithography and etching process may be performed using a gate pattern photomask including the gate pattern 110 of fig. 1A and the gate pattern 111 of fig. 1B, transferring the pattern of the photomask into a gate material layer on the substrate 202, forming the gate body 212 of the gate structure RS1 and the gate body 212 of the gate structure G at the same time, then depositing a dielectric material layer on the substrate 202 to cover each gate body 212, and performing an anisotropic etching process to remove a portion of the dielectric material layer, so that the remaining dielectric material layer is self-aligned on the sidewalls of each gate body 212 to form the spacers 213.
In some embodiments, gate body 212 may comprise a semiconductor material, such as, but not limited to, polysilicon. The spacers 213 may comprise a single-layer or multi-layer structure, and the material may comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or a combination thereof, but is not limited thereto. In some embodiments, the top of the gate body 212 may include a cap layer (e.g., a silicon nitride cap layer, not shown).
An interlayer dielectric layer 230 is on the substrate 202 and covers the isolation structures 208, island structures 206, and active region 210 of regions a and B. After the gate structures RS1 and G are completed, the interlayer dielectric layer 230 may be formed on the substrate 202 by chemical vapor deposition or other suitable manufacturing process. Interlayer dielectric layer 230 may comprise a dielectric material, such as silicon oxide (SiO) 2 ) An undoped silicate glass (undoped silica glass, USG) or low-k dielectric material such as fluorosilicone glass (fluorinated silica glass, FSG), carbon silicon oxide (SiCOH), spin-on glass (spin-on glass), a porous low-k dielectric material (porius low-k dielectric material), or an organic polymer dielectric material, but is not limited thereto. In some embodiments, interlayer dielectric layer 230 comprises silicon oxide (SiO 2 ). A Chemical Mechanical Polishing (CMP) process may be performed on the interlayer dielectric layer 230 to planarize the interlayer dielectric layer 230. As shown in fig. 7A and 7B, the top of the gate body 212 of the gate structure RS1 and the gate structure G may be exposed from the surface of the interlayer dielectric layer 230.
An etch stop layer 232 is disposed on the interlayer dielectric layer 230 and covers the exposed tops of the gate structures RS1 and G. An etch stop layer 232 may be formed on the planarized interlayer dielectric layer 230 by chemical vapor deposition or other suitable fabrication process. The etch stop layer 232 may comprise a dielectric material, such as silicon oxide (SiO) 2 ) Silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide nitride (SiCN), but is not limited thereto. In some embodiments, etch stop layer 232 comprises silicon oxide (SiO 2 )。
The resistive structure RS2 is located on the etch stop layer 232 and aligned with the gate structure RS1 in a vertical direction (e.g., the third direction D3). Resistive structure RS2 may include a resistive layer 234a and a hard mask layer 234b over resistive layer 234 a. A resistive material layer and a hard mask material layer may be deposited on the etch stop layer 232 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable semiconductor fabrication process, followed by a photolithography and etch process using a resistive pattern photomask including the resistive pattern 112 of fig. 1A, transferring the pattern of the photomask into the resistive material layer and the hard mask material layer, and removing the excess resistive material layer and the hard mask material layer to obtain the resistive layer 234a and the hard mask layer 234b of the resistive structure RS2.
According to some embodiments of the present invention, the resistive layer 234a material may include an alloy (alloy) or a metal compound (metal compound), such as a metal silicide, a metal oxide, a metal nitride, or a combination of the foregoing, but is not limited thereto. According to an embodiment of the present invention, the material of the resistive layer 234a includes titanium nitride (TiN). The hard mask layer 234b is formed of a material having etching selectivity to the etching stopper layer 232. For example, when etch stop layer 232 comprises silicon oxide, hard mask layer 234b may comprise silicon nitride.
It should be noted that, in the foregoing process of fabricating the semiconductor structure 200a, particularly in the Chemical Mechanical Polishing (CMP) process of the isolation structure 208, the top surface of the isolation structure 208 with a large area (or with too low pattern density) is often recessed (dishing), so that the height of the gate material layer on the recess is lower than that of the gate material layer in other areas, which affects the depth of focus, and is easy to cause abnormal patterning, resulting in deformation or line breakage of the gate body 212, or residual gate material layer. In addition, the height of the interlayer dielectric layer 230 on the recess is lower than that of the interlayer dielectric layer 230 in other regions, which results in uneven heights of the resistive material layer and the hard mask material layer, and increases difficulty in patterning the resistive structure RS2.
The invention adjusts the pattern density of the isolation structure 208 by forming the island-shaped structures 206 in the isolation structure 208, preferably, the total area of the island-shaped structures 206 in a plan view accounts for more than 0% and less than 50% of the area of the isolation structure 208, so that the polishing uniformity of a Chemical Mechanical Polishing (CMP) manufacturing process can be improved, the situation that the top surface of the isolation structure 208 is recessed is reduced, the problem that the heights of a gate material layer, a resistor material layer and a hard mask material layer are uneven is further reduced, the patterning manufacturing process of the gate structures RS1, G and the resistor structure RS2 can have better patterning results, and the manufacturing process allowance of the semiconductor structure is improved.
Please refer to fig. 8A and 8B. Fig. 8A is a schematic cross-sectional view of a region a of a semiconductor structure 200B along a tangent line I-I ', and fig. 8B is a schematic cross-sectional view of a region B along a tangent line II-II', according to another embodiment of the present invention. The gate structures RS1 'and G' of the semiconductor structure 200B of fig. 8A and 8B may include metal gates.
The gate structures RS1 'and G' may be formed by a replacement metal gate (replacement metal gate) fabrication process. In some embodiments, the replacement metal gate fabrication process step includes exposing the top of the gate body 212 of the gate structure RS1 and the gate structure G from the surface of the interlayer dielectric 230, and then removing the gate body 212 by a selective etching process (e.g., a wet etching process) to form a plurality of gate trenches. Then, a high-k dielectric layer (not shown), a work function metal layer 214, and a low-resistance metal 215 are sequentially deposited in the gate trench to fill the gate trench, and then a Chemical Mechanical Polishing (CMP) process is performed to remove the excess high-k dielectric layer, work function metal layer 214, and low-resistance metal 215 outside the gate trench, thereby obtaining the gate structure RS1 'of fig. 8A and the gate structure G' of fig. 8B. In some embodiments, the gate structure RS1' and the resistor structure RS2 may be used as embedded resistors of the semiconductor structure 200a, respectively. In other embodiments, the gate structure RS1' may be an electrically floating dummy structure that is not electrically connected to other components.
It should be noted that, in the foregoing replacement metal gate manufacturing process, if the top surface of the isolation structure 208 has a recess, the height of the gate structure RS1 located at the recess is lower than the height of the gate structure (e.g., the gate structure G) in other regions, so that the top of the gate body 212 of the gate structure RS1 is not exposed from the interlayer dielectric layer 230 and cannot be removed, resulting in abnormal metal gate replacement. In addition, the inter-layer dielectric layer 230 on the recess is lower, so that the gate metal layer above the recess is not easy to be polished and removed, resulting in a problem of metal layer residue.
The invention adjusts the pattern density of the isolation structure 208 by forming the island-shaped structure 206 in the isolation structure 208, thereby avoiding the occurrence of a dent on the top surface of the isolation structure 208, leading the gate structure RS1 and the gate structures (such as the gate structure G) in other areas to have more consistent heights, leading the whole interlayer dielectric layer 230 to have more consistent heights, reducing the abnormal replacement of the metal gate or the metal residue, and improving the manufacturing process allowance of the semiconductor structure.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (20)

1. A semiconductor layout is characterized by comprising
A base pattern surrounding the isolation region pattern;
a plurality of dummy patterns in the isolation region pattern and arranged in an array, the plurality of dummy patterns belonging to the same pattern layer as the base pattern;
a plurality of gate patterns entirely located in the isolation region pattern and passing between the plurality of dummy patterns; and
and a plurality of resistor patterns located in the isolation region pattern and overlapping the plurality of gate patterns.
2. The semiconductor layout of claim 1, wherein a percentage of a total area of said plurality of dummy patterns to an area of said isolation region pattern is greater than 0% and less than 50%.
3. The semiconductor layout of claim 1, wherein the plurality of gate patterns extend along a first direction and are arranged in parallel along a second direction.
4. The semiconductor layout of claim 3, wherein the plurality of dummy patterns comprise rectangular shapes and are aligned along the first direction and the second direction.
5. The semiconductor layout of claim 3, wherein said plurality of dummy patterns comprise rectangular shapes and are aligned along said first direction and staggered along said second direction.
6. The semiconductor layout of claim 3, wherein said plurality of dummy patterns extend along said first direction and are staggered with said plurality of gate patterns along said second direction.
7. The semiconductor layout of claim 1, wherein edges of the plurality of gate patterns overlap edge portions of the plurality of dummy patterns.
8. The semiconductor layout of claim 1, wherein the plurality of gate patterns and the plurality of dummy patterns do not overlap at all.
9. The semiconductor layout of claim 1, wherein the plurality of dummy patterns do not overlap entirely with edges of the isolation region pattern.
10. The semiconductor layout of claim 1 wherein the extent of the isolation region pattern overlaps the extent of the resistive marker region.
11. A semiconductor structure, comprising:
a substrate comprising an isolation structure surrounding a plurality of island structures, the plurality of island structures being arranged in an array with a top surface flush with a surface of the substrate;
an interlayer dielectric layer on the substrate;
a plurality of first gate structures located in the interlayer dielectric layer and entirely located on the isolation structure; and
and a plurality of resistor structures located on the interlayer dielectric layer and overlapping each of the first gate structures.
12. The semiconductor structure of claim 11, wherein the plurality of first gate structures comprise polysilicon and the plurality of resistive structures comprise titanium nitride (TiN).
13. The semiconductor structure of claim 11, wherein the plurality of first gate structures comprise a low resistance metal and the plurality of resistive structures comprise titanium nitride (TiN).
14. The semiconductor structure of claim 11, wherein said plurality of first gate structures are electrically floating.
15. The semiconductor structure of claim 11, further comprising a second gate structure in said interlayer dielectric layer and on said active region, wherein said second gate structure is level with top surfaces of said plurality of first gate structures.
16. The semiconductor structure of claim 15, wherein the plurality of first gate structures and the second gate structure comprise polysilicon and the resistive structure comprises titanium nitride (TiN).
17. The semiconductor structure of claim 15, wherein said plurality of first gate structures comprise polysilicon, said second gate structure comprises a low resistance metal, and said resistive structure comprises titanium nitride (TiN).
18. The semiconductor structure of claim 15, wherein the plurality of first gate structures and the second gate structure comprise a low resistance metal, the resistive structure comprising titanium nitride (TiN).
19. The semiconductor structure of claim 11, wherein said plurality of first gate structures do not overlap said plurality of island structures.
20. The semiconductor structure of claim 11, further comprising an etch stop layer between said plurality of first gate structures and said resistive structure.
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