CN113611661B - Method for preparing semiconductor structure and semiconductor structure - Google Patents

Method for preparing semiconductor structure and semiconductor structure Download PDF

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CN113611661B
CN113611661B CN202110880620.9A CN202110880620A CN113611661B CN 113611661 B CN113611661 B CN 113611661B CN 202110880620 A CN202110880620 A CN 202110880620A CN 113611661 B CN113611661 B CN 113611661B
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etching
filling layer
temperature
layer
filling
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CN113611661A (en
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郭帅
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon

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  • Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
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  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
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Abstract

The application relates to a preparation method of a semiconductor structure and the semiconductor structure, wherein the method comprises the following steps: providing an etching structure with a first etching hole; forming a first filling layer in the first etching hole; etching the first filling layer by adopting gradually-increased etching temperature to form a second etching hole in the reserved first filling layer, wherein the width of the second etching hole gradually decreases from top to bottom; and forming a second filling layer in at least the second etching hole, so that the second filling layer in the second etching hole and the reserved first filling layer jointly fill the first etching hole in a seamless manner. The method avoids forming cavities or air gaps in the process of filling the high-depth-to-width ratio holes, and improves the integrity of the manufactured semiconductor structure and the performance of the device.

Description

Method for preparing semiconductor structure and semiconductor structure
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
With the rapid development of integrated circuit processes, the requirements for the integration level of semiconductor products are increasing. With the integration of semiconductor products, the size of semiconductor devices is continuously reduced, and the semiconductor devices are continuously stacked upwards in space, so that the requirements on the filling process of high aspect ratio holes in the process of preparing semiconductors are increasingly higher.
However, conventional hole filling processes have limited filling capability, resulting in voids or air gaps formed during the filling of high aspect ratio holes, ultimately affecting the integrity of the resulting semiconductor structure and device performance.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method for fabricating a semiconductor structure and a semiconductor structure that avoid the formation of voids or air gaps during the filling of high aspect ratio holes and improve the integrity and device performance of the fabricated semiconductor structure.
To achieve the above and other related objects, one aspect of the present application provides a method for manufacturing a semiconductor structure, including the steps of:
providing an etching structure with a first etching hole;
forming a first filling layer in the first etching hole;
etching the first filling layer by adopting gradually-increased etching temperature to form a second etching hole in the reserved first filling layer, wherein the width of the second etching hole gradually decreases from top to bottom;
and forming a second filling layer in at least the second etching hole, so that the second filling layer in the second etching hole and the reserved first filling layer jointly fill the first etching hole in a seamless manner.
In the method for manufacturing a semiconductor structure in the above embodiment, after forming the first filling layer in the first etching hole in the etched structure by using the filling process, the first filling layer is etched by using the gradually increasing etching temperature, so as to form the second etching hole with the width gradually decreasing from top to bottom, for example, the deep "V" shape, in the remaining first filling layer; and forming a second filling layer in at least the second etching hole, so that the second filling layer in the second etching hole and the reserved first filling layer jointly fill the first etching hole in a seamless manner, thereby avoiding forming a cavity or an air gap in the process of filling the high-aspect-ratio hole and improving the integrity of the manufactured semiconductor structure and the performance of a device.
In one embodiment, the etching the first filling layer with the gradually increasing etching temperature includes: in the process of etching the first filling layer, the etching temperature and the etching time are controlled to be changed in a preset heating curve, so that the accurate control of the etching temperature is realized.
In one embodiment, the controlling the etching temperature and the etching time to change in a preset temperature rising curve includes:
controlling the etching temperature and the etching time to change in a proportional relation; or (b)
And controlling the etching temperature and the etching time to be changed in a pulse step-type rising curve.
In one embodiment, the pulse period of the pulse step-type rising curve of the etching temperature and the etching time is controlled to be 3s-5s, so that the complexity of controlling the etching temperature is reduced while the accurate control of the etching temperature is realized.
In one embodiment, the etching the first filling layer with the gradually increasing etching temperature includes: in the process of etching the first filling layer, controlling the flow of etching gas and the etching time to form a preset change curve change so as to cooperatively control the temperature, and forming a second etching hole with the width gradually reduced from top to bottom in the reserved first filling layer.
In one embodiment, the controlling the flow of the etching gas and the etching time to form a preset change curve includes: and controlling the flow of the etching gas and the etching time to be changed in a periodic pulse curve so as to reduce the complexity of controlling the flow of the etching gas.
In one embodiment, the etching the first filling layer with the gradually increasing etching temperature includes: and controlling the etching gas to etch the first filling layer in a plasma mode so as to reduce the complexity of flow control of the etching gas.
In one embodiment, the amplitude corresponding to each period in the periodic pulse curve is controlled to be in a positive semicircular curve change or a positive half-period sine wave curve change, so that the second etching holes with the widths gradually decreasing from top to bottom are formed in the reserved first filling layer in cooperation with temperature control.
In one embodiment, the pulse period of the periodic pulse profile is controlled to be 3s-5s.
In one embodiment, the etching the first filling layer with the gradually increasing etching temperature includes:
and in the process of etching the first filling layer, controlling the etching temperature to gradually rise to a preset temperature.
In one embodiment, the predetermined temperature is 400 ℃ to 450 ℃.
In one embodiment, the filling the first etching hole with the first filling layer includes:
forming a first filling material layer on the upper surface of the etching structure and in the first etching hole, wherein the top surface of the first filling material layer is higher than the top surface of the first etching hole;
and removing the first filling material layer positioned on the etching structure until the top surface of the first filling material layer positioned in the first etching hole is flush with the upper surface of the etching structure, so as to form the first filling layer.
In one embodiment, the removing the first filler material layer on the etched structure includes:
and removing the first filling material layer on the etching structure by adopting a low-temperature flat pushing process to form the first filling layer, and forming the first filling layer with the upper surface flush with the upper surface of the etching structure by utilizing the characteristic of isotropic etching when the etching temperature is low.
In one embodiment, the low temperature flat push process has a flat push temperature of 100 ℃ to 150 ℃.
In one embodiment, forming the second filling layer in at least the second etching hole includes:
and depositing a second filling layer on the upper surface of the etching structure and in the second etching hole, so that the second filling layer in the second etching hole and the reserved first filling layer jointly fill the first etching hole in a seamless manner.
In one embodiment, the method for forming the second filling layer includes any one of low pressure chemical vapor deposition, atomic layer deposition and a combination of atomic layer seed deposition and low pressure chemical vapor deposition.
In one embodiment, the materials of the first filling layer and the second filling layer comprise at least one of phosphorus doped silicon, boron doped silicon, undoped silicon, phosphorus doped germanium silicon, boron doped germanium silicon and undoped germanium silicon.
In one embodiment, the etching gas used to etch the first filling layer at the gradually increasing etching temperature includes at least one of chlorine, hydrogen chloride, chlorine trifluoride, carbon tetrafluoride, hexafluoroethane, perfluoropropane, octafluorocyclobutane, hexafluorobutadiene, octafluorocyclopentene, nitrogen trifluoride, and argon.
Another aspect of the present application provides a semiconductor structure comprising: the semiconductor structure is manufactured by adopting any manufacturing method of the semiconductor structure in the embodiment of the application. After a first filling layer is formed in a first etching hole in an etching structure by using a filling process, etching the first filling layer by adopting an etching temperature which is gradually increased so as to form a second etching hole with the width gradually reduced from top to bottom, for example, a deep V shape, in the reserved first filling layer; and forming a second filling layer in at least the second etching hole, so that the second filling layer in the second etching hole and the reserved first filling layer jointly fill the first etching hole in a seamless manner, thereby avoiding forming a cavity or an air gap in the process of filling the high-aspect-ratio hole and improving the integrity of the manufactured semiconductor structure and the performance of a device.
Drawings
For a better description and illustration of embodiments and/or examples of those applications disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of any of the disclosed applications, the presently described embodiments and/or examples, and the presently understood best mode of carrying out these applications.
FIG. 1 is a flow chart illustrating a method for fabricating a semiconductor structure according to one embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to one embodiment of the present invention, wherein the structure is obtained in step 12;
FIGS. 3 a-3 b are schematic cross-sectional views of the structure obtained in step 14 of a method for fabricating a semiconductor structure according to one embodiment of the present application;
FIG. 4 is a schematic diagram showing a time variation of the etching temperature and the etching gas flow in step 16 in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram showing a time variation curve of etching temperature and etching gas flow in step 16 in a semiconductor structure manufacturing method according to another embodiment of the present disclosure;
FIG. 6a is a schematic cross-sectional view of a semiconductor structure according to one embodiment of the present invention, wherein the structure is obtained in step 16;
FIG. 6b is a schematic cross-sectional view of a structure obtained in a conventional etching process;
FIG. 6c is a schematic cross-sectional view of another conventional etching process;
FIGS. 7 a-7 b are schematic cross-sectional views of the structure obtained in step 18 of a method for fabricating a semiconductor structure according to one embodiment of the present application;
FIG. 8 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure, wherein the structure is obtained in step 18;
reference numerals illustrate:
100. etching the structure; 21. a first etching hole; 22. a first filler layer; 221. a first filler material layer; 23. an air gap; 24. a second etching hole; 25. a groove; 26. etching back the hole; 27. and a second filling layer.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing, the regions illustrated in the figures being schematic in nature, and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
Please refer to fig. 1-8. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the illustration, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Referring to fig. 1, in a method for manufacturing a semiconductor structure according to an embodiment of the present application, the method includes the following steps:
step 12: providing an etching structure with a first etching hole;
step 14: forming a first filling layer in the first etching hole;
step 16: etching the first filling layer by adopting gradually-increased etching temperature to form a second etching hole in the reserved first filling layer, wherein the width of the second etching hole gradually decreases from top to bottom;
step 18: and forming a second filling layer in at least the second etching hole, so that the second filling layer in the second etching hole and the reserved first filling layer jointly fill the first etching hole in a seamless manner.
Specifically, referring to fig. 1, after a first filling layer is formed in a first etching hole in an etching structure by using a filling process, the first filling layer is etched at an gradually increasing etching temperature, so as to form a second etching hole with a width gradually decreasing from top to bottom, for example, a deep V shape, in the remaining first filling layer; and forming a second filling layer in at least the second etching hole, so that the second filling layer in the second etching hole and the reserved first filling layer jointly fill the first etching hole in a seamless manner, thereby avoiding forming a cavity or an air gap in the process of filling the high-aspect-ratio hole and improving the integrity of the manufactured semiconductor structure and the performance of a device.
In step 12, referring to step 12 in fig. 1 and fig. 2, an etching structure 100 is provided, and a first etching hole 21 is formed in the etching structure 100.
As an example, due to the limited filling capability of the conventional hole filling process, resulting in the formation of voids or air gaps, such as the first etching holes 21, during the filling of high aspect ratio holes, the first etching holes 21 shown in fig. 2 are intended to illustrate the implementation principle of the present application, and the number of first etching holes 21 formed may be plural during the actual semiconductor filling process. The application aims to provide a preparation method of a semiconductor structure, which avoids forming cavities or air gaps in the process of filling high aspect ratio holes and improves the integrity of the manufactured semiconductor structure and the performance of a device.
As an example, referring to step 14 in fig. 1, fig. 3a and fig. 3b, forming the first filling layer at least in the first etching hole 21 may include the following steps:
step 141: forming a first filling material layer 221 on the upper surface of the etching structure 100 and in the first etching hole 21, wherein the top surface of the first filling material layer 221 is higher than the top surface of the first etching hole 21;
step 142: the first filling material layer 221 located on the etching structure 100 is removed until the top surface of the first filling material layer 221 located in the first etching hole 21 is flush with the upper surface of the etching structure 100 to form the first filling layer 22.
In this embodiment, the etching process may include a plasma dry etching processAnd (5) art. The parameters of the adopted dry etching process include: the gas comprises fluorocarbon gas, HBr and Cl 2 And a carrier gas, the fluorocarbon gas comprising CF 4 、CHF 3 、CH 2 F 2 Or CH (CH) 3 F, the carrier gas is inert gas, such as He, the gas flow is 50sccm-400sccm, and the pressure is 3 milliTorr-8 milliTorr.
Illustratively, removing the first fill material layer 221 located over the etched structure 100 in step 142 includes:
the first filling material layer 221 on the etched structure 100 is removed by a low-temperature horizontal pushing process to form a first filling layer 22, and the first filling layer 22 with the upper surface flush with the upper surface of the etched structure 100 is formed by utilizing the characteristic of isotropic etching when the etching temperature is low.
As an example, in one embodiment of the present application, the plateau temperature of the low temperature plateau process is 100 ℃ -150 ℃, e.g., the plateau temperature of the low temperature plateau process may be 100 ℃, 110 ℃, 120 ℃, 130 ℃, 140 ℃, or 150 ℃.
As an example, the number of the first etching holes 21 in step 14 may be plural, and the depths of the first etching holes 21 may be the same or different; the width of each first etching hole 21 may be the same or different.
Due to the limited filling capability of conventional hole filling processes, air gaps 23 are formed during the filling of high aspect ratio holes, ultimately affecting the integrity of the resulting semiconductor structure and device performance. The number of air gaps 23 formed during filling of the high aspect ratio holes may be plural, and the air gaps 23 in fig. 3a and 3b are intended to illustrate the implementation principle of the present application, and the number is not particularly limited.
As an example, referring to step 16 in fig. 1 and fig. 4, etching the first filling layer 22 with gradually increasing etching temperature in step 16 includes:
in the process of etching the first filling layer 22, the etching temperature and the etching time are controlled to be changed in a preset temperature rising curve, so that accurate control of the etching temperature is realized.
As an example, referring to step 16 in fig. 1 and fig. 4, controlling the etching temperature and etching time to form a preset temperature rise curve in step 16 includes:
and controlling the etching temperature to change in a proportional relation with the etching time.
As an example, referring to step 16 in fig. 1 and fig. 5, controlling the etching temperature and etching time to form a preset temperature rise curve in step 16 includes:
and controlling the etching temperature and the etching time to be changed in a pulse step-type rising curve.
As an example, please continue to refer to fig. 5, in which the pulse period of the pulse-step-type rising curve of the etching temperature and the etching time is 3s-5s, for example, the pulse period of the pulse-step-type rising curve of the etching temperature and the etching time can be controlled to be 3s, 4s or 5s, so as to realize accurate control of the etching temperature and reduce the complexity of controlling the etching temperature.
As an example, with continued reference to step 16 in fig. 1, fig. 4 and fig. 5, etching the first filling layer 22 with gradually increasing etching temperature in step 16 includes: in the process of etching the first filling layer 22, the flow rate of the etching gas and the etching time are controlled to be changed in a preset change curve so as to cooperate with temperature control, so that the second etching holes 24 with the widths gradually decreasing from top to bottom are formed in the reserved first filling layer 22.
As an example, referring to step 16 in fig. 1, fig. 4 and fig. 5, controlling the flow rate of the etching gas and the etching time to form a predetermined change curve in step 16 includes: the flow rate of the etching gas is controlled to be changed in a periodical pulse curve with the etching time, so that the complexity of controlling the flow rate of the etching gas is reduced.
As an example, with continued reference to step 16 in fig. 1, fig. 4 and fig. 5, etching the first filling layer 22 with gradually increasing etching temperature in step 16 includes: the first fill layer 22 is etched by controlling the etching gas in a plasma manner to reduce the complexity of flow control of the etching gas.
As an example, in one embodiment of the present application, the flow rate of the etching gas and the etching time are controlled to be changed in a positive semicircular curve or a positive half-cycle sine wave curve according to the amplitude corresponding to each period in the periodic pulse curve, so as to cooperate with the temperature control, so that the second etching holes 24 with the widths gradually decreasing from top to bottom are formed in the first filling layer 22. In one embodiment of the present application, the flow rate of the etching gas is controlled to have a pulse period of 3s-5s in a periodic pulse curve with the etching time. For example, the flow rate of the etching gas and the etching time can be controlled to have a pulse period of 3s, 4s or 5s in a periodic pulse curve, so that the complexity of controlling the flow rate of the etching gas is reduced while the accurate control of the flow rate of the etching gas is realized.
As an example, with continued reference to step 16 in fig. 1, fig. 4 and fig. 5, etching the first filling layer 22 with gradually increasing etching temperature in step 16 includes:
during etching of the first filler layer 22, the etching temperature is controlled to gradually rise to a preset temperature. In one embodiment of the present application, the etching temperature is controlled to gradually rise to 400-450 ℃, for example, the etching temperature may be controlled to gradually rise to 400 ℃, 410 ℃, 420 ℃, 430 ℃, 440 ℃, or 450 ℃.
As an example, in one embodiment of the present application, the etching gas used to etch the first filling layer at the gradually increasing etching temperature includes at least one of chlorine gas, hydrogen chloride, chlorine trifluoride, carbon tetrafluoride, hexafluoroethane, perfluoropropane, octafluorocyclobutane, hexafluorobutadiene, octafluorocyclopentene, nitrogen trifluoride, and argon.
As an example, referring to fig. 6b, the limited filling capability of the conventional hole filling process results in the formation of voids or air gaps during the filling of high aspect ratio holes, and post-etch re-filling processes may be employed to avoid the creation of filled voids or air gaps. However, if the etching is continued at a higher etching temperature, the etching rate of the upper portion of the hole is much higher than that of the lower portion of the hole, so that a flat push is easily formed, and the recess 25 as shown in fig. 6b appears.
If the etching is continued at a lower etching temperature, which is isotropic, the top is not etched away and the bottom material has been etched too much, resulting in the etch back hole 26 shown in fig. 6 c.
With respect to fig. 6b and 6c, after forming the first filling layer 22 in the first etching hole 21 in the etched structure by using the filling process, the first filling layer 22 is etched by using the gradually increasing etching temperature, so as to form the second etching hole 24 with the width gradually decreasing from top to bottom, for example, the deep "V" shape, in the remaining first filling layer 22; then, at least the second etching hole 24 is formed with a second filling layer 27, so that the second filling layer 27 in the second etching hole 24 and the remaining first filling layer 22 together fill the first etching hole 21 without gaps, thereby avoiding forming voids or air gaps during the process of filling the high aspect ratio hole and improving the integrity of the manufactured semiconductor structure and the performance of the device.
As an example, referring to step 18 in fig. 1 and fig. 7a, forming the second filling layer 27 in at least the second etching holes 24 in step 18 includes:
step 181: a second filling layer 27 is deposited on the upper surface of the etched structure 100 and in the second etching hole 24, so that the second filling layer 27 in the second etching hole 24 and the remaining first filling layer 22 together fill the first etching hole 21 without gaps.
As an example, referring to fig. 7b, the first filling layer 22 and the second filling layer 27 are made of the same material. For example, the materials of the first filling layer 22 and the second filling layer 27 each include at least one of phosphorus doped silicon, boron doped silicon, undoped silicon, phosphorus doped germanium silicon, boron doped germanium silicon and undoped germanium silicon.
As an example, referring to fig. 8, step 181 further includes a step of removing the second filling layer 27 located on the upper surface of the etched structure 100, so that the upper surface of the second filling layer 27 remaining and located in the second etching hole 24 is flush with the upper surface of the etched structure 100.
By way of example, in one embodiment of the present application, step 18 may further include repeating steps 14, 16 and 18 to avoid voids or air gaps during filling of the high aspect ratio holes, thereby improving the integrity of the resulting semiconductor structure and device performance.
In one embodiment, the method of forming the second filling layer 27 includes any one of low pressure chemical vapor deposition, atomic layer deposition, and a combination of atomic layer seed deposition and low pressure chemical vapor deposition. The atomic layer seed deposition combined with low-pressure chemical vapor deposition composite method is that an atomic layer seed deposition method is adopted to form a seed layer, and then a low-pressure chemical vapor deposition method is adopted to deposit a second filling layer.
As an example, with continued reference to fig. 7a and 7b, in one embodiment of the present application, a semiconductor structure is provided, comprising: the semiconductor structure is manufactured by adopting any manufacturing method of the semiconductor structure in the embodiment of the application. After forming the first filling layer 22 in the first etching hole 21 in the etching structure 100 by using the filling process, etching the first filling layer 22 by using an etching temperature which is gradually increased so as to form a second etching hole 24 with a width gradually decreasing from top to bottom, for example, a deep "V" shape, in the remaining first filling layer 22; then, at least the second etching hole 24 is formed with a second filling layer 27, so that the second filling layer 27 in the second etching hole 24 and the remaining first filling layer 22 together fill the first etching hole 21 without gaps, thereby avoiding forming voids or air gaps during the process of filling the high aspect ratio hole and improving the integrity of the manufactured semiconductor structure and the performance of the device.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present application.
It should be understood that the steps described are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps described may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the sub-steps or stages of other steps or other steps.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (19)

1. A method of fabricating a semiconductor structure, comprising the steps of:
providing an etching structure with a first etching hole;
forming a first filling layer in the first etching hole;
etching the first filling layer by adopting gradually-increased etching temperature to form a second etching hole in the reserved first filling layer, wherein the width of the second etching hole gradually decreases from top to bottom;
and forming a second filling layer in at least the second etching hole, so that the second filling layer in the second etching hole and the reserved first filling layer jointly fill the first etching hole in a seamless manner.
2. The method of claim 1, wherein etching the first fill layer with a gradually increasing etching temperature comprises:
and in the process of etching the first filling layer, controlling the etching temperature and the etching time to change in a preset temperature rising curve.
3. The method of claim 2, wherein controlling the etching temperature and etching time to change in a preset temperature rise curve comprises:
controlling the etching temperature and the etching time to change in a proportional relation; or (b)
And controlling the etching temperature and the etching time to be changed in a pulse step-type rising curve.
4. The method of claim 3, wherein the pulse period for controlling the etching temperature and the etching time to form a pulse step-up curve is 3s-5s.
5. The method of any of claims 1-4, wherein etching the first fill layer with a gradually increasing etching temperature comprises:
and controlling the flow of etching gas and the etching time to form a preset change curve change in the process of etching the first filling layer.
6. The method of claim 5, wherein controlling the flow of the etching gas to vary in a predetermined variation curve with the etching time comprises:
and controlling the flow of the etching gas and the etching time to be changed in a periodic pulse curve.
7. The method of claim 5, wherein etching the first fill layer with a gradually increasing etching temperature comprises:
and controlling the etching gas to etch the first filling layer in a plasma mode.
8. The method of claim 6, wherein the amplitude of each period in the periodic pulse profile is controlled to vary in a positive half-cycle or a positive half-cycle sine wave profile.
9. The method of manufacturing a semiconductor structure according to claim 6, wherein a pulse period of the periodic pulse profile is controlled to be 3s to 5s.
10. The method of any of claims 1-4, wherein etching the first fill layer with a gradually increasing etching temperature comprises:
and in the process of etching the first filling layer, controlling the etching temperature to gradually rise to a preset temperature.
11. The method of claim 10, wherein the predetermined temperature is 400 ℃ to 450 ℃.
12. The method of any one of claims 1-4, wherein filling the first etch hole with a first filling layer comprises:
forming a first filling material layer on the upper surface of the etching structure and in the first etching hole, wherein the top surface of the first filling material layer is higher than the top surface of the first etching hole;
and removing the first filling material layer positioned on the etching structure until the top surface of the first filling material layer positioned in the first etching hole is flush with the upper surface of the etching structure, so as to form the first filling layer.
13. The method of claim 12, wherein said removing said first filler material layer on said etched structure comprises:
and removing the first filling material layer on the etching structure by adopting a low-temperature horizontal pushing process so as to form the first filling layer.
14. The method of claim 13, wherein the low temperature flat push process has a flat push temperature of 100 ℃ to 150 ℃.
15. The method of any of claims 1-4, wherein forming a second fill layer in at least the second etch hole comprises:
and depositing a second filling layer on the upper surface of the etching structure and in the second etching hole, so that the second filling layer in the second etching hole and the reserved first filling layer jointly fill the first etching hole in a seamless manner.
16. The method of any one of claims 1-4, wherein the second filling layer is formed by any one of low pressure chemical vapor deposition, atomic layer deposition and a combination of atomic layer seed deposition and low pressure chemical vapor deposition.
17. The method of any of claims 1-4, wherein the materials of the first filling layer and the second filling layer each comprise at least one of phosphorus doped silicon, boron doped silicon, undoped silicon, phosphorus doped germanium silicon, boron doped germanium silicon, and undoped germanium silicon.
18. The method of any of claims 1-4, wherein the etching gas used to etch the first filling layer at the gradually increasing etching temperature comprises at least one of chlorine, hydrogen chloride, chlorine trifluoride, carbon tetrafluoride, hexafluoroethane, perfluoropropane, octafluorocyclobutane, hexafluorobutadiene, octafluorocyclopentene, nitrogen trifluoride, and argon.
19. A semiconductor structure produced by the method of any one of claims 1-18.
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