CN113611661A - Preparation method of semiconductor structure and semiconductor structure - Google Patents

Preparation method of semiconductor structure and semiconductor structure Download PDF

Info

Publication number
CN113611661A
CN113611661A CN202110880620.9A CN202110880620A CN113611661A CN 113611661 A CN113611661 A CN 113611661A CN 202110880620 A CN202110880620 A CN 202110880620A CN 113611661 A CN113611661 A CN 113611661A
Authority
CN
China
Prior art keywords
etching
filling
filling layer
temperature
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110880620.9A
Other languages
Chinese (zh)
Other versions
CN113611661B (en
Inventor
郭帅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN202110880620.9A priority Critical patent/CN113611661B/en
Publication of CN113611661A publication Critical patent/CN113611661A/en
Application granted granted Critical
Publication of CN113611661B publication Critical patent/CN113611661B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The application relates to a preparation method of a semiconductor structure and the semiconductor structure, wherein the method comprises the following steps: providing an etching structure with a first etching hole; forming a first filling layer in the first etching hole; etching the first filling layer by adopting the gradually increased etching temperature so as to form a second etching hole in the reserved first filling layer, wherein the width of the second etching hole is gradually reduced from top to bottom; and forming a second filling layer in at least the second etching hole, so that the second filling layer in the second etching hole and the remained first filling layer jointly fill the first etching hole without gaps. The method and the device avoid the formation of a cavity or an air gap in the process of filling the high aspect ratio hole, and improve the integrity and the device performance of the manufactured semiconductor structure.

Description

Preparation method of semiconductor structure and semiconductor structure
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
With the rapid development of integrated circuit manufacturing processes, the demand for the integration level of semiconductor products is higher and higher. With the integration of semiconductor products, the size of semiconductor devices is continuously reduced and the semiconductor devices are continuously stacked upwards in space, so that the requirements on the filling process of high aspect ratio holes in the process of preparing semiconductors are higher and higher.
However, conventional via filling processes have limited filling capabilities, resulting in the formation of voids or air gaps during the filling of high aspect ratio vias, which ultimately affects the integrity of the resulting semiconductor structure and device performance.
Disclosure of Invention
Accordingly, there is a need to provide a method for fabricating a semiconductor structure and a semiconductor structure, which can avoid forming voids or air gaps during the process of filling high aspect ratio holes, and improve the integrity of the fabricated semiconductor structure and the device performance.
To achieve the above and other related objects, one aspect of the present application provides a method for fabricating a semiconductor structure, comprising the steps of:
providing an etching structure with a first etching hole;
forming a first filling layer in the first etching hole;
etching the first filling layer by adopting the gradually increased etching temperature so as to form a second etching hole in the reserved first filling layer, wherein the width of the second etching hole is gradually reduced from top to bottom;
and forming a second filling layer in at least the second etching hole, so that the second filling layer in the second etching hole and the remained first filling layer jointly fill the first etching hole without gaps.
In the semiconductor structure manufacturing method in the above embodiment, after a first filling layer is formed in a first etching hole in an etching structure by using a filling process, the first filling layer is etched at a gradually increased etching temperature to form a second etching hole, the width of which is gradually reduced from top to bottom, for example, a deep "V" shape, in the remaining first filling layer; and then forming a second filling layer in at least the second etching hole, so that the second filling layer in the second etching hole and the reserved first filling layer jointly fill the first etching hole in a seamless manner, thereby avoiding forming a hollow hole or an air gap in the process of filling the high-aspect-ratio hole and improving the integrity of the manufactured semiconductor structure and the performance of a device.
In one embodiment, the etching the first filling layer with the gradually increased etching temperature includes: and in the process of etching the first filling layer, controlling the etching temperature and the etching time to be changed in a preset temperature rise curve so as to realize accurate control of the etching temperature.
In one embodiment, the controlling the etching temperature and the etching time to change in a preset temperature rise curve includes:
controlling the etching temperature and the etching time to change in a direct proportional relation; or
And controlling the etching temperature and the etching time to change in a pulse step-type rising curve manner.
In one embodiment, the pulse period of the pulse stepped rising curve of the etching temperature and the etching time is controlled to be 3s-5s, so that the etching temperature is accurately controlled, and the complexity of controlling the etching temperature is reduced.
In one embodiment, the etching the first filling layer with the gradually increased etching temperature includes: and in the process of etching the first filling layer, controlling the flow of the etching gas and the etching time to be changed in a preset change curve so as to cooperate with temperature control to form a second etching hole with the width gradually reduced from top to bottom in the reserved first filling layer.
In one embodiment, the controlling the flow rate of the etching gas and the etching time to change according to a preset change curve includes: and controlling the flow of the etching gas and the etching time to be in periodic pulse curve change so as to reduce the complexity of controlling the flow of the etching gas.
In one embodiment, the etching the first filling layer with the gradually increased etching temperature includes: and controlling the etching gas to etch the first filling layer in a plasma mode so as to reduce the complexity of controlling the flow of the etching gas.
In one embodiment, the amplitude corresponding to each period in the periodic pulse curve is controlled to change in a positive semicircular curve or a positive half-period sine wave curve, so as to cooperate with temperature control, and form a second etching hole with a width gradually decreasing from top to bottom in the reserved first filling layer.
In one embodiment, the pulse period of the periodic pulse profile is controlled to be 3s-5 s.
In one embodiment, the etching the first filling layer with the gradually increased etching temperature includes:
and controlling the etching temperature to gradually rise to a preset temperature in the process of etching the first filling layer.
In one embodiment, the preset temperature is 400 ℃ to 450 ℃.
In one embodiment, filling the first filling layer in the first etching hole includes:
forming a first filling material layer on the upper surface of the etching structure and in the first etching hole, wherein the top surface of the first filling material layer is higher than that of the first etching hole;
and removing the first filling material layer on the etching structure until the top surface of the first filling material layer in the first etching hole is flush with the upper surface of the etching structure to form the first filling layer.
In one embodiment, the removing the first filling material layer on the etching structure includes:
and removing the first filling material layer on the etching structure by adopting a low-temperature flat pushing process to form the first filling layer, and forming the first filling layer with the upper surface flush with the upper surface of the etching structure by utilizing the characteristic of isotropic etching when the etching temperature is lower.
In one embodiment, the flat push temperature of the low temperature flat push process is 100 ℃ to 150 ℃.
In one embodiment, the forming of the second filling layer in at least the second etching hole includes:
and depositing a second filling layer on the upper surface of the etching structure and in the second etching hole, so that the second filling layer in the second etching hole and the reserved first filling layer jointly and seamlessly fill the first etching hole.
In one embodiment, the method for forming the second filling layer includes any one of low pressure chemical vapor deposition, atomic layer deposition, and a composite method combining atomic layer seed deposition and low pressure chemical vapor deposition.
In one embodiment, the material of the first and second filling layers comprises at least one of phosphorus doped silicon, boron doped silicon, undoped silicon, phosphorus doped silicon germanium, boron doped silicon germanium and undoped silicon germanium.
In one embodiment, the etching the first filling layer with the gradually-increased etching temperature includes at least one of chlorine gas, hydrogen chloride, chlorine trifluoride, carbon tetrafluoride, hexafluoroethane, perfluoropropane, octafluorocyclobutane, hexafluorobutadiene, octafluorocyclopentene, nitrogen trifluoride, and argon.
Another aspect of the present application provides a semiconductor structure comprising: the semiconductor structure is manufactured by adopting the manufacturing method of the semiconductor structure in any embodiment of the application. After a first filling layer is formed in a first etching hole in an etching structure by using a filling process, etching the first filling layer by adopting a gradually-increased etching temperature so as to form a second etching hole with the width gradually reduced from top to bottom, such as a deep V shape, in the reserved first filling layer; and then forming a second filling layer in at least the second etching hole, so that the second filling layer in the second etching hole and the reserved first filling layer jointly fill the first etching hole in a seamless manner, thereby avoiding forming a hollow hole or an air gap in the process of filling the high-aspect-ratio hole and improving the integrity of the manufactured semiconductor structure and the performance of a device.
Drawings
For a better understanding of the description and/or illustration of embodiments and/or examples of those applications disclosed herein, reference may be made to one or more of the drawings. The additional details or examples used to describe the figures should not be considered limiting of the scope of any of the disclosed applications, the presently described embodiments and/or examples, and the presently understood best mode of such applications.
FIG. 1 is a flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of the structure obtained in step 12 of a method for fabricating a semiconductor structure according to an embodiment of the present application;
FIGS. 3 a-3 b are schematic cross-sectional views of the structure obtained in step 14 of a method for fabricating a semiconductor structure according to an embodiment of the present application;
fig. 4 is a schematic diagram illustrating a time variation curve of the etching temperature and the etching gas flow rate in step 16 of the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram showing a time variation curve of the etching temperature and the flow rate of the etching gas in step 16 of the method for fabricating a semiconductor structure according to another embodiment of the present application;
FIG. 6a is a schematic cross-sectional view of the structure obtained in step 16 of a method for fabricating a semiconductor structure according to an embodiment of the present application;
FIG. 6b is a schematic cross-sectional view of a structure obtained by a conventional etching process;
FIG. 6c is a schematic cross-sectional view of a structure obtained by another conventional etching process;
FIGS. 7 a-7 b are schematic cross-sectional views illustrating the structure obtained in step 18 of a method for fabricating a semiconductor structure according to an embodiment of the present application;
FIG. 8 is a schematic cross-sectional view of the structure obtained in step 18 of a method for fabricating a semiconductor structure according to another embodiment of the present application;
description of reference numerals:
100. etching the structure; 21. a first etching hole; 22. a first filling layer; 221. a first layer of filler material; 23. an air gap; 24. a second etching hole; 25. a groove; 26. back-carving the hole; 27. and a second filling layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing, the regions illustrated in the figures being schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
Please refer to fig. 1-8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present application, and although the drawings only show the components related to the present application and are not drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Referring to fig. 1, in an embodiment of the present application, a method for fabricating a semiconductor structure includes the following steps:
step 12: providing an etching structure with a first etching hole;
step 14: forming a first filling layer in the first etching hole;
step 16: etching the first filling layer by adopting the gradually increased etching temperature so as to form a second etching hole in the reserved first filling layer, wherein the width of the second etching hole is gradually reduced from top to bottom;
step 18: and forming a second filling layer in at least the second etching hole, so that the second filling layer in the second etching hole and the remained first filling layer jointly fill the first etching hole without gaps.
Specifically, with reference to fig. 1, after a first filling layer is formed in a first etching hole in an etching structure by a filling process, the first filling layer is etched at a gradually increased etching temperature to form a second etching hole having a width gradually decreasing from top to bottom, for example, a deep "V" shape, in the remaining first filling layer; and then forming a second filling layer in at least the second etching hole, so that the second filling layer in the second etching hole and the reserved first filling layer jointly fill the first etching hole in a seamless manner, thereby avoiding forming a hollow hole or an air gap in the process of filling the high-aspect-ratio hole and improving the integrity of the manufactured semiconductor structure and the performance of a device.
In step 12, referring to step 12 in fig. 1 and fig. 2, an etching structure 100 is provided, and a first etching hole 21 is formed in the etching structure 100.
As an example, since the conventional hole filling process has a limited filling capability, resulting in the formation of a void or air gap such as the first etching hole 21 during the filling of the high aspect ratio hole, the first etching hole 21 shown in fig. 2 is intended to exemplify the implementation principle of the present application, and the number of the first etching holes 21 formed may be plural during the actual semiconductor filling process. The application aims to provide a preparation method of a semiconductor structure, which avoids forming a cavity or an air gap in the process of filling a hole with a high aspect ratio and improves the integrity and the device performance of the manufactured semiconductor structure.
For example, continuing with step 14 of fig. 1, fig. 3a and fig. 3b, the step of forming the first filling layer at least in the first via 21 may include the following steps:
step 141: forming a first filling material layer 221 on the upper surface of the etching structure 100 and in the first etching hole 21, wherein the top surface of the first filling material layer 221 is higher than the top surface of the first etching hole 21;
step 142: the first filling material layer 221 on the etching structure 100 is removed until the top surface of the first filling material layer 221 in the first etching hole 21 is flush with the upper surface of the etching structure 100 to form the first filling layer 22.
In this embodiment, the etching process may include a plasma dry etching process. The parameters of the adopted dry etching process comprise: the gas comprises fluorocarbon gas, HBr and Cl2And a carrier gas, the fluorocarbon gas comprising CF4、CHF3、CH2F2Or CH3And F, the carrier gas is inert gas such as He, the gas flow is 50-400 sccm, and the pressure is 3-8 mTorr.
As an example, the removing the first filling material layer 221 on the etched structure 100 in step 142 includes:
and removing the first filling material layer 221 on the etching structure 100 by adopting a low-temperature flat-pushing process to form the first filling layer 22, and forming the first filling layer 22 with the upper surface flush with the upper surface of the etching structure 100 by utilizing the characteristic of isotropic etching when the etching temperature is lower.
By way of example, in one embodiment of the present application, the flat-pushing temperature of the low temperature flat-pushing process is from 100 ℃ to 150 ℃, for example, the flat-pushing temperature of the low temperature flat-pushing process may be 100 ℃, 110 ℃, 120 ℃, 130 ℃, 140 ℃ or 150 ℃.
As an example, the number of the first etching holes 21 in the step 14 may be plural, and the depth of each first etching hole 21 may be the same or different; the widths of the first via holes 21 may be the same or different.
Due to the limited filling capability of conventional hole filling processes, air gaps 23 are formed during the filling of high aspect ratio holes, which ultimately affects the integrity of the resulting semiconductor structure and device performance. The number of the air gaps 23 formed in the process of filling the high aspect ratio hole may be plural, and the air gaps 23 in fig. 3a and 3b are intended to exemplify the implementation principle of the present application, and the number thereof is not particularly limited.
As an example, continuing with step 16 of fig. 1 and with reference to fig. 4, etching the first filling layer 22 at step 16 with a gradually increasing etching temperature includes:
in the process of etching the first filling layer 22, the etching temperature and the etching time are controlled to change in a preset temperature rise curve, so that the etching temperature is accurately controlled.
For example, referring to step 16 and fig. 4 in fig. 1, the step 16 of controlling the etching temperature and the etching time to change according to the preset temperature-increasing curve includes:
and controlling the etching temperature to change in a direct proportional relation with the etching time.
For example, referring to step 16 and fig. 5 in fig. 1, the step 16 of controlling the etching temperature and the etching time to change according to the preset temperature-increasing curve includes:
and controlling the etching temperature and the etching time to change in a pulse step-type rising curve manner.
For example, please refer to fig. 5, wherein the pulse period of the pulse-shaped ascending curve of the etching temperature and the etching time is controlled to be 3s-5s, for example, the pulse period of the pulse-shaped ascending curve of the etching temperature and the etching time can be controlled to be 3s, 4s or 5s, so as to realize accurate control of the etching temperature and reduce the complexity of controlling the etching temperature.
As an example, continuing with step 16 of fig. 1, fig. 4 and fig. 5, etching the first filling layer 22 with a gradually increasing etching temperature in step 16 includes: in the process of etching the first filling layer 22, the flow rate of the etching gas and the etching time are controlled to change in a preset change curve, so as to cooperate with temperature control, and form the second etching holes 24 with the width gradually decreasing from top to bottom in the reserved first filling layer 22.
For example, continuing to refer to step 16, fig. 4 and fig. 5 in fig. 1, the step 16 of controlling the flow rate of the etching gas and the etching time to change according to a predetermined change curve includes: the flow of the etching gas and the etching time are controlled to be changed in a periodic pulse curve, so that the complexity of controlling the flow of the etching gas is reduced.
As an example, continuing with step 16 of fig. 1, fig. 4 and fig. 5, etching the first filling layer 22 with a gradually increasing etching temperature in step 16 includes: the etching gas is controlled to etch the first filling layer 22 in a plasma manner to reduce the complexity of flow control of the etching gas.
As an example, in an embodiment of the present application, the flow rate of the etching gas and the etching time are controlled to change in a positive semicircular curve or a positive half-cycle sine wave curve, so as to cooperate with the temperature control, so that the second etching holes 24 with gradually decreasing widths from top to bottom are formed in the remaining first filling layer 22. In one embodiment of the present application, the flow rate of the etching gas is controlled to have a periodic pulse profile with an etching time having a pulse period of 3s to 5 s. For example, the pulse period of the periodic pulse curve of the flow rate of the etching gas and the etching time can be controlled to be 3s, 4s or 5s, so that the flow rate of the etching gas can be accurately controlled, and the complexity of controlling the flow rate of the etching gas can be reduced.
As an example, continuing with step 16 of fig. 1, fig. 4 and fig. 5, etching the first filling layer 22 with a gradually increasing etching temperature in step 16 includes:
during the etching of the first filling layer 22, the etching temperature is controlled to be gradually increased to a preset temperature. In one embodiment of the present application, the etching temperature is controlled to be gradually increased to 400 ℃ to 450 ℃, for example, the etching temperature may be controlled to be gradually increased to 400 ℃, 410 ℃, 420 ℃, 430 ℃, 440 ℃, or 450 ℃.
As an example, in an embodiment of the present application, the etching gas used for etching the first filling layer at the gradually increasing etching temperature includes at least one of chlorine gas, hydrogen chloride, chlorine trifluoride, carbon tetrafluoride, hexafluoroethane, perfluoropropane, octafluorocyclobutane, hexafluorobutadiene, octafluorocyclopentene, nitrogen trifluoride, and argon gas.
As an example, referring to fig. 6b, the conventional hole filling process has a limited filling capability, which results in formation of voids or air gaps during the filling of the high aspect ratio holes, and a process of refilling after etching back may be used to avoid the formation of filled voids or air gaps. However, if the etch back is continued at a higher etch temperature, the etch rate at the upper portion of the hole is much higher than the etch rate at the lower portion of the hole, and a flat push is easily formed, resulting in a recess 25 as shown in FIG. 6 b.
If the etch back is continued at a lower temperature, the etch back is isotropic at a lower temperature, the top is not etched away, and the bottom material has been etched too much, resulting in the etch back holes 26 shown in FIG. 6 c.
With respect to fig. 6b and 6c, after forming the first filling layer 22 in the first etching hole 21 in the etching structure by using the filling process, the present application uses a gradually increased etching temperature to etch the first filling layer 22, so as to form a second etching hole 24 with a width gradually decreasing from top to bottom, for example, a deep "V" shape, in the remaining first filling layer 22; then, at least a second filling layer 27 is formed in the second etching hole 24, so that the second filling layer 27 in the second etching hole 24 and the remaining first filling layer 22 together fill the first etching hole 21 without a gap, thereby avoiding the formation of a void or an air gap during the process of filling the high aspect ratio hole, and improving the integrity of the manufactured semiconductor structure and the device performance.
For example, continuing with step 18 of fig. 1 and fig. 7a, the step 18 of forming at least the second filling-up layer 27 in the second via 24 includes:
step 181: the second filling layer 27 is deposited on the upper surface of the etching structure 100 and in the second etching hole 24, so that the second filling layer 27 in the second etching hole 24 and the remaining first filling layer 22 together fill the first etching hole 21 without a gap.
As an example, referring to fig. 7b, the first filling-up layer 22 and the second filling-up layer 27 are made of the same material. For example, the material of each of the first and second filling layers 22 and 27 includes at least one of phosphorus doped silicon, boron doped silicon, undoped silicon, phosphorus doped silicon germanium, boron doped silicon germanium, and undoped silicon germanium.
As an example, referring to fig. 8, step 181 is followed by a step of removing the second filling-up layer 27 on the upper surface of the etched structure 100, so that the upper surface of the second filling-up layer 27 remaining and located in the second etching hole 24 is flush with the upper surface of the etched structure 100.
As an example, in one embodiment of the present application, step 18 is followed by repeating steps 14, 16 and 18 to avoid void formation or air gaps during the filling of the high aspect ratio holes and to improve the integrity of the resulting semiconductor structure and device performance.
In one embodiment, the method for forming the second filling layer 27 includes any one of low pressure chemical vapor deposition, atomic layer deposition, and a composite method combining atomic layer seed deposition and low pressure chemical vapor deposition. The atomic layer seed deposition and low-pressure chemical vapor deposition combined composite method comprises the steps of firstly forming a seed layer by adopting an atomic layer seed deposition method and then depositing a second filling layer by adopting a low-pressure chemical vapor deposition method.
By way of example, with continuing reference to fig. 7a and 7b, in one embodiment of the present application, a semiconductor structure is provided, comprising: the semiconductor structure is manufactured by adopting the manufacturing method of the semiconductor structure in any embodiment of the application. After forming a first filling layer 22 in the first etching hole 21 in the etching structure 100 by using a filling process, etching the first filling layer 22 by using a gradually increased etching temperature to form a second etching hole 24 with a width gradually decreasing from top to bottom, for example, a deep "V" shape, in the remaining first filling layer 22; then, at least a second filling layer 27 is formed in the second etching hole 24, so that the second filling layer 27 in the second etching hole 24 and the remaining first filling layer 22 together fill the first etching hole 21 without a gap, thereby avoiding the formation of a void or an air gap during the process of filling the high aspect ratio hole, and improving the integrity of the manufactured semiconductor structure and the device performance.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present application.
It should be understood that the steps described are not to be performed in the exact order recited, and that the steps may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps described may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed alternately or in alternation with other steps or at least some of the sub-steps or stages of other steps.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (19)

1. A method for manufacturing a semiconductor structure, comprising the steps of:
providing an etching structure with a first etching hole;
forming a first filling layer in the first etching hole;
etching the first filling layer by adopting the gradually increased etching temperature so as to form a second etching hole in the reserved first filling layer, wherein the width of the second etching hole is gradually reduced from top to bottom;
and forming a second filling layer in at least the second etching hole, so that the second filling layer in the second etching hole and the remained first filling layer jointly fill the first etching hole without gaps.
2. The method of claim 1, wherein the etching the first fill layer with the gradually increasing etch temperature comprises:
and in the process of etching the first filling layer, controlling the etching temperature and the etching time to change in a preset temperature rise curve.
3. The method for manufacturing a semiconductor structure according to claim 2, wherein the controlling the etching temperature and the etching time to change in a preset temperature-rise curve comprises:
controlling the etching temperature and the etching time to change in a direct proportional relation; or
And controlling the etching temperature and the etching time to change in a pulse step-type rising curve manner.
4. The method according to claim 3, wherein the pulse period of the pulse stepwise rising curve of the etching temperature and the etching time is controlled to be 3s-5 s.
5. The method of fabricating a semiconductor structure according to any of claims 1-4, wherein the etching the first fill layer with a gradually increasing etch temperature comprises:
and in the process of etching the first filling layer, controlling the flow of the etching gas and the etching time to change in a preset change curve.
6. The method for manufacturing a semiconductor structure according to claim 5, wherein the controlling the flow rate of the etching gas and the etching time to change in a preset change curve comprises:
and controlling the flow of the etching gas and the etching time to be changed in a periodic pulse curve.
7. The method of claim 5, wherein the etching the first fill layer with the gradually increasing etch temperature comprises:
and controlling etching gas to etch the first filling layer in a plasma mode.
8. The method of claim 6, wherein the amplitude of each period of the periodic pulse profile is controlled to vary in a positive semicircular profile or a positive half-cycle sinusoidal profile.
9. The method of claim 6, wherein the periodic pulse profile is controlled to have a pulse period of 3s to 5 s.
10. The method of fabricating a semiconductor structure according to any of claims 1-4, wherein the etching the first fill layer with a gradually increasing etch temperature comprises:
and controlling the etching temperature to gradually rise to a preset temperature in the process of etching the first filling layer.
11. The method of claim 10, wherein the predetermined temperature is 400 ℃ to 450 ℃.
12. The method for fabricating a semiconductor structure according to any one of claims 1 to 4, wherein filling a first filling layer in the first via hole comprises:
forming a first filling material layer on the upper surface of the etching structure and in the first etching hole, wherein the top surface of the first filling material layer is higher than that of the first etching hole;
and removing the first filling material layer on the etching structure until the top surface of the first filling material layer in the first etching hole is flush with the upper surface of the etching structure to form the first filling layer.
13. The method for fabricating a semiconductor structure according to claim 12, wherein the removing the first filling material layer on the etched structure comprises:
and removing the first filling material layer on the etching structure by adopting a low-temperature flat pushing process to form the first filling layer.
14. The method of claim 13, wherein the low temperature flat push process has a flat push temperature of 100 ℃ to 150 ℃.
15. The method for fabricating a semiconductor structure according to any one of claims 1 to 4, wherein the forming of the second filling layer in at least the second via hole comprises:
and depositing a second filling layer on the upper surface of the etching structure and in the second etching hole, so that the second filling layer in the second etching hole and the reserved first filling layer jointly and seamlessly fill the first etching hole.
16. The method for fabricating a semiconductor structure according to any one of claims 1 to 4, wherein the method for forming the second filling layer comprises any one of low pressure chemical vapor deposition, atomic layer deposition and a composite method combining atomic layer seed deposition and low pressure chemical vapor deposition.
17. The method as claimed in any one of claims 1 to 4, wherein the material of each of the first and second filling layers comprises at least one of P-doped silicon, B-doped silicon, undoped silicon, P-doped SiGe, B-doped SiGe and undoped SiGe.
18. The method of any one of claims 1-4, wherein the etching gas used to etch the first fill layer at the gradually increasing etching temperature comprises at least one of chlorine, hydrogen chloride, chlorine trifluoride, carbon tetrafluoride, hexafluoroethane, perfluoropropane, octafluorocyclobutane, hexafluorobutadiene, octafluorocyclopentene, nitrogen trifluoride, and argon.
19. A semiconductor structure produced by the method for producing a semiconductor structure according to any one of claims 1 to 18.
CN202110880620.9A 2021-08-02 2021-08-02 Method for preparing semiconductor structure and semiconductor structure Active CN113611661B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110880620.9A CN113611661B (en) 2021-08-02 2021-08-02 Method for preparing semiconductor structure and semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110880620.9A CN113611661B (en) 2021-08-02 2021-08-02 Method for preparing semiconductor structure and semiconductor structure

Publications (2)

Publication Number Publication Date
CN113611661A true CN113611661A (en) 2021-11-05
CN113611661B CN113611661B (en) 2023-06-13

Family

ID=78339051

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110880620.9A Active CN113611661B (en) 2021-08-02 2021-08-02 Method for preparing semiconductor structure and semiconductor structure

Country Status (1)

Country Link
CN (1) CN113611661B (en)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050148171A1 (en) * 2002-06-11 2005-07-07 Dietmar Temmler Method for filling trench and relief geometries in semiconductor structures
CN1979796A (en) * 2005-12-05 2007-06-13 中芯国际集成电路制造(上海)有限公司 Method with high seam-filling ability and device structure obtained therefrom
CN101635274A (en) * 2009-08-18 2010-01-27 上海集成电路研发中心有限公司 Method for eliminating cavity in filling of metal gap
US20120119376A1 (en) * 2010-11-16 2012-05-17 Dong-Chan Lim Semiconductor chips and methods of forming the same
US20150011091A1 (en) * 2013-07-03 2015-01-08 Tokyo Electron Limited Substrate processing method and control apparatus
CN106653675A (en) * 2015-08-28 2017-05-10 中芯国际集成电路制造(北京)有限公司 Method of forming isolation structure of shallow trench
CN207398112U (en) * 2017-11-07 2018-05-22 睿力集成电路有限公司 Semiconductor structure
CN112864097A (en) * 2021-01-14 2021-05-28 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof
CN112992774A (en) * 2019-12-02 2021-06-18 长鑫存储技术有限公司 Method for forming gap

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050148171A1 (en) * 2002-06-11 2005-07-07 Dietmar Temmler Method for filling trench and relief geometries in semiconductor structures
CN1979796A (en) * 2005-12-05 2007-06-13 中芯国际集成电路制造(上海)有限公司 Method with high seam-filling ability and device structure obtained therefrom
CN101635274A (en) * 2009-08-18 2010-01-27 上海集成电路研发中心有限公司 Method for eliminating cavity in filling of metal gap
US20120119376A1 (en) * 2010-11-16 2012-05-17 Dong-Chan Lim Semiconductor chips and methods of forming the same
US20150011091A1 (en) * 2013-07-03 2015-01-08 Tokyo Electron Limited Substrate processing method and control apparatus
CN106653675A (en) * 2015-08-28 2017-05-10 中芯国际集成电路制造(北京)有限公司 Method of forming isolation structure of shallow trench
CN207398112U (en) * 2017-11-07 2018-05-22 睿力集成电路有限公司 Semiconductor structure
CN112992774A (en) * 2019-12-02 2021-06-18 长鑫存储技术有限公司 Method for forming gap
CN112864097A (en) * 2021-01-14 2021-05-28 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof

Also Published As

Publication number Publication date
CN113611661B (en) 2023-06-13

Similar Documents

Publication Publication Date Title
TWI625862B (en) Intergrated chip and method of forming deep trench capacitor
US7998874B2 (en) Method for forming hard mask patterns having a fine pitch and method for forming a semiconductor device using the same
JP2013520830A (en) Method for forming conformal insulating layer and pattern forming method in via and etched structure
TWI723231B (en) Method of forming semiconductor device and semiconductor device
CN1783452A (en) Method for forming silicon lining bottom on pattern insulator
JP2009260284A (en) Semiconductor element and semiconductor element fabrication method
KR102631107B1 (en) High aspect ratio bosch deep etch
CN105742156A (en) Method Of Forming A Graphene Structure
CN111952313A (en) Three-dimensional memory and manufacturing method thereof
CN113611661B (en) Method for preparing semiconductor structure and semiconductor structure
US11309382B2 (en) Electronic product comprising a component having triskelion-pillars, and corresponding fabrication method
CN109427647B (en) Method for manufacturing isolation structure
JP2013153120A (en) Manufacturing method of semiconductor device
TW201232699A (en) Method for forming deep trench isolation
US9892969B2 (en) Process of forming an electronic device
CN112018089B (en) Semiconductor capacitor and method for manufacturing the same
EP1719181A1 (en) Gradient deposition of low-k cvd materials
CN113611662B (en) Method for preparing semiconductor structure and semiconductor structure
CN114556545A (en) Method for producing a semiconductor body with a trench, semiconductor body with at least one trench and semiconductor component
CN107706147B (en) Preparation method of vertical contact hole
CN105460883B (en) A kind of semiconductor devices and preparation method thereof, electronic installation
CN104340951B (en) A kind of preparation method of motion sensor
CN107978557B (en) Method for manufacturing vacuum gap in etching groove
US20070267671A1 (en) Trench capacitor having lateral extensions in only one direction and related methods
CN105097661B (en) A kind of semiconductor devices and preparation method thereof, electronic device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant