CN113611601B - Method for adjusting flatness of wafer - Google Patents

Method for adjusting flatness of wafer Download PDF

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Publication number
CN113611601B
CN113611601B CN202110818214.XA CN202110818214A CN113611601B CN 113611601 B CN113611601 B CN 113611601B CN 202110818214 A CN202110818214 A CN 202110818214A CN 113611601 B CN113611601 B CN 113611601B
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dielectric layer
grinding
wafer
polishing
layer
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CN113611601A (en
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邢程
孙鹏
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ICLeague Technology Co Ltd
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ICLeague Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The embodiment of the application discloses a method for adjusting the flatness of a wafer. The method comprises the following steps: forming a first dielectric layer on the surface of a wafer to be processed; performing first grinding on the first dielectric layer; the grinding thickness of the first grinding is smaller than or equal to the thickness of the first dielectric layer; forming a second dielectric layer on the surface of the wafer after the first grinding; performing second grinding on the second dielectric layer; wherein the second dielectric layer with a predetermined thickness remains after the second grinding.

Description

Method for adjusting flatness of wafer
Technical Field
The embodiment of the application relates to a semiconductor technology, in particular to a method for adjusting the flatness of a wafer.
Background
In the integrated circuit manufacturing process, with the increase of the number of interconnection layers and the reduction of process characteristics, the requirements on the flatness of the wafer surface are also higher and higher, and the metal layer and the dielectric layer are required to be subjected to planarization treatment so as to reduce or eliminate the influence of uneven phenomena such as bulges and/or depressions. The occurrence of these irregularities may cause voids to form during the deposition growth of the thin film, thereby affecting the coverage of the deposited and grown thin film, so that it is desirable to reduce or eliminate the effect of the protrusions and/or depressions. Thus, there is an increasing demand for planarization of metal layers and dielectric layers.
Disclosure of Invention
In view of this, the embodiment of the application provides a method for adjusting the flatness of a wafer.
The embodiment of the application provides a method for adjusting the flatness of a wafer, which comprises the following steps:
Forming a first dielectric layer on the surface of a wafer to be processed;
Performing first grinding on the first dielectric layer; the grinding thickness of the first grinding is smaller than or equal to the thickness of the first dielectric layer;
forming a second dielectric layer on the surface of the wafer after the first grinding;
Performing second grinding on the second dielectric layer; wherein the second dielectric layer with a predetermined thickness remains after the second grinding.
In some embodiments, the first grinding the first dielectric layer includes:
and taking the surface of the wafer as a polishing end point, and carrying out first polishing on the first dielectric layer.
In some embodiments, the material of the wafer surface is: silicon nitride; the silicon nitride is used to block the first polish.
In some embodiments, prior to forming the first dielectric layer, the method further comprises:
Forming a barrier layer on the surface of the wafer;
the first grinding of the first dielectric layer comprises the following steps:
and taking the barrier layer as a polishing end point, and carrying out first polishing on the first dielectric layer.
In some embodiments, the barrier layer is a polysilicon film.
In some embodiments, the first grinding comprises:
Performing the first polishing on the first dielectric layer by using a first polishing liquid; wherein the first grinding fluid is cerium dioxide.
In some embodiments, the second grinding comprises:
Performing the second polishing on the second medium layer by using a second polishing liquid; wherein the second grinding fluid is silicon dioxide.
In some embodiments, the first dielectric layer and the second dielectric layer are the same material.
In some embodiments, the materials of the first dielectric layer and the second dielectric layer are: silica.
In some embodiments, the second dielectric layer remaining after the second grinding is used as a bonding dielectric layer in a wafer bonding process of the wafer.
In the embodiment of the application, the flatness of the surface of the wafer is adjusted by forming a first dielectric layer on the surface of the wafer to be processed, performing first grinding, forming a second dielectric layer, and performing second grinding. Compared with the mode of forming only one dielectric layer and grinding once, the method can improve the flatness of the wafer and reduce the defects on the surface of the wafer.
Drawings
In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.
Fig. 1 is a flowchart of a method for adjusting the flatness of a wafer according to an embodiment of the present application;
FIGS. 2A-2E are schematic cross-sectional views of a wafer at each step in an adjustment method according to an embodiment of the present application;
fig. 3A to 3E are schematic cross-sectional views of a wafer at each step in another adjustment method according to an embodiment of the present application.
Detailed Description
The flatness adjustment, also called planarization, is a process for reducing the roughness of the wafer surface and reducing wafer warpage. The planarization process is a key technology for manufacturing chips, and each wafer can be subjected to several or even tens of planarization processes in the production process according to the requirements of different process steps and technical nodes, and is mainly used for surface planarization of silicon wafers, metal layers above the silicon wafers, interlayer dielectric layers, bonding dielectric layers and other structures.
Fig. 1 is a flowchart of a method for adjusting flatness of a wafer according to an embodiment of the present application, where the method includes:
step S101, forming a first dielectric layer on the surface of a wafer to be processed;
Step S102, carrying out first grinding on the first dielectric layer; the grinding thickness of the first grinding is smaller than or equal to the thickness of the first dielectric layer;
Step S103, forming a second dielectric layer 203 on the surface of the wafer after the first polishing;
step S104, carrying out second grinding on the second dielectric layer; wherein the second dielectric layer with a predetermined thickness remains after the second grinding.
In an embodiment of the present application, as shown in fig. 2A and 2B, a first dielectric layer 202 may be formed on a wafer surface 201 to be processed. The first dielectric layer 202 may be used as a polishing medium, on one hand, the material of the first dielectric layer 202 may fill some recessed defects on the wafer surface 201, and on the other hand, the flatness of the entire wafer may be adjusted during polishing. The material of the first dielectric layer 202 may be an insulating layer, including silicon oxide or silicon nitride, or may be a semiconductor or metal layer. The first dielectric layer 202 may be formed by a growth method or a deposition method. The growth method comprises the following steps: oxidation processes and nitridation processes. The deposition method comprises the following steps: evaporation processes, sputtering processes, electroplating processes, chemical vapor deposition (CVD, chemical Vapor Deposition) processes, and the like.
After forming the first dielectric layer 202, the first dielectric layer 202 is subjected to the first polishing. The grinding may be performed by chemical mechanical Polishing (CMP, chemical Mechanical Polishing). For example, the polishing may be achieved by using a CMP slurry in combination with mechanical polishing. The CMP polishing liquid is a mixture of polishing materials and chemical additives in a planarization process, and mainly comprises components such as an abrasive, a surfactant, PH buffer glue, an oxidant, a preservative and the like. Among them, the abrasive generally includes nanoscale silica (SiO 2), nanoscale cerium oxide (CeO 2), nanoscale aluminum oxide (Al 2O 3), and the like. The CMP polishing liquid may be a silica polishing liquid, a ceria polishing liquid, an alumina polishing liquid, or the like.
In the embodiment of the present application, as shown in fig. 2C, the thickness of the first polished-away layer should not exceed the thickness of the first dielectric layer 202, i.e. the maximum polished thickness is the thickness of the first dielectric layer 202. When the thickness of the first polishing does not exceed the thickness of the first dielectric layer 202, the first polishing can be stopped when the flatness of the first dielectric layer 202 is within the desired range. Or stopping the first polishing immediately when the thickness of the first dielectric layer 202 is reached by the thickness of the first polishing. In this way, on the one hand, the first dielectric layer 202 can be used to fill the concave or uneven area on the surface of the wafer, on the other hand, the uneven area corresponding to the wafer on the surface of the first dielectric layer 202 can be removed by grinding, so that the second dielectric layer can be formed on the surface with the highest flatness as possible.
In an embodiment of the present application, as shown in fig. 2D, a second dielectric layer 203 may be further formed on the surface of the wafer after the first polishing is performed. The second dielectric layer 203 serves as a polishing object for the second polishing and, at the same time, can also be used as a structural layer in a semiconductor device. For example, the second dielectric layer 203 may be used as a photoresist layer, a metal layer, an interlayer dielectric layer, a bonding dielectric layer, and other structural layers. Accordingly, after the second grinding is performed, the second dielectric layer 203 of a predetermined thickness may remain for forming the above-described structural layer in the semiconductor device.
Here, the material of the second dielectric layer 203 may be an insulating layer, including silicon oxide or silicon nitride. But may also be a semiconductor or metal layer. The material and the formation method of the second dielectric layer 203 may be the same as those of the first dielectric layer 202 or may be different from those of the first dielectric layer 202.
In the embodiment of the present application, after the second dielectric layer 203 is formed, as shown in fig. 2E, a flatter surface of the second dielectric layer 203 needs to be obtained for performing a photolithography process or a bonding process. The second dielectric layer 203 thus requires a second polish. The second polishing may be by means of CMP. The CMP polishing liquid is a ceria polishing liquid, a silica polishing liquid, an alumina polishing liquid, or the like. When the thickness of the second dielectric layer 203 reaches the desired retention thickness, the second polishing is stopped. For example, a sensor may be used to detect whether the second dielectric layer 203 has reached a specified polish thickness and signal the arrival while stopping the second polish.
By the method, the second dielectric layer 203 further fills the defect of the wafer surface after the first grinding, and a smoother surface is obtained by the second grinding. In this way, on one hand, the flatness of the surface of the wafer is improved, on the other hand, the second dielectric layer 203 reserved after the second grinding is performed forms a semiconductor structure layer meeting the flatness requirement, the subsequent process is convenient to perform, the product failure caused by flatness defects in the subsequent process is reduced, and the product yield is improved.
In the embodiment of the present application, as shown in fig. 2C, the first polishing is performed on the first dielectric layer 202 by using the wafer surface 201 as a polishing endpoint.
Taking the wafer surface 201 as the polishing end point means that the wafer surface 201 and the following parts are not polished when the first polishing is performed. When the flatness of the first dielectric layer 202 is within a desired range, and the next process can be performed, the first polishing may be stopped in the first dielectric layer 202. When the first polish reaches the wafer surface 201, the polish may be stopped immediately. So as to avoid dishing caused by different selection ratios of the CMP polishing liquid to the first dielectric layer 202 and the wafer.
In an embodiment of the present application, as shown in fig. 2A, the materials of the wafer surface 201 are: silicon nitride; the silicon nitride is used to block the first polish.
When the material of the wafer surface 201 is silicon nitride, the first dielectric layer 202 has a high selectivity to silicon nitride under the same CMP process condition, i.e., the polishing liquid does not etch or etches less to the silicon nitride layer of the wafer surface 201. The silicon nitride at this time may block the first polish. I.e., the silicon nitride film serves as a polish stop layer. The material of the first dielectric layer 202 is selected to have a different polishing rate than the silicon nitride film. Thus, during the CMP process performed on the first dielectric layer 202. The silicon nitride film protects the wafer beneath it.
In the embodiment of the present application, as shown in fig. 3A, a barrier layer 302 is formed on the wafer surface 301; the first polishing the first dielectric layer 202 includes: the first polishing is performed on the first dielectric layer 202 by using the barrier layer 302 as a polishing endpoint.
Under the same CMP process conditions, when the first dielectric layer 202 does not have a high selectivity to the wafer surface 301, a barrier layer 302 may be formed on the wafer surface 301 so that the polishing liquid does not etch to the wafer surface 301. Alternatively, under the same CMP process conditions, when the first dielectric layer 202 has a high selectivity to the wafer surface 301, a barrier layer 302 having a higher selectivity may be formed on the wafer surface 301. The polishing liquid is enabled to be polished more uniformly on the surface of the barrier layer 302, and the flatness of the first polishing is improved.
In an embodiment of the present application, as shown in fig. 3A, the barrier layer 302 is a polysilicon film.
Under the same CMP process condition, the selectivity of the first dielectric layer 202 to the polysilicon film is higher than ten times of the selectivity of the first dielectric layer 202 to the silicon nitride film. Therefore, when a layer of polysilicon blocking film is formed on the surface of the wafer and then CMP grinding is carried out, a better blocking effect can be obtained, and better flatness can be obtained. The polysilicon film serves as a polish stop layer. The material of the first dielectric layer 202 is selected to have a different polishing rate than the polysilicon film. Thus, during the CMP process performed on the first dielectric layer 202. The polysilicon film protects the wafer beneath it.
In the embodiment of the present application, as shown in fig. 2C and fig. 3C, the first polishing is performed on the first dielectric layers 202 and 303 using a first polishing liquid; wherein the first grinding fluid is cerium dioxide. The polishing of the cerium oxide grinding fluid is mainly based on chemical action, and has the following advantages: 1. the flattening efficiency is high, and the convex surface can be selectively ground; 2. the polishing process has high selectivity to silicon nitride, and can automatically terminate polishing to a certain extent.
In the first polishing, a defect of local unevenness of the wafer surface 201 is mainly flattened. The ceria slurry can achieve higher local flatness than other slurries.
In the embodiment of the present application, as shown in fig. 2E and fig. 3E, the second polishing is performed on the second dielectric layers 203 and 304 with a second polishing liquid; wherein the second grinding fluid is silicon dioxide. The polishing of the silicon dioxide grinding liquid is mainly performed by mechanical action. When the second polishing is performed, global planarization is required for the defects and undulations of the irregularities of the second dielectric layers 203 and 304. The silica slurry may achieve a higher global flatness than other slurries.
In the embodiment of the present application, as shown in fig. 2B and 2D, fig. 3B and 3D, the first dielectric layers 202 and 303 and the second dielectric layers 203 and 304 are made of the same material.
The first dielectric layers 202 and 303 and the second dielectric layers 203 and 304 may use the same dielectric material. Thus, the remaining portions of first dielectric layers 202 and 303 after the first grinding may be used as a remaining dielectric layer together with the remaining portions of second dielectric layers 203 and 304 after the second grinding.
In the embodiment of the present application, as shown in fig. 2B and fig. 2D, fig. 3B and fig. 3D, the materials of the first dielectric layer 202 and the second dielectric layer 202 are: silica.
The silicon dioxide film can be used to treat silicon surfaces, as a doped barrier layer, surface insulation layer, bonding dielectric layer, and as an insulating portion in a device. When the materials of the first dielectric layer 202 and the second dielectric layer 202 are silicon dioxide, the silicon dioxide film has a high selectivity to the wafer surface or the barrier layer on the wafer surface under the same CMP process condition, and the wafer surface 201 or the barrier layer 302 on the wafer surface can be used as a polishing stop layer when the first polishing and the second polishing are performed, so as to protect the wafer.
In the embodiment of the present application, as shown in fig. 2E and fig. 3E, the second dielectric layers 203 and 304 remaining after the second polishing are used as bonding dielectric layers in the wafer bonding process.
The second dielectric layers 203 and 304 remaining after the second grinding may be used as a photolithography layer or a bonding dielectric layer for wafer bonding. Wafer bonding refers to the process of tightly bonding two mirror polished homogeneous or heterogeneous wafers through chemical and physical actions, wherein after the wafers are bonded, atoms at an interface react under the action of external force to form covalent bonds to be bonded together, and the bonding interface reaches a specific bonding strength.
The purpose of the remaining second dielectric layers 203 and 304 may also be determined according to the different materials of the second dielectric layers 203 and 304 and the next process step after the second dielectric layers 203 and 304 are formed.
The embodiment of the application also provides the following examples, as shown in fig. 2A to 2E:
The two wafers are bonded, and the surface flatness of the two wafer dielectric layers is extremely high. The flatness of the wafer surface 201 includes local flatness and global flatness. The local flatness is reflected by the fluctuation of the surface morphology of a certain local area, and the main reason is the pattern arrangement of the bottom layer wiring/device. The global flatness is responsive to the waviness of the entire wafer surface, mainly due to the speed of film growth and the rate of chemical mechanical polishing. Wafer bonding requires both high local and global flatness. This is because if the wafer is locally rugged, the two interfaces cannot be effectively contacted during bonding, and bubble defects are easily generated in the cavity to cause bonding failure. If the global flatness of the two wafers does not reach the standard, partial region dislocation and insufficient bonding can be caused.
When the material of the wafer surface 201 is silicon nitride, the wafer surface 201 directly grows a silicon dioxide film as the first dielectric layer 202, and then the cerium oxide polishing liquid is selected to perform the first CMP polishing, the thickness of the polished silicon dioxide film is smaller than or equal to the thickness of the silicon dioxide film, and the cerium oxide polishing liquid is used in the first polishing, so that the silicon dioxide film has a higher selection ratio to the silicon nitride. The silicon nitride layer on the wafer surface 201 serves as a barrier layer to control the local flatness. The grinding fluid does not etch or etch the silicon nitride layer on the surface of the wafer less, and local butterfly-shaped concave is not easy to generate, so that the local flatness of the wafer is improved. After the adjustment of the local flatness of the wafer is completed, a silicon dioxide film is grown again as the second dielectric layer 203, and then a silicon dioxide polishing liquid is selected to perform a second CMP polishing to reach a final required thickness. The second polishing improves the global flatness of the wafer. The planarized second dielectric layer 203 after the second polishing may be used as a bonding dielectric layer for performing a subsequent bonding process.
The embodiment of the application also provides another example as shown in fig. 3A to 3E:
When the material of the wafer surface 301 is silicon nitride, a polysilicon layer is grown on the silicon nitride surface by a low temperature process. Then, a silicon dioxide film is formed on the polysilicon barrier layer 302 as a first dielectric layer 303, and then, cerium oxide polishing liquid is selected to perform a first CMP polishing, and under the condition that the cerium oxide polishing liquid is used to perform a CMP process, the barrier effect of the polysilicon layer is ten times or more than that of silicon nitride. I.e., the silicon dioxide film to polysilicon film selectivity is ten times that of silicon nitride. The polysilicon layer serves as a barrier layer 302 to control the local flatness. The polishing liquid does not etch or etches the polysilicon layer 302 grown on the wafer surface 201 slightly, so that local dishing is not easy to generate, and the local flatness of the wafer is improved. After the adjustment of the local flatness of the wafer is completed, a silicon dioxide film is grown again as the second dielectric layer 304, and then a silicon dioxide polishing solution is selected for performing a second CMP polishing to reach a final desired thickness. The second polishing improves the global flatness of the wafer. The planarized second dielectric layer 304 after the second polishing may be used as a bonding dielectric layer for subsequent bonding processes.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application. The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is merely an embodiment of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. The method for adjusting the flatness of the wafer is characterized by comprising the following steps:
Forming a first dielectric layer on the surface of a wafer to be processed;
Performing first grinding on the first dielectric layer; the grinding thickness of the first grinding is smaller than or equal to the thickness of the first dielectric layer;
forming a second dielectric layer on the surface of the wafer after the first grinding;
Performing second grinding on the second dielectric layer; wherein the second dielectric layer with a preset thickness is reserved after the second grinding, and the preset thickness is not zero; the grinding thickness of the second grinding is smaller than the thickness of the second dielectric layer;
the first grinding is different from the grinding liquid used by the second grinding, the first grinding is used for adjusting local unevenness, and the second grinding is used for adjusting global unevenness.
2. The method of claim 1, wherein first grinding the first dielectric layer comprises:
and taking the surface of the wafer as a polishing end point, and carrying out first polishing on the first dielectric layer.
3. The method of claim 2, wherein the material of the wafer surface is: silicon nitride; the silicon nitride is used to block the first polish.
4. The method of claim 1, wherein prior to forming the first dielectric layer, the method further comprises:
Forming a barrier layer on the surface of the wafer;
performing first grinding on the first dielectric layer, including:
and taking the barrier layer as a polishing end point, and carrying out first polishing on the first dielectric layer.
5. The method of claim 4, wherein the barrier layer is a polysilicon film.
6. The method of any one of claims 1 to 5, wherein the first grinding comprises:
Performing the first polishing on the first dielectric layer by using a first polishing liquid; wherein the first grinding fluid is cerium dioxide.
7. The method of any one of claims 1 to 5, wherein the second grinding comprises:
Performing the second polishing on the second medium layer by using a second polishing liquid; wherein the second grinding fluid is silicon dioxide.
8. The method of any of claims 1-5, wherein the first dielectric layer and the second dielectric layer are the same material.
9. The method of claim 8, wherein the materials of the first dielectric layer and the second dielectric layer are: silica.
10. The method of any one of claims 1 to 4, wherein the second dielectric layer remaining after the second grinding is used as a bonding dielectric layer during wafer bonding of the wafer.
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