CN113611601A - Method for adjusting flatness of wafer - Google Patents

Method for adjusting flatness of wafer Download PDF

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Publication number
CN113611601A
CN113611601A CN202110818214.XA CN202110818214A CN113611601A CN 113611601 A CN113611601 A CN 113611601A CN 202110818214 A CN202110818214 A CN 202110818214A CN 113611601 A CN113611601 A CN 113611601A
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grinding
wafer
dielectric layer
layer
polishing
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CN113611601B (en
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邢程
孙鹏
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ICLeague Technology Co Ltd
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ICLeague Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The embodiment of the application discloses a method for adjusting the flatness of a wafer. The method comprises the following steps: forming a first dielectric layer on the surface of a wafer to be processed; carrying out first grinding on the first medium layer; the grinding thickness of the first grinding is smaller than or equal to the thickness of the first medium layer; forming a second dielectric layer on the surface of the wafer after the first grinding; carrying out second grinding on the second medium layer; and after the second grinding, reserving the second medium layer with a preset thickness.

Description

Method for adjusting flatness of wafer
Technical Field
The embodiment of the application relates to a semiconductor technology, and relates to but is not limited to a method for adjusting the flatness of a wafer.
Background
In the manufacturing process of the integrated circuit, along with the increase of the number of interconnection layers and the reduction of process characteristics, the requirement on the flatness of the surface of a wafer is higher and higher, and a metal layer and a dielectric layer are required to be subjected to planarization treatment so as to reduce or eliminate the influence of unevenness such as protrusion and/or depression. The occurrence of these irregularities may cause voids to form during the film deposition and growth process, thereby affecting the coverage of the deposited and grown film, and it is desirable to reduce or eliminate the effects of the protrusions and/or depressions. Thus, the requirements for planarization of the metal layer and the dielectric layer are increasing.
Disclosure of Invention
In view of the above, the present disclosure provides a method for adjusting the flatness of a wafer.
The embodiment of the application provides a method for adjusting the flatness of a wafer, which comprises the following steps:
forming a first dielectric layer on the surface of a wafer to be processed;
carrying out first grinding on the first medium layer; the grinding thickness of the first grinding is smaller than or equal to the thickness of the first medium layer;
forming a second dielectric layer on the surface of the wafer after the first grinding;
carrying out second grinding on the second medium layer; and after the second grinding, reserving the second medium layer with a preset thickness.
In some embodiments, the performing the first grinding on the first medium layer includes:
and performing the first grinding on the first medium layer by taking the surface of the wafer as a grinding end point.
In some embodiments, the material of the wafer surface is: silicon nitride; the silicon nitride is used for blocking the first grinding.
In some embodiments, prior to forming the first dielectric layer, the method further comprises:
forming a barrier layer on the surface of the wafer;
the first grinding of the first medium layer comprises the following steps:
and performing the first grinding on the first medium layer by taking the barrier layer as a grinding end point.
In some embodiments, the barrier layer is a polysilicon thin film.
In some embodiments, the first grinding, comprises:
performing the first grinding on the first medium layer by using first grinding liquid; wherein the first polishing solution is cerium dioxide.
In some embodiments, the second grinding, comprises:
performing second grinding on the second medium layer by using second grinding liquid; wherein the second grinding fluid is silicon dioxide.
In some embodiments, the first dielectric layer and the second dielectric layer are the same material.
In some embodiments, the materials of the first dielectric layer and the second dielectric layer are: silicon dioxide.
In some embodiments, the second dielectric layer remaining after the second grinding is used as a bonding dielectric layer in a wafer bonding process of the wafer.
In the embodiment of the application, the flatness of the surface of the wafer is adjusted by forming a first medium layer on the surface of the wafer to be processed, performing first grinding, then forming a second medium layer, and performing second grinding. Compared with a mode of only forming one dielectric layer and grinding at one time, the method can improve the flatness of the wafer and reduce the defects on the surface of the wafer.
Drawings
In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.
Fig. 1 is a flowchart illustrating a method for adjusting the flatness of a wafer according to an embodiment of the present disclosure;
fig. 2A to fig. 2E are schematic cross-sectional views of a wafer at various steps in an adjusting method according to an embodiment of the present disclosure;
fig. 3A to fig. 3E are schematic cross-sectional views of a wafer at various steps in another adjusting method according to an embodiment of the present disclosure.
Detailed Description
The adjustment of the flatness of the wafer, also called planarization, is a process for reducing the defects of the unevenness on the surface of the wafer and reducing the warpage of the wafer. The planarization treatment is a key technology for manufacturing chips, and according to the requirements of different process procedures and technical nodes, each wafer can undergo several or even dozens of planarization treatments in the production process, and the planarization treatment is mainly used for surface planarization of silicon wafers, metal layers above the silicon wafers, interlayer dielectric layers, bonding dielectric layers and other structures.
Fig. 1 is a flowchart of a method for adjusting a flatness of a wafer according to an embodiment of the present disclosure, where the method includes:
step S101, forming a first dielectric layer on the surface of a wafer to be processed;
step S102, carrying out first grinding on the first medium layer; the grinding thickness of the first grinding is smaller than or equal to the thickness of the first medium layer;
step S103, forming a second dielectric layer 203 on the surface of the wafer subjected to the first grinding;
step S104, carrying out second grinding on the second medium layer; and after the second grinding, reserving the second medium layer with a preset thickness.
In the embodiment of the present application, as shown in fig. 2A and 2B, a first dielectric layer 202 may be formed on a surface 201 of a wafer to be processed. The first dielectric layer 202 can be used as a grinding medium, on one hand, the material of the first dielectric layer 202 can fill some recessed defects on the wafer surface 201, and on the other hand, the flatness of the whole wafer can be adjusted during grinding. The material of the first dielectric layer 202 may be an insulating layer, including silicon oxide or silicon nitride, or a semiconductor or metal layer. The first dielectric layer 202 may be formed by a growth method or a deposition method. The growth method comprises the following steps: an oxidation process and a nitridation process. The deposition method comprises the following steps: an evaporation process, a sputtering process, a plating process, and a Chemical Vapor Deposition (CVD) process, etc.
After the first dielectric layer 202 is formed, the first dielectric layer 202 is subjected to the first polishing. The Polishing method may be Chemical Mechanical Polishing (CMP). Illustratively, the lapping can be accomplished using a CMP slurry in combination with mechanical polishing. The CMP polishing solution is a mixture of a polishing material and a chemical additive in a planarization process, and mainly comprises components such as a polishing agent, a surfactant, a PH buffer gel, an oxidant, a preservative and the like. The abrasive generally includes nanoscale silica (SiO2), nanoscale cerium oxide (CeO2), and nanoscale aluminum oxide (Al2O 3). The CMP polishing liquid may be a silicon dioxide polishing liquid, a cerium oxide polishing liquid, an alumina polishing liquid, or the like.
In the embodiment of the present application, as shown in fig. 2C, the thickness of the first polishing should not exceed the thickness of the first dielectric layer 202, i.e., the maximum polishing thickness is the thickness of the first dielectric layer 202. When the thickness of the first dielectric layer 202 is not exceeded by the thickness of the first polishing, the first polishing can be stopped when the flatness of the first dielectric layer 202 is within the desired range. Alternatively, when the thickness of the first dielectric layer 202 is reached, the first polishing is stopped immediately. In this way, on one hand, the first dielectric layer 202 can be used to fill up the concave or uneven area on the surface of the wafer, and on the other hand, the uneven area on the surface of the first dielectric layer 202 corresponding to the wafer can be removed by grinding, so that the second dielectric layer can be formed on the surface with the highest flatness.
In the embodiment of the present invention, as shown in fig. 2D, a second dielectric layer 203 may be further formed on the surface of the wafer after the first polishing. The second dielectric layer 203 is used as a grinding object of the second grinding, and can also be used as a structural layer in a semiconductor device. For example, the second dielectric layer 203 may serve as a photoresist layer, a metal layer, an interlayer dielectric layer, a bonding dielectric layer, and other structural layers. Therefore, after the second grinding, the second dielectric layer 203 with a predetermined thickness may remain for forming the above-mentioned structural layer in the semiconductor device.
Here, the material of the second dielectric layer 203 may be an insulating layer, including silicon oxide, silicon nitride, or the like. But may also be a semiconductor or metal layer. The material and formation method of the second dielectric layer 203 may be the same as those of the first dielectric layer 202, or may be different from those of the first dielectric layer 202.
In the embodiment of the present application, as shown in fig. 2E, after the second dielectric layer 203 is formed, a flatter surface of the second dielectric layer 203 needs to be obtained for the next photolithography process or bonding process. The second dielectric layer 203 thus requires a second polish. The second grinding may be performed by CMP. The CMP polishing liquid is a ceria polishing liquid, a silica polishing liquid, an alumina polishing liquid, or the like. When the thickness of the second dielectric layer 203 reaches the required remaining thickness, the second polishing is stopped. Illustratively, a sensor may be used to detect whether the second media layer 203 has reached a specified polishing thickness and signal a reach when it has arrived while stopping the second polishing.
By the method, the second medium layer 203 further fills the defects of the surface of the wafer after the first grinding, and a smoother surface is obtained by the second grinding. Therefore, the flatness of the surface of the wafer is improved on the one hand, and on the other hand, the second dielectric layer 203 reserved after the second grinding forms a semiconductor structure layer meeting the flatness requirement, so that the subsequent process is convenient to carry out, the product failure caused by the flatness defect in the subsequent process is reduced, and the product yield is improved.
In the embodiment of the present application, as shown in fig. 2C, the first polishing is performed on the first dielectric layer 202 with the wafer surface 201 as a polishing endpoint.
Taking the wafer surface 201 as the polishing end point means that the wafer surface 201 and the following portions are not polished at the time of the first polishing. When the flatness of the first dielectric layer 202 is within a desired range, the first polishing may be stopped in the first dielectric layer 202 when the next process can be performed. When the first polish reaches the wafer surface 201, the polish can be stopped immediately. So as to prevent the CMP slurry from causing surface dishing due to the different selection ratios of the first dielectric layer 202 and the wafer.
In the embodiment of the present application, as shown in fig. 2A, the material of the wafer surface 201 is: silicon nitride; the silicon nitride is used for blocking the first grinding.
When the material of the wafer surface 201 is silicon nitride, under the same CMP process condition, the first dielectric layer 202 has a high selectivity to silicon nitride, i.e., the polishing slurry does not etch or etches a small amount of the silicon nitride layer on the wafer surface 201. The silicon nitride may block the first polish at this time. I.e., the silicon nitride film, serves as a polish stop layer. The material of the first dielectric layer 202 is selected to have a different polishing rate than the silicon nitride film. Thus, during the CMP process performed on the first dielectric layer 202. The silicon nitride film protects the wafer below it.
In the embodiment of the present application, as shown in fig. 3A, a barrier layer 302 is formed on the wafer surface 301; the first grinding of the first dielectric layer 202 includes: the first polishing is performed on the first dielectric layer 202 with the barrier layer 302 as a polishing endpoint.
Under the same CMP process condition, when the first dielectric layer 202 does not have a high selectivity to the wafer surface 301, a barrier layer 302 may be formed on the wafer surface 301 so that the slurry does not etch the wafer surface 301. Alternatively, under the same CMP process conditions, when the first dielectric layer 202 has a high selectivity to the wafer surface 301, a barrier layer 302 with a higher selectivity may also be formed on the wafer surface 301. The polishing slurry is more uniformly polished on the surface of the barrier layer 302, and the flatness of the first polishing is improved.
In the embodiment of the present application, as shown in fig. 3A, the barrier layer 302 is a polysilicon thin film.
Under the same CMP process condition, the selectivity ratio of the first dielectric layer 202 to the polysilicon film is higher and ten times of the selectivity ratio of the first dielectric layer 202 to the silicon nitride. Therefore, when a polysilicon barrier film is formed on the surface of the wafer and then CMP grinding is carried out, a better barrier effect can be obtained, and better flatness can be obtained. The polysilicon film serves as a polish stop layer. The material of the first dielectric layer 202 is selected to have a different polishing rate than the polysilicon film. Thus, during the CMP process performed on the first dielectric layer 202. The polysilicon film protects the wafer below it.
In the embodiment of the present application, as shown in fig. 2C and 3C, the first polishing is performed on the first medium layers 202 and 303 by using a first polishing slurry; wherein the first polishing solution is cerium dioxide. The ceria slurry polishing is dominated by chemical action and has the following advantages: 1. the flatness efficiency is high, and the convex surface can be selectively ground; 2. the silicon nitride has a high selection ratio, and can realize automatic termination of polishing to a certain extent.
During the first polishing, the local unevenness of the wafer surface 201 is mainly planarized. The ceria slurry can achieve higher local planarity than other slurries.
In the embodiment of the present application, as shown in fig. 2E and fig. 3E, the second polishing is performed on the second medium layers 203 and 304 by using a second polishing liquid; wherein the second grinding fluid is silicon dioxide. The polishing with silica slurry is dominated by mechanical action. When the second polishing is performed, global planarization treatment is required for the uneven defects and undulations of the second dielectric layers 203 and 304. The silicon dioxide grinding liquid phase can obtain higher global flatness than other grinding liquids.
In the embodiment of the present application, as shown in fig. 2B and 2D, and fig. 3B and 3D, the first dielectric layers 202 and 303 and the second dielectric layers 203 and 304 are made of the same material.
The first dielectric layers 202 and 303 and the second dielectric layers 203 and 304 may use the same dielectric material. Thus, the remaining portions of the first dielectric layers 202 and 303 after the first polishing can be used as the remaining dielectric layers together with the remaining portions of the second dielectric layers 203 and 304 after the second polishing.
In the embodiment of the present application, as shown in fig. 2B and 2D, and fig. 3B and 3D, the materials of the first dielectric layer 202 and the second dielectric layer 202 are: silicon dioxide.
The silicon dioxide film can be used for processing silicon surfaces, as a doping barrier layer, a surface insulating layer, a bonding dielectric layer and as an insulating part in a device. When the first dielectric layer 202 and the second dielectric layer 202 are made of silicon dioxide, the silicon dioxide film has a high selectivity ratio to the wafer surface or the barrier layer on the wafer surface under the same CMP process condition, and both the wafer surface 201 or the barrier layer 302 on the wafer surface can be used as a polishing stop layer during the first polishing and the second polishing, so that the wafer is protected.
In the embodiment of the present application, as shown in fig. 2E and fig. 3E, the second dielectric layers 203 and 304 remaining after the second grinding are used as bonding dielectric layers in a wafer bonding process performed on the wafer.
The second dielectric layers 203 and 304 remaining after the second grinding can be used as a photoetching layer and also can be used as bonding dielectric layers for wafer bonding. Wafer bonding refers to the process of tightly bonding two mirror polished homogeneous or heterogeneous chips through chemical and physical actions, and after the chips are bonded, atoms on the interface are acted by external force to react to form covalent bonds to be bonded into a whole, so that the bonded interface achieves specific bonding strength.
The purpose of the remaining second dielectric layers 203 and 304 may also be determined by the different materials of the second dielectric layers 203 and 304, and the next processing steps after the second dielectric layers 203 and 304 are formed.
The embodiment of the present application further provides the following examples, as shown in fig. 2A to 2E:
when the two wafers are bonded, the requirement on the flatness of the surfaces of the two wafer dielectric layers is extremely high. The flatness of the wafer surface 201 includes local flatness and global flatness. The local flatness reflects the fluctuation of the surface appearance of a certain local area, and the main cause is the pattern arrangement of bottom layer wiring/devices. The global flatness reflects the topography of the entire wafer surface, mainly due to the speed of film growth and the rate of chemical mechanical polishing. Wafer bonding requires both high local and global planarity. This is because if the local topography of the wafer is uneven, the two interfaces cannot be effectively contacted during bonding, and bubble defects are easily generated in the cavity to cause bonding failure. If the global flatness of the two wafers does not reach the standard, the partial regions are dislocated and the bonding is insufficient.
When the material of the wafer surface 201 is silicon nitride, a silicon dioxide film directly grows on the wafer surface 201 to serve as the first dielectric layer 202, and then the ceria slurry is selected to perform the first CMP polishing, wherein the thickness of the polished silicon dioxide film is less than or equal to the thickness of the silicon dioxide film, and the ceria slurry is used in the first polishing, so that the silicon dioxide film has a higher selectivity to silicon nitride. The silicon nitride layer on the wafer surface 201 serves as a barrier layer to control local flatness. The grinding liquid does not etch or slightly etches the silicon nitride layer on the surface of the wafer, so that local butterfly-shaped depressions are not easy to generate, and the local flatness of the wafer is improved. After the adjustment of the local flatness of the wafer is completed, a silicon dioxide film is grown again to serve as a second dielectric layer 203, and then silicon dioxide grinding liquid is selected to perform second CMP grinding to reach the final required thickness. The second grinding improves the global flatness of the wafer. The planarized second dielectric layer 203 after the second grinding can be used as a bonding dielectric layer for a subsequent bonding process.
The embodiment of the present application further provides another example as follows, as shown in fig. 3A to 3E:
when the material of the wafer surface 301 is silicon nitride, a polysilicon layer is grown on the silicon nitride surface by a low-temperature process. And then generating a silicon dioxide film on the polysilicon barrier layer 302 as a first dielectric layer 303, and then selecting a cerium dioxide polishing solution to perform first CMP (chemical mechanical polishing) polishing, wherein the barrier effect of the polysilicon layer is more than ten times that of silicon nitride under the condition of performing a CMP process by using the cerium dioxide polishing solution. I.e., the selectivity ratio of the silicon dioxide film to the polysilicon film is ten times that of the silicon nitride. The polysilicon layer serves as a barrier layer 302 to achieve control of local planarity. The grinding liquid does not etch or slightly etches the polycrystalline silicon layer 302 growing on the surface 201 of the wafer, so that local butterfly-shaped depressions are not easy to generate, and the local flatness of the wafer is improved. After the adjustment of the local flatness of the wafer is completed, a silicon dioxide film is grown again to serve as a second dielectric layer 304, and then silicon dioxide polishing liquid is selected to perform second CMP polishing to reach the final required thickness. The second grinding improves the global flatness of the wafer. The planarized second dielectric layer 304 after the second grinding may be used as a bonding dielectric layer for a subsequent bonding process.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only for the embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A method for adjusting the flatness of a wafer is characterized by comprising the following steps:
forming a first dielectric layer on the surface of a wafer to be processed;
carrying out first grinding on the first medium layer; the grinding thickness of the first grinding is smaller than or equal to the thickness of the first medium layer;
forming a second dielectric layer on the surface of the wafer after the first grinding;
carrying out second grinding on the second medium layer; and after the second grinding, reserving the second medium layer with a preset thickness.
2. The method of claim 1, wherein the first grinding of the first media layer comprises:
and performing the first grinding on the first medium layer by taking the surface of the wafer as a grinding end point.
3. The method of claim 2, wherein the wafer surface is made of: silicon nitride; the silicon nitride is used for blocking the first grinding.
4. The method of claim 1, wherein prior to forming the first dielectric layer, the method further comprises:
forming a barrier layer on the surface of the wafer;
the first grinding of the first medium layer comprises the following steps:
and performing the first grinding on the first medium layer by taking the barrier layer as a grinding end point.
5. The method of claim 4, wherein the barrier layer is a polysilicon thin film.
6. The method of any one of claims 1 to 5, wherein the first grinding comprises:
performing the first grinding on the first medium layer by using first grinding liquid; wherein the first polishing solution is cerium dioxide.
7. The method of any one of claims 1 to 5, wherein the second grinding comprises:
performing second grinding on the second medium layer by using second grinding liquid; wherein the second grinding fluid is silicon dioxide.
8. The method of any of claims 1 to 5, wherein the first dielectric layer and the second dielectric layer are the same material.
9. The method of claim 8, wherein the first dielectric layer and the second dielectric layer are made of: silicon dioxide.
10. The method of any of claims 1 to 4, wherein the second dielectric layer remaining after the second grinding is used as a bonding dielectric layer during wafer bonding of the wafer.
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