CN113609037A - GPIO module verification method, device and equipment based on UVM and readable medium - Google Patents
GPIO module verification method, device and equipment based on UVM and readable medium Download PDFInfo
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Abstract
The invention provides a method, a device, equipment and a readable medium for verifying a GPIO module based on UVM, wherein the method comprises the following steps: dividing the signals of the GPIO module into five groups based on the signal category; responding to a received instruction verified by the GPIO module, and detecting a stage verification indication mark; selecting one or more of the five groups of signals based on the detected stage verification indication mark and verifying the current stage of the GPIO module based on the UVM architecture; in response to the current phase verification passing, the phase verification indication flag is updated. By using the scheme of the invention, the verification efficiency can be improved, the number and the correlation of the excitation can be reduced, the judgment logic in scoreboard classes is reduced, and the verification convergence speed can be accelerated.
Description
Technical Field
The field relates to the field of computers, and more particularly to a method, device, apparatus and readable medium for UVM-based GPIO module authentication.
Background
In a server, a BMC (baseboard management controller) chip needs to receive operating state information from a CPU and control various devices on a motherboard, such as a serial port, a USB port, a fan, and the like, so the BMC chip generates many external interface pins, and in order to reduce the number of interfaces, a GPIO (general purpose input/output) module is often required to multiplex the interfaces. For example, in the BMC, 244 GPIO pins are implemented, which can support the multiplexing of 732 interfaces in total, thereby greatly reducing the number of pins.
For a basic GPIO module with general purpose functions, the basic GPIO module mainly includes GPIO basic input/output functions, and this function needs to configure corresponding registers, such as data registers and direction registers, so that the system can communicate with the outside through GPIO, and at this time, the CPU in the system usually controls and communicates. And an interrupt function, when the GPIO input function is used, corresponding interrupt can be selected to be generated, such as interrupt in the forms of high level, rising edge and the like, namely when the external input 1 is input, if the high level interrupt is selected at the moment, the GPIO can generate an interrupt signal to trigger the CPU to perform corresponding interrupt operation. The multiplexing function can realize the interface multiplexing of other modules in the system by configuring the GPIO internal interface, for example, the interfaces of the modules such as I2C and lpc can perform data interaction with the outside world through the GPIO interface.
With the continuous improvement of the process level, the complexity of the design is becoming larger, and the traditional Verilog-based verification method cannot meet the requirements of the current design.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method, an apparatus, a device, and a readable medium for GPIO module verification based on UVM (universal verification methodology), which can improve verification efficiency, reduce the number and correlation of stimuli, reduce the determination logic in scoreboard classes, and accelerate verification convergence speed.
Based on the above object, an aspect of the embodiments of the present invention provides a method for verification of a GPIO module based on UVM, including the following steps:
dividing the signals of the GPIO module into five groups based on the signal category;
responding to a received instruction verified by the GPIO module, and detecting a stage verification indication mark;
selecting one or more of the five groups of signals based on the detected stage verification indication mark and verifying the current stage of the GPIO module based on the UVM architecture;
in response to the current phase verification passing, the phase verification indication flag is updated.
According to one embodiment of the present invention, the five sets of signals are:
the first group of signals are bus protocol related signals;
the second group of signals are internal input/output signals, direction control signals and multiplexing priority signals;
the third group of signals are external input signals;
the fourth group of signals are external output signals;
the fifth set of signals are the partial read write register and internal register signals in the DUT.
According to one embodiment of the invention, selecting one or more of the five groups of signals based on the detected indicator and performing the current stage verification of the GPIO module based on the UVM architecture comprises:
selecting a first set of signals in response to detecting that the phase verification indication flag is register read-write verification;
the sequence type in the UVM structure randomizes the register address and data, the driver type receives random register information and sends out bus write operation according to a bus protocol, and the write operation stores the data corresponding to the address after the corresponding operation is carried out on the data through the register function in the DUT;
after the randomized waiting time, performing bus reading operation on the address, detecting bus signals by the monitor, sampling the address and data at the effective moment of a bus protocol, maintaining an associated array by the scoreboard, using the address as an index of the array, and comparing the data corresponding to the address in the array with the sampled and read data of the monitor by the reading operation to judge the reading and writing correctness;
the register read-write verification passes in response to the read-write being correct and the address being overwritten the desired number of times.
According to one embodiment of the invention, selecting one or more of the five groups of signals based on the detected indicator and performing the current stage verification of the GPIO module based on the UVM architecture comprises:
selecting a third, fourth, and fifth set of signals in response to detecting that the phase verification indicator is a basic input output verification;
the sequence class in the UVM structure randomizes directions and data sending registers in a third group and a fifth group according to the sequence, a driver class drives a third group signal port of a DUT, a register value in the DUT is modified through a back door access method, a transaction data packet is sent to a scoreboard class, an omotor class back door accesses a data receiving register, a fourth group signal in the DUT is detected, information is sent to the scoreboard class, and the scoreboard class compares the values of the third group signal and a receiving register in the fifth group signal, the fourth group signal and a sending register in the fifth group signal based on the value of the direction register so as to judge the basic input and output functions;
and responding to the input excitation meeting the coverage rate requirement, and the basic input and output passes the verification.
According to one embodiment of the invention, selecting one or more of the five groups of signals based on the detected indicator and performing the current stage verification of the GPIO module based on the UVM architecture comprises:
selecting a first, third, and fifth set of signals in response to detecting that the phase verification indicator is an interrupt verification;
the sequence class in the UVM structure randomizes the direction and the interrupt enabling register in the third group and the fifth group of signals according to the sequence, the driver class drives a third group signal port of the DUT, the register value in the DUT is modified through a back door access method, a transaction data packet is sent to the scoreboard class, the rear door of the omonor class accesses an interrupt state register and sends information to the scoreboard class, and the scoreboard class compares the values of the receiving register in the third group signal and the fifth group signal based on the value of the direction register so as to judge the interrupt generating function;
the sequence type randomizes a first group of signals, the driver type drives a DUT (device under test) by generating a bus protocol, and transmits a transaction data packet to the scoreboard type, the omotor type accesses an interrupt state register through a backdoor and transmits information to the scoreboard type, and the scoreboard type compares an interrupt register value and a bus write-in value so as to judge an interrupt clearing function;
and interrupting the verification to pass in response to the input excitation meeting the coverage rate requirement.
According to one embodiment of the invention, selecting one or more of the five groups of signals based on the detected indicator and performing the current stage verification of the GPIO module based on the UVM architecture comprises:
selecting a second, third and fourth set of signals in response to detecting that the phase verification indicator is a multiplex function verification;
the sequence class in the UVM structure randomizes a second group of input signals and a third group of signals, the driver class drives a second group of signal input ports and a third group of signal input ports of the DUT, transmits a transaction data packet to the scoreboard class, the omonitor class detects a second group of output signals and a fourth group of output signals and transmits information to the scoreboard class, and the scoreboard class judges a direction control signal and a multiplexing priority signal by comparing an internal input in the second group with an external output in the fourth group and an internal output in the second group with an external input signal in the third group so as to judge a multiplexing function;
the multiplexing function verifies in response to the input stimulus satisfying the coverage requirement.
According to an embodiment of the present invention, further comprising:
and stopping verification and sending out a warning in response to the current stage verification failing.
In another aspect of the embodiments of the present invention, there is also provided a device for UVM-based GPIO module verification, the device including:
the dividing module is configured to divide the signals of the GPIO module into five groups based on the signal category;
a detection module configured to detect a stage verification indicator in response to receiving an instruction for GPIO module verification;
a verification module configured to select one or more of the five groups of signals based on the detected phase verification indication flag and perform a current phase verification of the GPIO module based on the UVM architecture;
an update module configured to update the phase verification indication in response to the current phase verification passing.
In another aspect of an embodiment of the present invention, there is also provided a computer apparatus including:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of any of the methods described above.
In another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program, which when executed by a processor implements the steps of any one of the above-mentioned methods.
The invention has the following beneficial technical effects: according to the method for verifying the GPIO module based on the UVM, the signals of the GPIO module are divided into five groups based on the signal category; responding to a received instruction verified by the GPIO module, and detecting a stage verification indication mark; selecting one or more of the five groups of signals based on the detected stage verification indication mark and verifying the current stage of the GPIO module based on the UVM architecture; in response to the passing of the verification of the current stage, the technical scheme of updating the stage verification indication mark can improve the verification efficiency, reduce the number and the correlation of the excitation, reduce the judgment logic in scoreboard classes and accelerate the verification convergence speed.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic flow diagram of a method of UVM-based GPIO module authentication in accordance with one embodiment of the present invention;
fig. 2 is a schematic diagram of a UVM architecture according to an embodiment of the invention;
fig. 3 is a schematic diagram of an apparatus for UVM-based GPIO module authentication according to one embodiment of the present invention;
FIG. 4 is a schematic diagram of a computer device according to one embodiment of the present invention;
fig. 5 is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
In view of the above objects, a first aspect of the embodiments of the present invention proposes an embodiment of a method for UVM-based GPIO module verification. Fig. 1 shows a schematic flow diagram of the method.
As shown in fig. 1, the method may include the steps of:
s1 divides the signals of the GPIO modules into five groups based on the signal class.
The five groups of signals are respectively the first group of signals which are related to the bus protocol; the second group of signals are internal input/output signals, direction control signals and multiplexing priority signals; the third group of signals are external input signals; the fourth group of signals are external output signals; the fifth set of signals are the partial read write register and internal register signals in the DUT.
S2 detects a phase verification indication flag in response to receiving the instruction for GPIO module verification.
The stage verification indication mark comprises a register read-write verification mark, a basic input and output verification mark, an interruption verification mark and a multiplexing verification mark.
S3 selects one or more of the five sets of signals based on the detected phase verification indication flag and performs current phase verification of the GPIO module based on the UVM architecture.
S4 updates the phase verification indicator in response to the current phase verification passing.
And if the current stage passes the verification, updating the stage verification indication mark and performing the verification of the next stage, and if the current stage fails the verification, stopping the verification and giving an alarm.
As shown in fig. 2, the UVM architecture of the present invention includes:
the sequence class is used to generate constrained random stimuli;
the sequence class is used for receiving a transaction class (data packet) generated in the sequence and sending the transaction class to the driver;
the driver class analyzes the received transaction and sends a signal to a design to be tested according to the DUT (design to be tested) time sequence and a period;
the imonitor class detects the value of the input port of the design to be tested and packs and sends the signal to the scoreboard class;
the omotor class detects the value of the output port of the design to be tested, packs the signal and sends the signal to the scoreboard class;
scoreboard-like comparisons whether the resulting stimulus produced the correct output as intended;
the env class is used to interconnect the above components.
For different stages of verification, the coverage value is updated each time a stimulus is generated by using a callback function in the driver class, by using a coverage-driven based global flag signal in the env class to indicate the verification stage. In addition, in different verification stages, the behaviors of each component are different, for example, sequences use different signal groups for random excitation generation, so that signals needing to be driven in the verification process can be reduced, the time sequence relation among the signals is reduced, and the design difficulty is simplified; the monitor class will also sample different signals at different stages. By a phased approach, the generation, reception and comparison of signals can be focused on the part at the respective stage, thereby reducing the implementation complexity of the individual components.
In each verification stage, each time the driver class sends an excitation, coverage rate information required by the stage is collected by calling a callback function, and after the scoreboard class comparison is passed, if the coverage rate reaches an expected value, the stage indication mark is updated, so that each component releases the memory space applied by the stage, and the next stage of testing is started.
By the technical scheme of the invention, the verification efficiency can be improved, the number and the correlation of the excitations can be reduced, the judgment logic in scoreboard classes is reduced, and the verification convergence speed can be accelerated.
In a preferred embodiment of the present invention, the five sets of signals are:
the first group of signals are bus protocol related signals;
the second group of signals are internal input/output signals, direction control signals and multiplexing priority signals;
the third group of signals are external input signals;
the fourth group of signals are external output signals;
the fifth set of signals are the partial read write register and internal register signals in the DUT.
In a preferred embodiment of the present invention, the selecting one or more of the five sets of signals based on the detected indicator and performing the current stage verification of the GPIO module based on the UVM architecture comprises:
selecting a first set of signals in response to detecting that the phase verification indication flag is register read-write verification;
the sequence type in the UVM structure randomizes the register address and data, the driver type receives random register information and sends out bus write operation according to a bus protocol, and the write operation stores the data corresponding to the address after the corresponding operation is carried out on the data through the register function in the DUT;
after the randomized waiting time, performing bus reading operation on the address, detecting bus signals by the monitor, sampling the address and data at the effective moment of a bus protocol, maintaining an associated array by the scoreboard, using the address as an index of the array, and comparing the data corresponding to the address in the array with the sampled and read data of the monitor by the reading operation to judge the reading and writing correctness;
the register read-write verification passes in response to the read-write being correct and the address being overwritten the desired number of times.
In a preferred embodiment of the present invention, the selecting one or more of the five sets of signals based on the detected indicator and performing the current stage verification of the GPIO module based on the UVM architecture comprises:
in response to detecting that the phase verification indication flag is a basic input output verification, selecting a third, fourth and fifth set (direction register, data transmit register, data receive register (read only)) of signals;
the sequence class in the UVM structure randomizes directions and data sending registers in a third group and a fifth group according to the sequence, a driver class drives a third group signal port of a DUT, a register value in the DUT is modified through a back door access method, a transaction data packet is sent to a scoreboard class, an omotor class back door accesses a data receiving register, a fourth group signal in the DUT is detected, information is sent to the scoreboard class, and the scoreboard class compares the values of the third group signal and a receiving register in the fifth group signal, the fourth group signal and a sending register in the fifth group signal based on the value of the direction register so as to judge the basic input and output functions;
and responding to the input excitation meeting the coverage rate requirement, and the basic input and output passes the verification.
In a preferred embodiment of the present invention, the selecting one or more of the five sets of signals based on the detected indicator and performing the current stage verification of the GPIO module based on the UVM architecture comprises:
in response to detecting that the phase verification indication flag is interrupt verification, selecting a first set, a third set, and a fifth set (direction register, interrupt enable register, interrupt status register) of signals;
the sequence class in the UVM structure randomizes the direction and the interrupt enabling register in the third group and the fifth group of signals according to the sequence, the driver class drives a third group signal port of the DUT, the register value in the DUT is modified through a back door access method, a transaction data packet is sent to the scoreboard class, the rear door of the omonor class accesses an interrupt state register and sends information to the scoreboard class, and the scoreboard class compares the values of the receiving register in the third group signal and the fifth group signal based on the value of the direction register so as to judge the interrupt generating function;
the sequence type randomizes a first group of signals, the driver type drives a DUT (device under test) by generating a bus protocol, and transmits a transaction data packet to the scoreboard type, the omotor type accesses an interrupt state register through a backdoor and transmits information to the scoreboard type, and the scoreboard type compares an interrupt register value and a bus write-in value so as to judge an interrupt clearing function;
and interrupting the verification to pass in response to the input excitation meeting the coverage rate requirement.
In a preferred embodiment of the present invention, the selecting one or more of the five sets of signals based on the detected indicator and performing the current stage verification of the GPIO module based on the UVM architecture comprises:
selecting a second, third and fourth set of signals in response to detecting that the phase verification indicator is a multiplex function verification;
the sequence class in the UVM structure randomizes a second group of input signals and a third group of signals, the driver class drives a second group of signal input ports and a third group of signal input ports of the DUT, transmits a transaction data packet to the scoreboard class, the omonitor class detects a second group of output signals and a fourth group of output signals and transmits information to the scoreboard class, and the scoreboard class judges a direction control signal and a multiplexing priority signal by comparing an internal input in the second group with an external output in the fourth group and an internal output in the second group with an external input signal in the third group so as to judge a multiplexing function;
the multiplexing function verifies in response to the input stimulus satisfying the coverage requirement.
In a preferred embodiment of the present invention, the method further comprises:
and stopping verification and sending out a warning in response to the current stage verification failing.
The invention is based on the UVM verification platform, has strong universality, high verification efficiency and complete function coverage. Meanwhile, aiming at the design to be tested, the concept of segmented verification is adopted, the stage indication marks are used, and the signals are grouped, so that the platform design is simplified in each design stage, for example, the number and the correlation of excitation are reduced, the judgment logic in the scoreboard is reduced, and the verification convergence speed is accelerated.
It should be noted that, as will be understood by those skilled in the art, all or part of the processes in the methods of the above embodiments may be implemented by instructing relevant hardware through a computer program, and the above programs may be stored in a computer-readable storage medium, and when executed, the programs may include the processes of the embodiments of the methods as described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.
In view of the above-mentioned objects, a second aspect of the embodiments of the present invention proposes a device for UVM-based GPIO module verification, as shown in fig. 3, where the device 200 includes:
the dividing module is configured to divide the signals of the GPIO module into five groups based on the signal category;
a detection module configured to detect a stage verification indicator in response to receiving an instruction for GPIO module verification;
a verification module configured to select one or more of the five groups of signals based on the detected phase verification indication flag and perform a current phase verification of the GPIO module based on the UVM architecture;
an update module configured to update the phase verification indication in response to the current phase verification passing.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device. Fig. 4 is a schematic diagram of an embodiment of a computer device provided by the present invention. As shown in fig. 4, an embodiment of the present invention includes the following means: at least one processor S21; and a memory S22, the memory S22 storing computer instructions S23 executable on the processor, the instructions when executed by the processor implementing the method of:
dividing the signals of the GPIO module into five groups based on the signal category;
responding to a received instruction verified by the GPIO module, and detecting a stage verification indication mark;
selecting one or more of the five groups of signals based on the detected stage verification indication mark and verifying the current stage of the GPIO module based on the UVM architecture;
in response to the current phase verification passing, the phase verification indication flag is updated.
In a preferred embodiment of the present invention, the five sets of signals are:
the first group of signals are bus protocol related signals;
the second group of signals are internal input/output signals, direction control signals and multiplexing priority signals;
the third group of signals are external input signals;
the fourth group of signals are external output signals;
the fifth set of signals are the partial read write register and internal register signals in the DUT.
In a preferred embodiment of the present invention, the selecting one or more of the five sets of signals based on the detected indicator and performing the current stage verification of the GPIO module based on the UVM architecture comprises:
selecting a first set of signals in response to detecting that the phase verification indication flag is register read-write verification;
the sequence type in the UVM structure randomizes the register address and data, the driver type receives random register information and sends out bus write operation according to a bus protocol, and the write operation stores the data corresponding to the address after the corresponding operation is carried out on the data through the register function in the DUT;
after the randomized waiting time, performing bus reading operation on the address, detecting bus signals by the monitor, sampling the address and data at the effective moment of a bus protocol, maintaining an associated array by the scoreboard, using the address as an index of the array, and comparing the data corresponding to the address in the array with the sampled and read data of the monitor by the reading operation to judge the reading and writing correctness;
the register read-write verification passes in response to the read-write being correct and the address being overwritten the desired number of times.
In a preferred embodiment of the present invention, the selecting one or more of the five sets of signals based on the detected indicator and performing the current stage verification of the GPIO module based on the UVM architecture comprises:
selecting a third, fourth, and fifth set of signals in response to detecting that the phase verification indicator is a basic input output verification;
the sequence class in the UVM structure randomizes directions and data sending registers in a third group and a fifth group according to the sequence, a driver class drives a third group signal port of a DUT, a register value in the DUT is modified through a back door access method, a transaction data packet is sent to a scoreboard class, an omotor class back door accesses a data receiving register, a fourth group signal in the DUT is detected, information is sent to the scoreboard class, and the scoreboard class compares the values of the third group signal and a receiving register in the fifth group signal, the fourth group signal and a sending register in the fifth group signal based on the value of the direction register so as to judge the basic input and output functions;
and responding to the input excitation meeting the coverage rate requirement, and the basic input and output passes the verification.
In a preferred embodiment of the present invention, the selecting one or more of the five sets of signals based on the detected indicator and performing the current stage verification of the GPIO module based on the UVM architecture comprises:
selecting a first, third, and fifth set of signals in response to detecting that the phase verification indicator is an interrupt verification;
the sequence class in the UVM structure randomizes the direction and the interrupt enabling register in the third group and the fifth group of signals according to the sequence, the driver class drives a third group signal port of the DUT, the register value in the DUT is modified through a back door access method, a transaction data packet is sent to the scoreboard class, the rear door of the omonor class accesses an interrupt state register and sends information to the scoreboard class, and the scoreboard class compares the values of the receiving register in the third group signal and the fifth group signal based on the value of the direction register so as to judge the interrupt generating function;
the sequence type randomizes a first group of signals, the driver type drives a DUT (device under test) by generating a bus protocol, and transmits a transaction data packet to the scoreboard type, the omotor type accesses an interrupt state register through a backdoor and transmits information to the scoreboard type, and the scoreboard type compares an interrupt register value and a bus write-in value so as to judge an interrupt clearing function;
and interrupting the verification to pass in response to the input excitation meeting the coverage rate requirement.
In a preferred embodiment of the present invention, the selecting one or more of the five sets of signals based on the detected indicator and performing the current stage verification of the GPIO module based on the UVM architecture comprises:
selecting a second, third and fourth set of signals in response to detecting that the phase verification indicator is a multiplex function verification;
the sequence class in the UVM structure randomizes a second group of input signals and a third group of signals, the driver class drives a second group of signal input ports and a third group of signal input ports of the DUT, transmits a transaction data packet to the scoreboard class, the omonitor class detects a second group of output signals and a fourth group of output signals and transmits information to the scoreboard class, and the scoreboard class judges a direction control signal and a multiplexing priority signal by comparing an internal input in the second group with an external output in the fourth group and an internal output in the second group with an external input signal in the third group so as to judge a multiplexing function;
the multiplexing function verifies in response to the input stimulus satisfying the coverage requirement.
In a preferred embodiment of the present invention, the method further comprises:
and stopping verification and sending out a warning in response to the current stage verification failing.
In view of the above object, a fourth aspect of the embodiments of the present invention proposes a computer-readable storage medium. FIG. 5 is a schematic diagram illustrating an embodiment of a computer-readable storage medium provided by the present invention. As shown in fig. 5, the computer readable storage medium stores S31 a computer program that, when executed by a processor, performs the method as described above S32.
Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method for verifying GPIO module based on UVM is characterized by comprising the following steps:
dividing the signals of the GPIO module into five groups based on the signal category;
responding to a received instruction verified by the GPIO module, and detecting a stage verification indication mark;
selecting one or more of the five groups of signals based on the detected stage verification indication mark and verifying the current stage of the GPIO module based on the UVM architecture;
in response to the current phase verification passing, the phase verification indication flag is updated.
2. The method of claim 1, wherein the five sets of signals are:
the first group of signals are bus protocol related signals;
the second group of signals are internal input/output signals, direction control signals and multiplexing priority signals;
the third group of signals are external input signals;
the fourth group of signals are external output signals;
the fifth set of signals are the partial read write register and internal register signals in the DUT.
3. The method of claim 2, wherein selecting one or more of the five sets of signals based on the detected indicator and performing the current stage of verification of the GPIO module based on the UVM architecture comprises:
selecting a first set of signals in response to detecting that the phase verification indication flag is register read-write verification;
the sequence type in the UVM structure randomizes the register address and data, the driver type receives random register information and sends out bus write operation according to a bus protocol, and the write operation stores the data corresponding to the address after the corresponding operation is carried out on the data through the register function in the DUT;
after the randomized waiting time, performing bus reading operation on the address, detecting bus signals by the monitor, sampling the address and data at the effective moment of a bus protocol, maintaining an associated array by the scoreboard, using the address as an index of the array, and comparing the data corresponding to the address in the array with the sampled and read data of the monitor by the reading operation to judge the reading and writing correctness;
the register read-write verification passes in response to the read-write being correct and the address being overwritten the desired number of times.
4. The method of claim 2, wherein selecting one or more of the five sets of signals based on the detected indicator and performing the current stage of verification of the GPIO module based on the UVM architecture comprises:
selecting a third, fourth, and fifth set of signals in response to detecting that the phase verification indicator is a basic input output verification;
the sequence class in the UVM structure randomizes directions and data sending registers in a third group and a fifth group according to the sequence, a driver class drives a third group signal port of a DUT, a register value in the DUT is modified through a back door access method, a transaction data packet is sent to a scoreboard class, an omotor class back door accesses a data receiving register, a fourth group signal in the DUT is detected, information is sent to the scoreboard class, and the scoreboard class compares the values of the third group signal and a receiving register in the fifth group signal, the fourth group signal and a sending register in the fifth group signal based on the value of the direction register so as to judge the basic input and output functions;
and responding to the input excitation meeting the coverage rate requirement, and the basic input and output passes the verification.
5. The method of claim 2, wherein selecting one or more of the five sets of signals based on the detected indicator and performing the current stage of verification of the GPIO module based on the UVM architecture comprises:
selecting a first, third, and fifth set of signals in response to detecting that the phase verification indicator is an interrupt verification;
the sequence class in the UVM structure randomizes the direction and the interrupt enabling register in the third group and the fifth group of signals according to the sequence, the driver class drives a third group signal port of the DUT, the register value in the DUT is modified through a back door access method, a transaction data packet is sent to the scoreboard class, the rear door of the omonor class accesses an interrupt state register and sends information to the scoreboard class, and the scoreboard class compares the values of the receiving register in the third group signal and the fifth group signal based on the value of the direction register so as to judge the interrupt generating function;
the sequence type randomizes a first group of signals, the driver type drives a DUT (device under test) by generating a bus protocol, and transmits a transaction data packet to the scoreboard type, the omotor type accesses an interrupt state register through a backdoor and transmits information to the scoreboard type, and the scoreboard type compares an interrupt register value and a bus write-in value so as to judge an interrupt clearing function;
and interrupting the verification to pass in response to the input excitation meeting the coverage rate requirement.
6. The method of claim 2, wherein selecting one or more of the five sets of signals based on the detected indicator and performing the current stage of verification of the GPIO module based on the UVM architecture comprises:
selecting a second, third and fourth set of signals in response to detecting that the phase verification indicator is a multiplex function verification;
the sequence class in the UVM structure randomizes a second group of input signals and a third group of signals, the driver class drives a second group of signal input ports and a third group of signal input ports of the DUT, transmits a transaction data packet to the scoreboard class, the omonitor class detects a second group of output signals and a fourth group of output signals and transmits information to the scoreboard class, and the scoreboard class judges a direction control signal and a multiplexing priority signal by comparing an internal input in the second group with an external output in the fourth group and an internal output in the second group with an external input signal in the third group so as to judge a multiplexing function;
the multiplexing function verifies in response to the input stimulus satisfying the coverage requirement.
7. The method of claim 1, further comprising:
and stopping verification and sending out a warning in response to the current stage verification failing.
8. An apparatus for UVM based GPIO module authentication, the apparatus comprising:
a partitioning module configured to partition signals of the GPIO modules into five groups based on signal class;
a detection module configured to detect a stage verification indication flag in response to receiving an instruction for GPIO module verification;
a verification module configured to select one or more of the five sets of signals based on the detected phase verification indicator and perform a current phase verification of the GPIO module based on the UVM architecture;
an update module configured to update the phase verification indication in response to a current phase verification passing.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 7.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.
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