CN113608602A - Reset method and device of system on chip - Google Patents
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- G06F15/00—Digital computers in general; Data processing equipment in general
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- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
Abstract
The invention discloses a reset method and a reset device of a system on a chip, wherein the method comprises the following steps: continuously detecting, by a detection module, whether one or more of a plurality of functional modules in a system-on-chip need to be actively reset; sending one or more reset marks corresponding to one or more functional modules needing to be actively reset to a reset execution module; sending a reset signal to one or more functional modules needing to be actively reset corresponding to one or more reset marks by a reset execution module, and resetting the one or more functional modules needing to be actively reset; and sending one or more reset messages corresponding to one or more functional modules needing to be actively reset to the record generating module by the detection module so that the record generating module records the one or more reset messages. The invention can improve the reset flexibility, reduce the CPU frequency occupation, is compatible with active reset and accurate reset, and simultaneously keeps the reset record.
Description
Technical Field
The present invention relates to the field of system control, and more particularly, to a method and apparatus for resetting a system on a chip.
Background
There are many functional blocks on a SoC (system on a chip), and almost all blocks have a reset signal. The reset signal is a pulse signal with a certain width, and can reset the target module. The reset operation may restore the preset state of each functional module. The reset operation is performed when the module is abnormal or the working state is to be reset according to the program requirement. According to the functional requirements, a plurality of different reset signals are required on the whole SoC, and each reset signal controls a corresponding reset domain respectively. These reset signals are divided into external reset signals and internal reset signals according to the source; the reset range is divided into a global reset signal and a local reset signal. A large number of reset signals need to be managed in a unified mode, and information such as occurrence reasons and frequency of reset operation is recorded, so that the analysis of the advantages and the disadvantages of the design of each module in the current version SoC is facilitated.
The reset of SoC currently takes the following form: (1) power-on reset: when the system is powered on, global reset is carried out, and all chips need to be initialized. (2) Hardware reset: and generally, the system circuit is reset through a key. (3) Software resetting: a reset mode with the highest executed frequency; and sending an interrupt signal to the CPU after each module is abnormal, executing an interrupt service program after the CPU receives the interrupt signal, resetting if the abnormality can be solved by resetting, and sending a reset signal to the abnormal module by the CPU.
The software reset of the prior art occupies too much CPU frequency, the CPU can not process other programs when executing the interrupt service program, and the reset operation is generally included in the interrupt service program, so the high-frequency software reset operation occupies the CPU for a high frequency. Meanwhile, the prior art cannot specify a specific module to perform reset operation, and needs to perform global reset or passive reset, so that the flexibility is insufficient. In addition, the SoC in the prior art cannot record when resetting, and information such as the reason and frequency of resetting cannot be reserved, which is not favorable for providing data experience support for the optimization design of each module, and is also not favorable for quickly positioning the reason and the position of system faults.
Aiming at the problems of low reset flexibility, incapability of actively resetting, incapability of accurately resetting, no reservation of reset records and excessive CPU frequency occupation in the prior art, no effective solution is available at present.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a reset method and apparatus for a system on a chip, which can improve the flexibility of resetting, reduce the CPU frequency occupation, and are compatible with active reset and accurate reset, while keeping the reset record.
In view of the above object, a first aspect of the embodiments of the present invention provides a reset method for a system on chip, including the following steps:
continuously detecting, by a detection module, whether one or more of a plurality of functional modules in a system-on-chip need to be actively reset;
in response to detecting by the detection module that there are one or more functional modules that need to be actively reset, issuing one or more reset flags to the reset execution module corresponding to the one or more functional modules that need to be actively reset;
in response to receiving one or more reset flags by the reset execution module, sending a reset signal to one or more functional modules needing to be actively reset corresponding to the one or more reset flags, and resetting the one or more functional modules needing to be actively reset;
and in response to the detection module detecting that one or more functional modules need to be actively reset, sending one or more reset information corresponding to the one or more functional modules needing to be actively reset to the record generation module, and causing the record generation module to record the one or more reset information.
In some embodiments, continuously detecting, by the detection module, whether one or more of the plurality of functional modules in the system-on-chip need to be actively reset comprises: the method comprises the steps of establishing communication connection between a detection module and a plurality of functional modules by using a bus, and periodically detecting whether one or more of the functional modules are in an abnormal state which can be recovered to a normal working state only through resetting by the detection module through the bus.
In some embodiments, continuously detecting, by the detection module, whether one or more of the plurality of functional modules in the system-on-chip need to be actively reset comprises: the detection module is communicatively coupled to the command source and determines that the indicated one or more functional modules need to be actively reset in response to the detection module receiving a reset command to perform a reset for the one or more functional modules.
In some embodiments, the reset instruction includes a module code and an operation code, wherein the operation code indicates that the reset operation is performed, and the module code includes a functional module code of one or more functional modules that need to perform the reset.
In some embodiments, the reset instruction is configured as an extra coded bit that extends the use.
In some embodiments, the method further comprises performing the steps of:
in response to receiving the one or more reset flags by the reset execution module, a feedback signal is also sent to a central processor of the system-on-chip informing that one or more functional modules that need to be actively reset have been reset.
In some embodiments, the detection module and the reset execution module both operate independently of the central processor.
In some embodiments, the reset information includes a module code including a functional module code of one or more functional modules that need to perform a reset, and a reset reason including an active reset based on an exception status or an active reset based on a reset instruction.
In some embodiments, causing the record generation module to record the one or more reset messages comprises: and enabling the record generation module to write the reset information into the reset information by taking the time of receiving the reset information as a time stamp, and further enabling the reset information with the time stamp written into the storage area to be persistent in a binary coding mode.
A second aspect of an embodiment of the present invention provides a reset apparatus for a system on chip, including:
a processor;
a controller storing program code executable by a processor, the processor executing the following steps when executing the program code:
continuously detecting, by a detection module, whether one or more of a plurality of functional modules in a system-on-chip need to be actively reset;
in response to detecting by the detection module that there are one or more functional modules that need to be actively reset, issuing one or more reset flags to the reset execution module corresponding to the one or more functional modules that need to be actively reset;
in response to receiving one or more reset flags by the reset execution module, sending a reset signal to one or more functional modules needing to be actively reset corresponding to the one or more reset flags, and resetting the one or more functional modules needing to be actively reset;
and in response to the detection module detecting that one or more functional modules need to be actively reset, sending one or more reset information corresponding to the one or more functional modules needing to be actively reset to the record generation module, and causing the record generation module to record the one or more reset information.
In some embodiments, continuously detecting, by the detection module, whether one or more of the plurality of functional modules in the system-on-chip need to be actively reset comprises: the method comprises the steps of establishing communication connection between a detection module and a plurality of functional modules by using a bus, and periodically detecting whether one or more of the functional modules are in an abnormal state which can be recovered to a normal working state only through resetting by the detection module through the bus.
In some embodiments, continuously detecting, by the detection module, whether one or more of the plurality of functional modules in the system-on-chip need to be actively reset comprises: the detection module is communicatively coupled to the command source and determines that the indicated one or more functional modules need to be actively reset in response to the detection module receiving a reset command to perform a reset for the one or more functional modules.
In some embodiments, the reset instruction includes a module code and an operation code, wherein the operation code indicates that the reset operation is performed, and the module code includes a functional module code of one or more functional modules that need to perform the reset.
In some embodiments, the reset instruction is configured as an extra coded bit that extends the use.
In some embodiments, further comprising performing the steps of:
in response to receiving the one or more reset flags by the reset execution module, a feedback signal is also sent to a central processor of the system-on-chip informing that one or more functional modules that need to be actively reset have been reset.
In some embodiments, the detection module and the reset execution module both operate independently of the central processor.
In some embodiments, the reset information includes a module code including a functional module code of one or more functional modules that need to perform a reset, and a reset reason including an active reset based on an exception status or an active reset based on a reset instruction.
In some embodiments, causing the record generation module to record the one or more reset messages comprises: and enabling the record generation module to write the reset information into the reset information by taking the time of receiving the reset information as a time stamp, and further enabling the reset information with the time stamp written into the storage area to be persistent in a binary coding mode.
The invention has the following beneficial technical effects: according to the reset method and the reset device of the system on chip provided by the embodiment of the invention, whether one or more functional modules in the system on chip need to be actively reset is continuously detected by the detection module; in response to detecting by the detection module that there are one or more functional modules that need to be actively reset, issuing one or more reset flags to the reset execution module corresponding to the one or more functional modules that need to be actively reset; in response to receiving one or more reset flags by the reset execution module, sending a reset signal to one or more functional modules needing to be actively reset corresponding to the one or more reset flags, and resetting the one or more functional modules needing to be actively reset; the technical scheme that one or more reset information corresponding to one or more functional modules needing to be actively reset is sent to the record generation module in response to the detection module detecting that one or more functional modules needing to be actively reset exist, so that the record generation module records the one or more reset information can improve the reset flexibility, reduce the CPU frequency occupation, be compatible with active reset and accurate reset, and simultaneously reserve the reset record.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flowchart illustrating a reset method of a system on a chip according to the present invention;
FIG. 2 is a block diagram of a reset method of a system on a chip according to the present invention;
fig. 3 is a structural diagram of a reset management unit of the reset method of the system on chip according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the foregoing, a first aspect of the embodiments of the present invention provides an embodiment of a reset method for a system on chip, which improves reset flexibility, reduces CPU frequency occupation, is compatible with active reset and accurate reset, and retains a reset record. Fig. 1 is a flowchart illustrating a reset method of a system on chip according to the present invention.
The reset method of the system on chip, as shown in fig. 1, includes the following steps:
step S101, a detection module continuously detects whether one or more of a plurality of functional modules in the system on chip need to be actively reset;
step S103, responding to the detection module detecting that one or more functional modules need to be actively reset, and sending one or more reset marks corresponding to the one or more functional modules needing to be actively reset to the reset execution module;
step S105, responding to the one or more reset marks received by the reset execution module, sending a reset signal to one or more functional modules needing to be actively reset corresponding to the one or more reset marks, and resetting the one or more functional modules needing to be actively reset;
step S107, in response to the detection module detecting that one or more functional modules need to be actively reset, one or more reset messages corresponding to the one or more functional modules need to be actively reset are also sent to the record generation module, and the record generation module is caused to record the one or more reset messages.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like. Embodiments of the computer program may achieve the same or similar effects as any of the preceding method embodiments to which it corresponds.
In some embodiments, continuously detecting, by the detection module, whether one or more of the plurality of functional modules in the system-on-chip need to be actively reset comprises: the method comprises the steps of establishing communication connection between a detection module and a plurality of functional modules by using a bus, and periodically detecting whether one or more of the functional modules are in an abnormal state which can be recovered to a normal working state only through resetting by the detection module through the bus.
In some embodiments, continuously detecting, by the detection module, whether one or more of the plurality of functional modules in the system-on-chip need to be actively reset comprises: the detection module is communicatively coupled to the command source and determines that the indicated one or more functional modules need to be actively reset in response to the detection module receiving a reset command to perform a reset for the one or more functional modules.
In some embodiments, the reset instruction includes a module code and an operation code, wherein the operation code indicates that the reset operation is performed, and the module code includes a functional module code of one or more functional modules that need to perform the reset.
In some embodiments, the reset instruction is configured as an extra coded bit that extends the use.
The various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
In some embodiments, the method further comprises performing the steps of:
in response to receiving the one or more reset flags by the reset execution module, a feedback signal is also sent to a central processor of the system-on-chip informing that one or more functional modules that need to be actively reset have been reset.
In some embodiments, the detection module and the reset execution module both operate independently of the central processor.
In some embodiments, the reset information includes a module code including a functional module code of one or more functional modules that need to perform a reset, and a reset reason including an active reset based on an exception status or an active reset based on a reset instruction.
In some embodiments, causing the record generation module to record the one or more reset messages comprises: and enabling the record generation module to write the reset information into the reset information by taking the time of receiving the reset information as a time stamp, and further enabling the reset information with the time stamp written into the storage area to be persistent in a binary coding mode.
The computer-readable storage media (e.g., memory) described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Fig. 2 shows the overall structure of the reset method of the system on chip, and the following further illustrates an embodiment of the present invention according to the embodiment shown in fig. 2.
The embodiment takes the reset management unit as a center, the reset management unit is embedded with a detection module, the detection module periodically acquires the current state of each module through a bus, and then the acquired current state information of the modules is detected. If the detected module is in an abnormal state which can be solved only by resetting, the reset management unit immediately resets the module through the directly connected reset signal line. The reset management unit can also reset a specific module by receiving a reset instruction. And after receiving the reset instruction, the reset management unit performs corresponding operation according to the information contained in the instruction. The reset management unit generates a reset signal and records information such as a reset module name, a reset reason, and a time stamp in the high-speed memory. Meanwhile, the management unit sends a feedback signal to the CPU to inform the CPU which module is reset, so that the CPU can reasonably arrange the work of instruction scheduling and the like.
Fig. 3 is an inside of the reset management unit. Referring to fig. 3, the detection module sets a separate reset flag for each module, and when the detected module needs to be reset, the corresponding reset flag is valid. The reset execution module is sensitive to the reset flag, and once valid, the reset signal of the corresponding module is set to be valid. When the detection module detects the module to be reset, the detection module sends the reset information (including the code of the reset module and the reset reason) to the record generation module, and the record generation module arranges the reset information and the time stamp into a binary code and stores the binary code into the designated storage area.
When the instruction is reset, the above-described flow is also executed. The reset instruction consists of an operation code and a module code. And after identifying the operation code of the instruction, the decoder sends the module code to the reset management unit, and the reset management unit immediately resets the corresponding module after receiving the module code. The bit width of the module code at least contains all the managed modules, and a plurality of bits can be set aside for later expansion.
The invention can accurately reset any managed module at any time by using the reset instruction, thereby enhancing the flexibility of reset operation; the function of recording the reset information can help technicians to quickly and accurately locate abnormal positions and reset reasons, and also helps to analyze the design advantages and disadvantages of each module in the current SoC; the detection module takes the reset out of the original interrupt service program, so that the reset operation caused by the abnormity does not need to occupy the CPU, and only needs to inform the CPU when the reset is determined.
Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention. The above-described method steps and system elements may also be implemented using a controller and a computer-readable storage medium for storing a computer program for causing the controller to implement the functions of the above-described steps or elements.
It can be seen from the foregoing embodiments that, in the reset method of the system on chip provided in the embodiments of the present invention, whether one or more of the plurality of functional modules in the system on chip needs to be actively reset is continuously detected by the detection module; in response to detecting by the detection module that there are one or more functional modules that need to be actively reset, issuing one or more reset flags to the reset execution module corresponding to the one or more functional modules that need to be actively reset; in response to receiving one or more reset flags by the reset execution module, sending a reset signal to one or more functional modules needing to be actively reset corresponding to the one or more reset flags, and resetting the one or more functional modules needing to be actively reset; the technical scheme that one or more reset information corresponding to one or more functional modules needing to be actively reset is sent to the record generation module in response to the detection module detecting that one or more functional modules needing to be actively reset exist, so that the record generation module records the one or more reset information can improve the reset flexibility, reduce the CPU frequency occupation, be compatible with active reset and accurate reset, and simultaneously reserve the reset record.
It should be particularly noted that, the steps in the embodiments of the reset method of the system on chip described above can be mutually intersected, replaced, added, and deleted, so that these reasonable permutation and combination transformations of the reset method of the system on chip also belong to the scope of the present invention, and should not limit the scope of the present invention to the described embodiments.
In view of the above, a second aspect of the embodiments of the present invention provides an embodiment of a reset apparatus for a system on chip, which improves reset flexibility, reduces CPU frequency occupation, and is compatible with active reset and precise reset while maintaining reset records. The device comprises:
a processor;
a controller storing program code executable by a processor, the processor executing the following steps when executing the program code:
continuously detecting, by a detection module, whether one or more of a plurality of functional modules in a system-on-chip need to be actively reset;
in response to detecting by the detection module that there are one or more functional modules that need to be actively reset, issuing one or more reset flags to the reset execution module corresponding to the one or more functional modules that need to be actively reset;
in response to receiving one or more reset flags by the reset execution module, sending a reset signal to one or more functional modules needing to be actively reset corresponding to the one or more reset flags, and resetting the one or more functional modules needing to be actively reset;
and in response to the detection module detecting that one or more functional modules need to be actively reset, sending one or more reset information corresponding to the one or more functional modules needing to be actively reset to the record generation module, and causing the record generation module to record the one or more reset information.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In some embodiments, continuously detecting, by the detection module, whether one or more of the plurality of functional modules in the system-on-chip need to be actively reset comprises: the method comprises the steps of establishing communication connection between a detection module and a plurality of functional modules by using a bus, and periodically detecting whether one or more of the functional modules are in an abnormal state which can be recovered to a normal working state only through resetting by the detection module through the bus.
In some embodiments, continuously detecting, by the detection module, whether one or more of the plurality of functional modules in the system-on-chip need to be actively reset comprises: the detection module is communicatively coupled to the command source and determines that the indicated one or more functional modules need to be actively reset in response to the detection module receiving a reset command to perform a reset for the one or more functional modules.
In some embodiments, the reset instruction includes a module code and an operation code, wherein the operation code indicates that the reset operation is performed, and the module code includes a functional module code of one or more functional modules that need to perform the reset.
In some embodiments, the reset instruction is configured as an extra coded bit that extends the use.
In some embodiments, further comprising performing the steps of:
in response to receiving the one or more reset flags by the reset execution module, a feedback signal is also sent to a central processor of the system-on-chip informing that one or more functional modules that need to be actively reset have been reset.
In some embodiments, the detection module and the reset execution module both operate independently of the central processor.
In some embodiments, the reset information includes a module code including a functional module code of one or more functional modules that need to perform a reset, and a reset reason including an active reset based on an exception status or an active reset based on a reset instruction.
In some embodiments, causing the record generation module to record the one or more reset messages comprises: and enabling the record generation module to write the reset information into the reset information by taking the time of receiving the reset information as a time stamp, and further enabling the reset information with the time stamp written into the storage area to be persistent in a binary coding mode.
The apparatuses and devices disclosed in the embodiments of the present invention may be various electronic terminal devices, such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer (PAD), a smart television, and the like, or may be a large terminal device, such as a server, and therefore the scope of protection disclosed in the embodiments of the present invention should not be limited to a specific type of apparatus and device. The client disclosed in the embodiment of the present invention may be applied to any one of the above electronic terminal devices in the form of electronic hardware, computer software, or a combination of both.
As can be seen from the foregoing embodiments, the reset apparatus of the system on chip provided in the embodiments of the present invention continuously detects, by the detection module, whether one or more of the plurality of functional modules in the system on chip need to be actively reset; in response to detecting by the detection module that there are one or more functional modules that need to be actively reset, issuing one or more reset flags to the reset execution module corresponding to the one or more functional modules that need to be actively reset; in response to receiving one or more reset flags by the reset execution module, sending a reset signal to one or more functional modules needing to be actively reset corresponding to the one or more reset flags, and resetting the one or more functional modules needing to be actively reset; the technical scheme that one or more reset information corresponding to one or more functional modules needing to be actively reset is sent to the record generation module in response to the detection module detecting that one or more functional modules needing to be actively reset exist, so that the record generation module records the one or more reset information can improve the reset flexibility, reduce the CPU frequency occupation, be compatible with active reset and accurate reset, and simultaneously reserve the reset record.
It should be particularly noted that the above-mentioned embodiment of the apparatus employs the embodiment of the reset method of the system on chip to specifically describe the working process of each module, and those skilled in the art can easily think that these modules are applied to other embodiments of the reset method of the system on chip. Of course, since the steps in the reset method embodiment of the system on chip can be mutually intersected, replaced, added, and deleted, these reasonable permutations and combinations should also fall within the scope of the present invention, and should not limit the scope of the present invention to the embodiment.
The memory, which is a non-volatile computer-readable storage medium, may be used to store a non-volatile software program, a non-volatile computer-executable program, and modules, such as program instructions/modules corresponding to the reset method of the system on chip in the embodiments of the present application. The processor executes various functional applications of the server and data processing by running the nonvolatile software program, instructions and modules stored in the memory, that is, the reset method of the system on chip of the above-mentioned method embodiment is realized.
The memory may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to use of a reset device of the system on chip, and the like. Further, the memory may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, the memory optionally includes memory located remotely from the processor, and such remote memory may be coupled to the local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The embodiment of the present invention may further include a corresponding computer-readable storage medium, where the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions may execute the reset method of the system on chip in any of the above method embodiments and the reset apparatus for implementing the system on chip in any of the above apparatus embodiments. Embodiments of the computer-readable storage medium may achieve the same or similar effects as any of the aforementioned method and apparatus embodiments corresponding thereto.
Embodiments of the present invention may also include a corresponding computer program product comprising a computer program stored on a computer-readable storage medium, the computer program comprising instructions that, when executed by a computer, cause the computer to perform a method for resetting a system on chip in any of the above-described method embodiments and a resetting apparatus for implementing the system on chip in any of the above-described apparatus embodiments. Embodiments of the computer program product may achieve the same or similar effects as any of the aforementioned method and apparatus embodiments corresponding thereto.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like. Embodiments of the computer program may achieve the same or similar effects as any of the preceding method embodiments to which it corresponds.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method of resetting a system on a chip, comprising performing the steps of:
continuously detecting, by a detection module, whether one or more of a plurality of functional modules in a system-on-chip need to be actively reset;
in response to detecting, by the detection module, that there are one or more of the functional modules that need to be actively reset, issuing one or more reset flags to a reset execution module corresponding to the one or more of the functional modules that need to be actively reset;
in response to receiving one or more reset flags by a reset execution module, issuing a reset signal to one or more functional modules that need to be actively reset corresponding to the one or more reset flags, resetting the one or more functional modules that need to be actively reset;
in response to detecting, by the detection module, that there are one or more functional modules that need to be actively reset, further issuing, to a record generation module, one or more reset messages corresponding to the one or more functional modules that need to be actively reset, causing the record generation module to record the one or more reset messages.
2. The method of claim 1, wherein continuously detecting, by a detection module, whether one or more of a plurality of functional modules in a system-on-chip need to be actively reset comprises: the method comprises the steps of establishing communication connection between the detection module and a plurality of functional modules by using a bus, and periodically detecting whether one or more of the functional modules are in an abnormal state which can be recovered to a normal working state only through resetting by the detection module through the bus.
3. The method of claim 1, wherein continuously detecting, by a detection module, whether one or more of a plurality of functional modules in a system-on-chip need to be actively reset comprises: communicatively connecting the detection module to a source of instructions and determining that the indicated one or more of the functional modules needs to be actively reset in response to the detection module receiving a reset instruction to perform a reset for the one or more of the functional modules.
4. The method of claim 3, wherein the reset instruction comprises a module code and an operation code, wherein the operation code indicates to perform the reset operation, and wherein the module code comprises a functional module code of one or more of the functional modules that need to be reset.
5. The method of claim 4, wherein the reset instruction is configured as an extra coded bit for extended use.
6. The method of claim 1, further comprising performing the steps of:
in response to receiving one or more of the reset flags by the reset execution module, a feedback signal is also sent to a central processor of the system-on-chip informing that one or more of the functional modules that need to be actively reset have been reset.
7. The method of claim 6, wherein the detection module and the reset execution module each operate independently of a central processor.
8. The method of claim 1, wherein the reset information comprises a module code and a reset reason, wherein the module code comprises a functional module code of one or more functional modules that need to perform a reset, and the reset reason comprises an active reset based on an abnormal state or an active reset based on a reset instruction.
9. The method of claim 8, wherein causing the record generation module to record one or more of the reset messages comprises: and enabling the record generation module to write the time of receiving the reset information into the reset information as a time stamp, and further enabling the reset information written into the time stamp to be persisted into a storage area in a binary coding mode.
10. A reset device for a system-on-chip, comprising:
a processor;
a controller storing program code executable by the processor, the processor executing the following steps when executing the program code:
continuously detecting, by a detection module, whether one or more of a plurality of functional modules in a system-on-chip need to be actively reset;
in response to detecting, by the detection module, that there are one or more of the functional modules that need to be actively reset, issuing one or more reset flags to a reset execution module corresponding to the one or more of the functional modules that need to be actively reset;
in response to receiving one or more reset flags by a reset execution module, issuing a reset signal to one or more functional modules that need to be actively reset corresponding to the one or more reset flags, resetting the one or more functional modules that need to be actively reset;
in response to detecting, by the detection module, that there are one or more functional modules that need to be actively reset, further issuing, to a record generation module, one or more reset messages corresponding to the one or more functional modules that need to be actively reset, causing the record generation module to record the one or more reset messages.
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