CN113594187A - TFT (thin film transistor) structure touch array substrate with low parasitic capacitance and preparation method thereof - Google Patents
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000005416 organic matter Substances 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
- G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- G—PHYSICS
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Abstract
The invention discloses a TFT (thin film transistor) structure touch array substrate with low parasitic capacitance and a preparation method thereof, wherein the TFT structure touch array substrate comprises a substrate, a grid electrode layer, a grid electrode insulating layer, a blocking layer, an electrode layer, a passivation layer, a first planarization layer, a third electrode layer, a VA (vertical alignment) layer, a second planarization layer, an insulating layer CH and a pixel electrode, wherein the grid electrode layer, the grid electrode insulating layer, the blocking layer, the electrode layer, the passivation layer, the first planarization layer, the third electrode layer, the VA layer, the second planarization layer, the insulating layer CH and the pixel electrode are sequentially arranged on the substrate; the electrode layer part is in contact connection with the grid electrode insulating layer through the barrier layer; the third electrode layer is arranged in a region between the first planarization layer and the VA layer beside the pixel through hole; the bottom surface of the insulating layer CH is provided with a common electrode COM corresponding to the third electrode layer region, so that part of the common electrode COM is in contact connection with the third electrode layer CM through the touch via hole. The two-layer OC film layer structure of the invention ensures that the parasitic capacitance is lower, and meets the specification requirement of an active pen.
Description
Technical Field
The invention relates to the technical field of touch panels, in particular to a TFT (thin film transistor) structure touch array substrate with low parasitic capacitance and a preparation method thereof.
Background
As shown in fig. 1, the material of the VA insulating layer is silicon nitride, which needs to be slowly formed, the film forming time is too long, the film machine is easy to be heated and crashed, and the process time is also time-consuming, so that the manufacturing cost is greatly increased, therefore, the VA insulating layer cannot be designed to be too thick. However, the VA film layer is too thin, which results in too large parasitic capacitance and does not meet the requirement of lower parasitic capacitance of the active pen.
Disclosure of Invention
The invention aims to provide a TFT structure touch array substrate with low parasitic capacitance and a preparation method thereof.
The technical scheme adopted by the invention is as follows:
a TFT structure touch array substrate with low parasitic capacitance comprises a substrate, a grid electrode layer GE, a grid electrode insulating layer GI, an active layer SE, a blocking layer ES, an electrode layer SD, a passivation layer PV, a first planarization layer OC, a third electrode layer CM, a VA layer, a second planarization layer OC2, an insulating layer CH and a pixel electrode PE which are sequentially arranged on the substrate, wherein the pixel electrode PE covers partial area of the insulating layer CH and is positioned above partial electrode layer SD, pixel through holes are correspondingly arranged in the vertical direction of the passivation layer PV, the first planarization layer OC, the VA layer OC2 and the insulating layer CH between the pixel electrode PE and the electrode layer SD, and the pixel electrode PE is arranged in the pixel through hole and is in contact connection with the corresponding electrode layer SD area through the pixel through hole; the electrode layer SD part is in contact connection with the active layer SE through the barrier layer ES;
the third electrode layer CM is arranged in the region between the first planarization layer OC and the VA layer beside the pixel via hole; the bottom surface of the insulating layer CH is provided with a common electrode COM corresponding to the area of the third electrode layer CM, and the second planarization layer OC2 and the VA layer are provided with touch via holes corresponding to the middle area of the third electrode layer CM, so that part of the common electrode COM is in contact connection with the third electrode layer CM through the touch via holes.
Further, the first planarization layer OC has a thickness of 3 to 4 μm, and the second planarization layer OC2 has a thickness of 1 μm.
Further, the material of the gate insulating layer GI is one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.
Further, the VA layer is formed by adopting a silicon nitride material.
A preparation method of a TFT structure touch array substrate with low parasitic capacitance comprises the following steps:
step 1, preparing a precursor, wherein the precursor comprises a substrate, a grid electrode layer GE, a grid electrode insulating layer GI, an active layer SE, a barrier layer ES, an electrode layer SD and a passivation layer PV which are sequentially arranged;
step 2, manufacturing a first planarization layer OC on the precursor, and then developing to expose a pixel through hole of the first planarization layer OC;
step 3, sequentially arranging a VA layer, a second planarization layer OC2 and an insulating layer CH in the area of the first planarization layer OC corresponding to the two sides of the pixel through hole; developing the touch via exposing the second planarization layer OC 2;
step 4, manufacturing a pixel electrode PE in the pixel through hole, wherein the part of the pixel electrode PE passes through the pixel through hole to be lapped with the electrode layer SD,
step 5, forming a third electrode CM on the first planarization layer OC in the touch via hole,
step 7, digging a VA shallow hole on the VA layer to realize the inter-electrode lap joint, and arranging a common electrode COM on the bottom surface of the CH corresponding to the third electrode CM area; the common electrode COM is lapped with the third electrode CM through the touch via hole.
Further, the specific processes of the VA layer and the second planarization layer OC2 in step 3 are as follows:
step 3-1, carrying out physical vapor phase synthesis on SiNx to form a layer of VA film;
step 3-2, coating a layer of OC2 with the organic matter, wherein the film thickness is 1 um;
step 3-3, exposing for 2 times by using a VA/OC photomask, wherein the VA photomask has a second planarization layer OC2 on the VA layer, and the OC photomask has a first planarization layer OC under the VA layer;
step 3-4, baking the first planarization layer OC and the second planarization layer OC 2;
step 3-5, carrying out ion treatment on the first planarization layer OC and the second planarization layer OC2, and cleaning to prevent OC residues;
step 3-6, cleaning the first planarization layer OC and the second planarization layer OC 2;
step 3-7, performing photoresist coating, exposure and development on the VA layer;
step 3-8, dry etching the VA layer;
and 3-9, stripping the VA layer.
By adopting the technical scheme, the design of two OC film layers is adopted, the VA layer is respectively replaced by SiNx + OC, the distance between the TP Line and the COM is increased, the capacitance between the TP Line and the COM is reduced, and the design of low parasitic capacitance is obtained, so that the requirement of a lower parasitic capacitance of an active pen is met. The invention is suitable for binding In-cell (In cell), touch screen panel, active pen and the like. Under the structure of the active pen, the parasitic capacitance is lower due to the design of the two OC film layers, and the requirement of the specification of the active pen is met.
Drawings
The invention is described in further detail below with reference to the accompanying drawings and the detailed description;
fig. 1 is a schematic structural diagram of a TFT-structured touch array substrate in the prior art;
FIG. 2 is a schematic view of the manufacturing process of the VA (SiNx + OC) mask of the present invention;
fig. 3 is a schematic structural diagram of a TFT structure touch array substrate with low parasitic capacitance according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
As shown in fig. 2 or 3, the invention discloses a TFT structure touch array substrate with low parasitic capacitance, which includes a substrate, and a gate electrode layer GE, a gate insulating layer GI, an active layer SE, a blocking layer ES, an electrode layer SD, a passivation layer PV, a first planarization layer OC, a third electrode layer CM, a VA layer, a second planarization layer OC2, an insulating layer CH (contact hole), and a pixel electrode PE sequentially disposed on the substrate, wherein the pixel electrode PE covers a partial region of the insulating layer CH and is located above the partial electrode layer SD, and pixel via holes are correspondingly disposed in vertical directions of the passivation layer PV, the first planarization layer OC, the VA layer, the second planarization layer 2, and the insulating layer CH between the pixel electrode PE and the electrode layer SD, and the pixel electrode PE is disposed in the pixel via hole and is connected to the corresponding electrode layer SD region by the pixel via hole; the electrode layer SD part is in contact connection with the active layer SE through the barrier layer ES;
the third electrode layer CM is arranged in the region between the first planarization layer OC and the VA layer beside the pixel via hole; the bottom surface of the insulating layer CH is provided with a common electrode COM corresponding to the area of the third electrode layer CM, and the second planarization layer OC2 and the VA layer are provided with touch via holes corresponding to the middle area of the third electrode layer CM, so that part of the common electrode COM is in contact connection with the third electrode layer CM through the touch via holes.
Further, the first planarization layer OC has a thickness of 3 to 4 μm, and the second planarization layer OC2 has a thickness of 1 μm.
Further, the material of the gate insulating layer GI is one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.
Further, the VA layer is formed by adopting a silicon nitride material.
A preparation method of a pixel TFT structure with low parasitic capacitance comprises the following steps:
step 1, preparing a precursor, wherein the precursor comprises a substrate, a grid electrode layer GE, a grid electrode insulating layer GI, an active layer SE, a barrier layer ES, an electrode layer SD and a passivation layer PV which are sequentially arranged;
step 2, manufacturing a first planarization layer OC on the precursor, and then developing to expose a pixel through hole of the first planarization layer OC;
step 3, sequentially arranging a VA layer, a second planarization layer OC2 and an insulating layer CH in the area of the first planarization layer OC corresponding to the two sides of the pixel through hole; developing the touch via exposing the second planarization layer OC 2;
step 4, manufacturing a pixel electrode PE in the pixel through hole, wherein the part of the pixel electrode PE passes through the pixel through hole to be lapped with the electrode layer SD,
step 5, forming a third electrode CM on the first planarization layer OC in the touch via hole,
step 7, digging a VA shallow hole on the VA layer to realize the inter-electrode lap joint, and arranging a common electrode COM on the bottom surface of the CH corresponding to the third electrode CM area; the common electrode COM is lapped with the third electrode CM through the touch via hole.
Further, the specific processes of the VA layer and the second planarization layer OC2 in step 3 are as follows:
step 3-1, carrying out physical vapor phase synthesis on SiNx to form a layer of VA film;
step 3-2, coating a layer of OC2 with the organic matter, wherein the film thickness is 1 um;
step 3-3, exposing for 2 times by using a VA/OC photomask, wherein the VA photomask has a second planarization layer OC2 on the VA layer, and the OC photomask has a first planarization layer OC under the VA layer;
step 3-4, baking the first planarization layer OC and the second planarization layer OC 2;
step 3-5, carrying out ion treatment on the first planarization layer OC and the second planarization layer OC2, and cleaning to prevent OC residues;
step 3-6, cleaning the first planarization layer OC and the second planarization layer OC 2;
step 3-7, performing photoresist coating, exposure and development on the VA layer;
step 3-8, dry etching the VA layer;
and 3-9, stripping the VA layer.
Specifically, as shown in FIG. 2, the schematic process flow of the VA (SiNx + OC) mask in the embodiment of the present invention is shown, wherein PVD is physical vapor deposition; PHO, photoresist polishing, exposure and development; WET: wet etching; DRY: dry etching; STR: stripping the film; CVD, chemical vapor deposition; OVN: baking; DSC: carrying out ion treatment and cleaning; CLN: and (5) cleaning.
Because the active pen framework has lower capacitance requirements, VA (Via hole) can be modified into a SiNx + OC film layer from common SiNx (silicon nitride), the OC depth is deepened to 3-4 um (figure 3) from original 2um (figure 1), a VA insulating film layer can be replaced by SiNx + OC, namely after the common VA is formed by silicon nitride, a OC2 layer (organic layer) with larger thickness is formed by a photomask of the VA layer, the film thickness is 1um, the distance between TP Line (touch Line) and COM (common electrode) is increased, and the capacitance between TP Line and COM is reduced. The design of two OC film layers is adopted, and the requirement of the active pen on lower parasitic capacitance is met by reducing the capacitance between the TP Line and the COM.
By adopting the technical scheme, the design of two OC film layers is adopted, the VA layer is respectively replaced by SiNx + OC, the distance between the TP Line and the COM is increased, the capacitance between the TP Line and the COM is reduced, and the design of low parasitic capacitance is obtained, so that the requirement of a lower parasitic capacitance of an active pen is met. The invention is suitable for binding In-cell (In cell), touch screen panel, active pen and the like. Under the structure of the active pen, the parasitic capacitance is lower due to the design of the two OC film layers, and the requirement of the specification of the active pen is met.
It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The embodiments and features of the embodiments in the present application may be combined with each other without conflict. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Claims (6)
1. A TFT structure touch array substrate with low parasitic capacitance is characterized in that: the pixel electrode PE covers partial area of the insulating layer CH and is positioned above partial electrode layer SD, pixel through holes are correspondingly arranged in the vertical direction of the passivation layer PV, the first planarization layer OC, the VA layer, the second planarization layer OC2 and the insulating layer CH between the pixel electrode PE and the electrode layer SD, and the pixel electrode PE is arranged in the pixel through hole and is in contact connection with the corresponding electrode layer SD area through the pixel through hole; the electrode layer SD part is in contact connection with the active layer SE through the barrier layer ES;
the third electrode layer CM is arranged in the region between the first planarization layer OC and the VA layer beside the pixel via hole; the bottom surface of the insulating layer CH is provided with a common electrode COM corresponding to the area of the third electrode layer CM, and the second planarization layer OC2 and the VA layer are provided with touch via holes corresponding to the middle area of the third electrode layer CM, so that part of the common electrode COM is in contact connection with the third electrode layer CM through the touch via holes.
2. The touch array substrate with a low parasitic capacitance TFT structure of claim 1, wherein: the first planarization layer OC has a thickness of 3 to 4 μm, and the second planarization layer OC2 has a thickness of 1 μm.
3. The touch array substrate with a low parasitic capacitance TFT structure of claim 1, wherein: the gate insulating layer GI is made of one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.
4. The touch array substrate with a low parasitic capacitance TFT structure of claim 1, wherein: the VA layer is formed by adopting a silicon nitride material.
5. A method for preparing a TFT structure touch array substrate with low parasitic capacitance, which is used for preparing the TFT structure touch array substrate with low parasitic capacitance according to any one of claims 1 to 4, and is characterized in that: the method comprises the following steps:
step 1, preparing a precursor, wherein the precursor comprises a substrate, a grid electrode layer GE, a grid electrode insulating layer GI, an active layer SE, a barrier layer ES, an electrode layer SD and a passivation layer PV which are sequentially arranged;
step 2, manufacturing a first planarization layer OC on the precursor, and then developing to expose a pixel through hole of the first planarization layer OC;
step 3, sequentially arranging a VA layer, a second planarization layer OC2 and an insulating layer CH in the area of the first planarization layer OC corresponding to the two sides of the pixel through hole; developing the touch via exposing the second planarization layer OC 2;
step 4, manufacturing a pixel electrode PE in the pixel through hole, wherein the part of the pixel electrode PE passes through the pixel through hole to be lapped with the electrode layer SD,
step 5, forming a third electrode CM on the first planarization layer OC in the touch via hole,
step 7, digging a VA shallow hole on the VA layer to realize the inter-electrode lap joint, and arranging a common electrode COM on the bottom surface of the CH corresponding to the third electrode CM area; the common electrode COM is lapped with the third electrode CM through the touch via hole.
6. The method for manufacturing a TFT structure touch array substrate with low parasitic capacitance as claimed in claim 5, wherein: the specific processes of the VA layer and the second planarization layer OC2 in step 3 are as follows:
step 3-1, carrying out physical vapor phase synthesis on SiNx to form a layer of VA film;
step 3-2, coating a layer of OC2 with the organic matter, wherein the film thickness is 1 um;
step 3-3, exposing for 2 times by using a VA/OC photomask, wherein the VA photomask has a second planarization layer OC2 on the VA layer, and the OC photomask has a first planarization layer OC under the VA layer;
step 3-4, baking the first planarization layer OC and the second planarization layer OC 2;
step 3-5, carrying out ion treatment on the first planarization layer OC and the second planarization layer OC2, and cleaning to prevent OC residues;
step 3-6, cleaning the first planarization layer OC and the second planarization layer OC 2;
step 3-7, performing photoresist coating, exposure and development on the VA layer;
step 3-8, dry etching the VA layer;
and 3-9, stripping the VA layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114327143A (en) * | 2021-12-30 | 2022-04-12 | 福建华佳彩有限公司 | Method for improving dark spots of active pen technology |
| CN114995669A (en) * | 2022-05-24 | 2022-09-02 | 福建华佳彩有限公司 | Touch array substrate capable of avoiding active pen signal attenuation and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160291746A1 (en) * | 2015-03-31 | 2016-10-06 | Lg Display Co., Ltd. | Touch sensor integrated display device with multiple planarization layers |
| TWI623792B (en) * | 2017-08-07 | 2018-05-11 | 友達光電股份有限公司 | Display panel |
| CN110045852A (en) * | 2017-12-13 | 2019-07-23 | 乐金显示有限公司 | Display device and its manufacturing method with touch sensor |
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| US20160291746A1 (en) * | 2015-03-31 | 2016-10-06 | Lg Display Co., Ltd. | Touch sensor integrated display device with multiple planarization layers |
| TWI623792B (en) * | 2017-08-07 | 2018-05-11 | 友達光電股份有限公司 | Display panel |
| CN110045852A (en) * | 2017-12-13 | 2019-07-23 | 乐金显示有限公司 | Display device and its manufacturing method with touch sensor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114327143A (en) * | 2021-12-30 | 2022-04-12 | 福建华佳彩有限公司 | Method for improving dark spots of active pen technology |
| CN114995669A (en) * | 2022-05-24 | 2022-09-02 | 福建华佳彩有限公司 | Touch array substrate capable of avoiding active pen signal attenuation and preparation method thereof |
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