CN113594106A - Chip scale package - Google Patents
Chip scale package Download PDFInfo
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- CN113594106A CN113594106A CN202111143247.5A CN202111143247A CN113594106A CN 113594106 A CN113594106 A CN 113594106A CN 202111143247 A CN202111143247 A CN 202111143247A CN 113594106 A CN113594106 A CN 113594106A
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- metal layer
- scale package
- key notch
- chip scale
- chip
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- 239000002184 metal Substances 0.000 claims abstract description 92
- 229910052751 metal Inorganic materials 0.000 claims abstract description 92
- 239000005022 packaging material Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims description 23
- 230000003647 oxidation Effects 0.000 claims description 18
- 238000007254 oxidation reaction Methods 0.000 claims description 18
- 239000010949 copper Substances 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 238000005538 encapsulation Methods 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- HZEWFHLRYVTOIW-UHFFFAOYSA-N [Ti].[Ni] Chemical compound [Ti].[Ni] HZEWFHLRYVTOIW-UHFFFAOYSA-N 0.000 claims description 4
- MOFOBJHOKRNACT-UHFFFAOYSA-N nickel silver Chemical compound [Ni].[Ag] MOFOBJHOKRNACT-UHFFFAOYSA-N 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 description 28
- 238000000034 method Methods 0.000 description 19
- 239000000758 substrate Substances 0.000 description 12
- 238000002161 passivation Methods 0.000 description 9
- 238000000059 patterning Methods 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 239000008393 encapsulating agent Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 230000003064 anti-oxidating effect Effects 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application discloses wafer scale package includes: a chip has a front surface and a back surface, wherein the front surface has an active region. A metal layer formed on the back surface and larger than the projection of the active region, and suitable for a current to flow in the metal layer. The metal layer has four edges, wherein at least one edge has a key notch, and if the sinking direction of the key notch is parallel to the current direction, the key notch does not interfere with the projection of the active region. And the packaging material is formed on the back surface and at least covers the edge of the metal layer. The wafer size package can improve the connectivity of the metal layer and the packaging material, improve the reliability of the package, and avoid the generation of burrs.
Description
Technical Field
The present invention relates to a chip scale package, and more particularly, to a chip scale package capable of enhancing the mounting force of the packaging material.
Background
Today, the demand and trend for electronic products to be light and thin is continuously in response to the semiconductor package. Chip Scale Package (CSP) is a common type of semiconductor Package, and the volume of the overall Package is not more than 120% of the volume of the Chip. In the general chip scale package, the encapsulation material is used for encapsulating the chip at the wafer stage, and then the chip is cut. However, for some semiconductor devices, a large-area metal plating layer, such as a common-drain MOS (common-drain MOS), a chip with an anti-electrostatic discharge (ESD) protection circuit, a Transient Voltage Suppressor (TVS) chip, or a switching diode (switching diode) chip, is formed on the back surface of the chip. Poor adhesion of the encapsulating compound to the metal layer can cause subsequent package delamination (degradation) that can lead to moisture or particle penetration into the wafer and affect reliability. In addition, the large area of the metal layer may cause burrs during dicing of the wafer, which may affect the quality of the chip scale package.
Therefore, how to improve the above-mentioned problems and to provide a solution for a better quality chip scale package is an important need in this field.
Disclosure of Invention
In view of the above problems and the reasons to be solved, one aspect of the present invention is to provide a chip scale package, comprising: a chip having a front surface and a back surface, wherein the front surface has an active region; the metal layer is formed on the back surface, is larger than the projection of the active area, is suitable for a current to flow in the metal layer, and is provided with four edges, wherein at least one edge is provided with a key notch, and if the sinking direction of the key notch is parallel to the current direction, the key notch does not interfere with the projection of the active area; and a packaging material formed on the back surface and at least covering the edge of the metal layer.
Another aspect of the invention provides a chip scale package, comprising: a chip having a front surface and a back surface, wherein the front surface has an active region; the metal layer is formed on the back surface, is larger than the projection of the active area, is suitable for a current to flow in the metal layer, and is provided with four edges, wherein the edges are provided with a first key notch and a second key notch, the sinking direction of the first key notch is parallel to the current direction, the first key notch does not interfere with the projection of the active area, the sinking direction of the second key notch is vertical to the current direction, and the first key notch interferes with the projection of the active area; and the packaging material is formed on the back surface, at least covers the edge of the metal layer and is embedded into the first key notch and the second key notch.
According to an embodiment of the present invention, the passivation layer further includes an oxidation resistant layer formed on the surface of the metal layer.
According to another embodiment of the present invention, the encapsulation material further covers the surface of the metal layer.
According to a further embodiment of the invention, wherein the metal layer comprises copper.
According to another embodiment of the present invention, the oxidation resistant layer is selected from a group consisting of tin, titanium-nickel alloy, and silver-nickel alloy.
Drawings
In order to make the aforementioned and other objects, features, advantages and embodiments of the invention more comprehensible, the following description is given:
fig. 1 is a front view of a chip scale package according to an embodiment of the invention.
Fig. 2 is a back view of the chip scale package of fig. 1.
Fig. 3 is a schematic cross-sectional view illustrating a chip scale package process according to an embodiment of the invention.
Fig. 4 is a schematic cross-sectional view illustrating a chip scale package process according to an embodiment of the invention.
Fig. 5A is a schematic cross-sectional view illustrating a chip scale package process according to an embodiment of the invention.
Fig. 5B is a partial back view corresponding to fig. 5A.
Fig. 6 is a schematic cross-sectional view illustrating a chip scale package process according to an embodiment of the invention.
Fig. 7 is a schematic cross-sectional view illustrating a chip scale package process according to an embodiment of the invention.
Fig. 8 is a schematic cross-sectional view illustrating a chip scale package process according to another embodiment of the invention.
Fig. 9 is a schematic cross-sectional view illustrating a chip scale package process according to another embodiment of the invention.
Fig. 10 is a schematic cross-sectional view illustrating a chip scale package process according to another embodiment of the invention.
Reference numerals
10 chip scale package;
12 a source contact;
14 a gate contact;
16 a passivation layer;
18 in dashed lines;
19 an encapsulating material;
20 a semiconductor wafer;
22a semiconductor substrate;
22A front face;
22B back side;
24 pads;
26 a passivation layer;
28 a dividing line;
30 metal layers;
patterning the metal layer by 30A;
32 an encapsulating material;
40 patterning the packaging material;
patterning 42 the metal layer;
44 an oxidation resistant layer;
50 active regions;
52, a contour;
52A, a first key notch;
52B, a second key notch;
54 an encapsulation area;
d1, D2 concave depth;
d3 distance.
Detailed Description
For the purpose of facilitating an understanding of the embodiments, numerous technical details are provided below. Of course, these technical details are not required for all embodiments. Also, some well-known structures or elements are schematically depicted in the drawings only to simplify the drawing appropriately.
In order to make the description of the present disclosure more complete and complete, the following description is given for illustrative purposes with respect to the implementation aspects and specific embodiments of the present invention; it is not intended to be the only form in which the embodiments of the invention may be practiced or utilized. The embodiments are intended to cover the features of the various embodiments as well as the method steps and sequences for constructing and operating the embodiments. However, other embodiments may be utilized to achieve the same or equivalent functions and step sequences.
Referring to fig. 1 and 2, fig. 1 is a front view of a chip scale package according to an embodiment of the invention. Fig. 2 is a back view of the chip scale package of fig. 1. The chip scale package of the present invention is applied to a semiconductor device, and a large-area metal plating layer is formed on the back surface of the chip, such as a common-drain MOS (common-drain MOS), a chip with an anti-electrostatic discharge (ESD) protection circuit, a Transient Voltage Suppressor (TVS) chip, or a switching diode (switching diode) chip. As shown in fig. 1, the present embodiment is exemplified by a common-drain MOS device, in the chip scale package 10 of the present invention, a front view is shown, which is composed of two MOS devices, which are bounded by a middle dotted line 18 and are respectively a MOS device on the left and right, wherein each MOS device has four source contacts 12 and a gate contact 14, and the front surface of the chip scale package 10 is covered by a passivation layer 16, which only exposes the source contacts 12 and the gate contact 14. The passivation layer 16 includes, but is not limited to, polyimide (polyimide), and may be other commonly used semiconductor passivation layer materials.
The drains of the two MOS devices are formed on the semiconductor substrate, and a common drain (common drain) is formed by the doped region doped with P-type or N-type ions. In order to reduce the resistance of the common drain, a metal layer is formed on the back surface of the semiconductor substrate as the common drain. As shown in fig. 2, a package material 19 is coated on the metal layer (not shown) to protect the metal layer. The material of the encapsulating material 19 includes, but is not limited to, Epoxy resin (Epoxy).
Fig. 3 to 7 are schematic cross-sectional views illustrating a chip scale package process according to an embodiment of the invention. Referring to fig. 3, the packaging process of the present invention is performed on a semiconductor wafer 20 formed with devices (not shown), such as common-drain MOS (common-drain MOS), ESD (electrostatic discharge) chip, TVS (transient voltage suppressor) chip, or switching diode (switching diode) chip, in which the common-drain MOS device is taken as an example in the present embodiment, that is, the common-drain MOS device corresponds to fig. 1 and fig. 2. These elements are formed on the surface of the front surface 22A of the semiconductor substrate 22 by doping (doping), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), thermal Oxidation (Oxidation), photolithography (photolithography), etching (etching), etc., which are not described in detail herein. The semiconductor substrate 22 includes, but is not limited to, a silicon substrate, or a germanium substrate. Finally, bonding pads 24(bonding pads) of these devices are formed on the surface of the front surface 22A of the semiconductor substrate 22, and a passivation layer 26 is coated on the surface of the front surface 22A of the semiconductor substrate 22 to expose only a portion of the surface of the bonding pads 24 for external contact. The passivation layer 26 includes, but is not limited to, polyimide (polyimide), and may be other commonly used semiconductor passivation layer materials. The dividing line 28 of each die (die) of the semiconductor wafer 20 in fig. 3 is shown by a dotted line, and is also a cutting line for subsequent wafer dicing. Before the subsequent back side metallization, the back side 22B of the semiconductor substrate 22 is subjected to a grinding process (thinning), which thins to expose the contacts of the back side 22B of the semiconductor substrate 22, for example, a common drain mos device, i.e., a drain (doped region) is exposed.
Referring to fig. 4, a metal layer 30 is formed on the back surface 22B of the semiconductor substrate 22. The material of the metal layer 30 includes, but is not limited to, copper (Cu), and the manner of forming the metal layer 30 includes evaporation (evaporation) or sputtering (sputtering). In addition, after evaporation or sputtering, the metal layer 30 may be thickened by electroplating (plating) to reduce its resistance.
Referring to fig. 5A, a patterning process (patterning) is performed on the metal layer 30 to form a patterned metal layer 30A, wherein the patterning process includes photolithography and etching. Please also refer to fig. 5B, which is a partial back view corresponding to fig. 5A. A partial enlargement of one of the dies (die) of the semiconductor wafer 20 in fig. 5A is illustrated. It should be noted that fig. 5B is a back view, and the source contact 12 and the gate contact 14 (corresponding to the pad 24 in fig. 5A) are shown in dotted lines on the front surface 22A of the die. Meanwhile, an active region 50(active region) of the die front surface 22A is also shown by a dotted line, and the active region 50 is a region where devices are formed on the front surface 22A of the semiconductor wafer 20. And the encapsulation area 54, which represents the area of subsequently formed encapsulation material, has a periphery that corresponds to the boundary 28 of the die of fig. 5A. The outline 52 of the patterned metal layer 30A is mainly between the package region 54 and the active region 50, and the periphery of the package region 54 is the subsequent scribe line as described above, so the outline 52 of the patterned metal layer 30A is smaller than the package region 54 and is separated by a distance D3, thereby avoiding the dicing of the patterned metal layer 30A during the dicing of the semiconductor wafer 20 and avoiding the burr problem.
As shown in fig. 5B, the outline 52 of the patterned metal layer 30A includes four edges forming a substantially quadrilateral shape, wherein opposite sides of the outline 52 have a pair of first key notches 52a (first key notches), and the other opposite sides of the outline 52 have a pair of second key notches 52B (second key notches). It should be noted that in the present embodiment, the patterned metal layer 30A serves as a common drain, so that the current flowing in the patterned metal layer 30A is in the direction connecting the two gates 14, and in order to maintain low impedance, the recess depth D1 (the recess direction is parallel to the current direction) of the first key notch 52A does not exceed the active region 50, i.e. the projection of the first key notch 52A and the active region 50 does not interfere. On the other hand, the depression direction of the second key notch 52B is perpendicular to the current direction, and the depression depth D2 does not affect the impedance, so that the depression depth D2 may exceed the active region 50, i.e., the projection of the second key notch 52B and the active region 50 may interfere. It should be noted that the first key notch 52A or the second key notch 52B is designed to form a fitting structure between the patterned metal layer 30A and the package material, so as to provide better connectivity and avoid delamination. However, it should be understood by those skilled in the art that the key notches of the patterned metal layer 30A are not limited to the embodiment, and the key notches are disposed on at least one edge of the patterned metal layer 30A, so that the engaging structure can be formed to improve the connection between the patterned metal layer 30A and the package material. It should be noted that, according to an embodiment of the present invention, the key gap is configured as follows: if the sinking direction of the key notch is parallel to the current direction, the key notch does not interfere with the projection of the active area; on the other hand, if the depression direction of the key notch is perpendicular to the current direction, the key notch and the projection of the active region can generate interference.
Referring to fig. 6, an encapsulation material 32 is formed on the back surface 22B of the semiconductor wafer 20 to cover the patterned metal layer 30A, including the periphery and the surface of the patterned metal layer 30A. As mentioned above, due to the design of the first key notch 52A and the second key notch 52B of the patterned metal layer 30A, the package material 32 is embedded into the first key notch 52A and the second key notch 52B to form a fitting structure, thereby improving the connectivity between the patterned metal layer 30A and the package material 32. The material of the encapsulating material 32 includes Epoxy (Epoxy).
Referring to fig. 6 and 7, a wafer dicing process is performed to dice the semiconductor wafer 20 along the dividing lines 28 (dicing lines) of fig. 6, and the dies are separated to form the chip scale package shown in fig. 7. As described above, since the patterned metal layer 30A is kept at the distance D3 from the boundary line 28 (see fig. 5B), the patterned metal layer 30A is not cut during wafer dicing, and the problem of burrs can be avoided.
Next, referring to fig. 8 to 10, cross-sectional views of a chip scale package process according to another embodiment of the invention are shown. Referring to fig. 8, a patterned packaging material 40 is formed on the back surface 22B of the semiconductor wafer 20, and the method may include forming a whole layer of packaging material on the back surface 22B of the semiconductor wafer 20, and then forming the patterned packaging material 40 through photolithography and etching. Referring also to fig. 5B, the patterned encapsulant 40 is patterned as the area enclosed between the package region 54 and the outline 52 in fig. 5B, i.e., around the entire periphery of the die (around the subsequent patterned metal layer), i.e., around the four edges where the patterned metal layer is expected to be formed. At this time, the patterned encapsulant 40 forms a protrusion at the position corresponding to the first key notch 52A and the second key notch 52B, so as to be embedded with a patterned metal layer formed later. The dimensions D1 and D2 of the protrusion are similar to those of the first key notch 52A and the second key notch 52B, and are not repeated herein.
Referring to fig. 9, a metal layer electroplating process is performed to form a patterned metal layer 42, which is patterned as the patterned metal layer 30A shown in fig. 5B, due to the patterned packaging material 40. That is, the patterned metal layer 42 is also formed with the first key notch 52A and the second key notch 52B as shown in fig. 5B, and is embedded with the patterned encapsulant 40. The material of the patterned metal layer 42 includes, but is not limited to, copper. It should be noted that, according to an embodiment of the present invention, the metal layer electroplating process may form a seed metal layer (not shown) covering the entire back surface 22B of the semiconductor wafer 20 before the patterned packaging material 40 is formed, so as to serve as a current conducting layer during electroplating. The seed metal layer is made of copper and is formed by evaporation or sputtering. Then, the patterned packaging material 40 is formed on the seed metal layer, and the seed metal layer is electrified for metal plating, and at this time, only the surface of the seed metal layer which is not covered by the patterned packaging material 40 is plated, so as to form the patterned metal layer 42. If the patterned metal layer 42 is made of copper, since the patterned packaging material 40 does not cover the surface of the patterned metal layer 42 in the present embodiment, an anti-oxidation layer 44 is preferably formed on the surface of the patterned metal layer 42 to prevent oxidation of copper. The material of the oxidation resistant layer 44 includes, but is not limited to, tin, titanium-nickel alloy, and silver-nickel alloy, and the formation manner thereof includes electroplating. It should be understood by those skilled in the art that the oxidation resistant layer 44 is conformal to the patterned metal layer 42 due to the patterned packaging material 40, i.e. the oxidation resistant layer 44 has the same pattern as the patterned metal layer 42, and has the first key recesses 52A and the second key recesses 52B as shown in fig. 5B. In contrast to the embodiments of fig. 3-7, the patterned encapsulant 40 is formed first, and then the patterned metal layer 42 and the oxidation resistant layer 44 are formed, but the structure of the patterned metal layer 42 and the oxidation resistant layer 44 is the same as that of the patterned metal layer 30A. Similarly, it should be understood by those skilled in the art that the key notches of the patterned metal layer 42 and the oxidation resistant layer 44 are not limited to the embodiment, and a fitting structure can be formed by providing the key notches on at least one edge to improve the connection between the patterned metal layer 42 and the oxidation resistant layer 44 and the patterned packaging material 40, and the more the number of the key notches is, the better the connection between the patterned metal layer 42 and the oxidation resistant layer 44 and the patterned packaging material 40 should be. Similarly, according to an embodiment of the present invention, the key gap is configured by: if the sinking direction of the key notch is parallel to the current direction, the key notch does not interfere with the projection of the active area; on the other hand, if the depression direction of the key notch is perpendicular to the current direction, the key notch and the projection of the active region can generate interference.
Referring to fig. 9 and 10, a wafer dicing process is performed to dice the semiconductor wafer 20 along the dividing lines 28 (dicing lines) of fig. 9, and the dies are separated to form the chip scale package shown in fig. 10. As mentioned above, since the patterned metal layer 42 and the anti-oxidation layer 44 are kept at a distance D3 (see fig. 5B) from the boundary line 28, the patterned metal layer 42 and the anti-oxidation layer 44 are not cut during wafer dicing, thereby avoiding the problem of burrs.
In summary, the chip size package of the present invention is designed such that the metal layer on the back of the chip has the key notch and keeps a distance from the cut edge of the chip, thereby not only improving the connectivity between the metal layer and the package material and improving the reliability of the package, but also avoiding the generation of burrs.
The present invention is disclosed only by the preferred embodiments, however, it should be understood by those skilled in the art that the above embodiments are only for describing the present invention, and not for limiting the scope of the claims of the present invention. All changes and substitutions that are equivalent or equivalent to the above-described embodiments should be understood to be included within the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the following claims.
Claims (10)
1. A chip scale package, comprising:
a chip having a front surface and a back surface, wherein the front surface has an active region;
a metal layer formed on the back surface and larger than the projection of the active region, suitable for a current to flow in the metal layer, wherein the metal layer has four edges, at least one edge has a key notch, and if the recess direction of the key notch is parallel to the current direction, the key notch does not interfere with the projection of the active region; and
and the packaging material is formed on the back surface and at least covers the edges of the metal layer.
2. The chip scale package of claim 1, further comprising an oxidation resistant layer formed on the surface of the metal layer.
3. The chip scale package of claim 1, wherein the encapsulation material further covers a surface of the metal layer.
4. The wafer scale package of claim 1, wherein the metal layer comprises copper.
5. The chip scale package of claim 2, wherein the oxidation resistant layer is selected from the group consisting of tin, titanium-nickel alloy, and silver-nickel alloy.
6. A chip scale package, comprising:
a chip having a front surface and a back surface, wherein the front surface has an active region;
a metal layer formed on the back surface and larger than the projection of the active area, wherein the metal layer is suitable for a current to flow in the metal layer, the metal layer has four edges, the edges have a first key notch and a second key notch, the depression direction of the first key notch is parallel to the current direction, the first key notch does not interfere with the projection of the active area, the depression direction of the second key notch is perpendicular to the current direction, and the first key notch interferes with the projection of the active area; and
and the packaging material is formed on the back surface, at least covers the edges of the metal layer and is embedded into the first key notch and the second key notch.
7. The chip scale package of claim 6, further comprising an oxidation resistant layer formed on the surface of the metal layer.
8. The chip scale package of claim 6, wherein the encapsulation material further covers a surface of the metal layer.
9. The chip scale package of claim 6, wherein the metal layer comprises copper.
10. The chip scale package according to claim 7, wherein the oxidation resistant layer is selected from the group consisting of tin, titanium-nickel alloy, and silver-nickel alloy.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111143247.5A CN113594106B (en) | 2021-09-28 | 2021-09-28 | Chip scale package |
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|---|---|---|---|
| CN202111143247.5A CN113594106B (en) | 2021-09-28 | 2021-09-28 | Chip scale package |
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| CN113594106B CN113594106B (en) | 2021-12-17 |
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