CN113593463A

CN113593463A - Display mode switching system and method and display device

Info

Publication number: CN113593463A
Application number: CN202110874462.6A
Authority: CN
Inventors: 林准; 苏国火; 陈航宇; 张银龙; 刘冬; 陈芪飞; 刘建涛; 廖燕平
Original assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Priority date: 2021-07-30
Filing date: 2021-07-30
Publication date: 2021-11-02

Abstract

The invention provides a display mode switching system, a display mode switching method and a display device, and relates to the technical field of display. The system comprises a display processor and a time sequence controller; the display processor sends a switching trigger signal to the time sequence controller when obtaining a first instruction for switching a display mode; the switching of the display mode comprises the switching of refreshing frequency and the switching of resolution; the time sequence controller responds to the switching trigger signal and adjusts the time sequence of the clock signal so as to realize the switching of the display mode. In the embodiment of the invention, when the display processor obtains the first instruction, the switching trigger signal is sent to the time schedule controller, and the time schedule controller responds to the switching trigger signal and can realize the switching of the refreshing frequency and the resolution ratio by adjusting the time sequence of the clock signal.

Description

Display mode switching system and method and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display mode switching system, method and display device.

Background

A Timing Controller (TCON) in the display device may Control a gate driving circuit of the display panel by a clock signal to provide a turn-on Control signal to the pixels, and a source driving circuit of the display panel by a pixel driving signal to provide display data signals to the pixels.

At present, the timing controller is designed according to only one specific display mode, which has a specific refresh rate and a specific resolution, however, in practical applications, when the signal source is switched to a signal source with another refresh rate and/or another resolution, the timing controller is very likely to cause abnormal display of the image if the display control is performed based on the current display mode.

Disclosure of Invention

The invention provides a display mode switching system, a display mode switching method and a display device, which aim to solve the problem that the conventional time schedule controller cannot support various display modes, so that abnormal picture display is easy to occur after a signal source is switched.

In order to solve the above problems, the present invention discloses a display mode switching system, which is applied to a display device, the system comprises a display processor and a time schedule controller which are connected;

the display processor is configured to send a switching trigger signal to the timing controller when a first instruction for switching a display mode is obtained; the switching of the display modes comprises switching of refresh frequency and switching of resolution;

the time sequence controller is configured to respond to the switching trigger signal and adjust the time sequence of the clock signal so as to realize the switching of the display mode.

Optionally, a target line is arranged between the display processor and the time schedule controller;

the display processor is configured to send a switching trigger signal to the timing controller through the target line; the signal form of the switching trigger signal is related to the target line.

Optionally, the display processor includes a first display data signal interface, the timing controller includes a second display data signal interface, the first display data signal interface is connected to the second display data signal interface, a signal line between the first display data signal interface and the second display data signal interface includes an integrated circuit bus signal line, and the target line is the integrated circuit bus signal line;

the display processor is specifically configured to send a switching trigger signal to the timing controller through the integrated circuit bus signal line; the signal form of the switching trigger signal is an integrated circuit bus instruction signal.

Optionally, the display processor includes a first input/output port, the timing controller includes a second input/output port, and the target line is a connection line between the first input/output port and the second input/output port;

the display processor is specifically configured to send a switching trigger signal to the timing controller through the first input/output port; the signal form of the switching trigger signal is a level signal.

Optionally, the display processor includes a first display data signal interface, the timing controller includes a second display data signal interface, the first display data signal interface is connected to the second display data signal interface, a signal line between the first display data signal interface and the second display data signal interface includes a display data signal line, and the target line is the display data signal line;

the display processor is specifically configured to send a switching trigger signal to the timing controller through the display data signal line; the signal form of the switching trigger signal is a display data signal.

Optionally, the switching trigger signal is a target display data signal corresponding to a preset picture, where the preset picture includes at least one pattern area;

the time schedule controller is specifically configured to determine the size and the pixel arrangement mode of each pattern area according to the target display data signal; when the size and the pixel arrangement mode of each pattern area meet the first switching condition, switching from the current first display mode to a second display mode; when the size and the pixel arrangement mode of each pattern area meet second switching conditions, switching from the current second display mode to the first display mode;

the first switching condition includes: the size of each pattern area is larger than the corresponding first preset size, and the pixel arrangement mode of each pattern area is the corresponding first preset arrangement mode;

the second switching condition includes: when the size of each pattern area is larger than the corresponding second preset size, and the pixel arrangement mode of each pattern area is the corresponding second preset arrangement mode;

for the same pattern area, the first preset size and the second preset size corresponding to the pattern area are different; and/or the first preset arrangement mode and the second preset arrangement mode corresponding to the pattern area are different.

Optionally, the display device further comprises a display panel, and the display panel is connected with the timing controller;

the time sequence controller is also configured to output a display data signal corresponding to a preset aging mode picture to the display panel so as to enter an aging mode, and switch the display mode in the aging mode.

Optionally, the display processor is specifically configured to, when a first instruction for switching a display mode is obtained, send a second instruction for entering the aging mode to the timing controller through the integrated circuit bus signal line;

the timing controller is specifically configured to respond to the second instruction, output a display data signal corresponding to the aging mode picture to the display panel to enter the aging mode, and perform switching of the display mode in the aging mode.

Optionally, the display processor further includes a third input/output port, the timing controller further includes a fourth input/output port, and the third input/output port is connected to the fourth input/output port;

the display processor is specifically configured to send a second instruction for entering the burn-in mode to the timing controller through the third input/output port when a first instruction for switching a display mode is obtained;

Optionally, the timing controller is specifically configured to, when it is determined that the size and the pixel arrangement manner of each pattern region satisfy the first switching condition, output a display data signal corresponding to the burn-in mode picture to the display panel to enter the burn-in mode, and switch from the current first display mode to the second display mode in the burn-in mode;

and when the size and the pixel arrangement mode of each pattern area meet a second switching condition, outputting a display data signal corresponding to the aging mode picture to the display panel to enter the aging mode, and switching from the current second display mode to the first display mode in the aging mode.

Optionally, the display device further comprises a backlight module, and the backlight module is connected with the display processor;

the display processor is further configured to control the backlight module to be closed after a first instruction for switching a display mode is obtained;

the time sequence controller is also configured to switch the display mode under the condition that the backlight module is closed.

Optionally, the display processor is further configured to control the backlight module to be turned on when a turn-on condition of the backlight module is met;

wherein, the starting condition of the backlight module comprises: the display processor receives a third instruction which is sent by the time sequence controller after the switching of the display mode is completed and is used for starting the backlight module; or the preset duration is reached after the display processor closes the backlight module, and the preset duration is longer than the duration required by the time schedule controller for switching the display modes.

Optionally, the first instruction is specifically configured to switch from a first display mode to a second display mode, where a refresh frequency of the second display mode is higher than a refresh frequency of the first display mode, and a resolution of the second display mode is lower than a resolution of the first display mode; in the first display mode, the clock signals are sequentially driven;

at least two adjacent clock signals are divided into a clock signal group, the number of the clock signals included in each clock signal group is the same, and the clock signals included in each clock signal group are not repeated;

the display processor is further configured to send display data of a pixel row corresponding to a target clock signal to the timing controller after sending the switching trigger signal to the timing controller; the timing controller is specifically configured to respond to the switching trigger signal, adjust each clock signal in the clock signal group to be driven synchronously with a target clock signal, and output display data of a pixel row corresponding to the target clock signal; alternatively, the first and second electrodes may be,

the display processor is further configured to transmit display data of each pixel row to the timing controller after transmitting the switching trigger signal to the timing controller; the timing controller is specifically configured to respond to the switching trigger signal, adjust each clock signal in the clock signal group to be driven synchronously with a target clock signal, and output display data of a pixel row corresponding to the target clock signal;

wherein, in the same clock signal group, the target clock signal is any one of the clock signal groups.

Optionally, the first instruction is specifically configured to switch from a second display mode to a first display mode, where a refresh frequency of the second display mode is higher than a refresh frequency of the first display mode, and a resolution of the second display mode is lower than a resolution of the first display mode;

in the second display mode, each clock signal in the clock signal group is driven synchronously with a target clock signal; the target clock signal is any one of the clock signal groups;

the display processor is further configured to transmit display data of each pixel row to the timing controller after transmitting the switching trigger signal to the timing controller;

the timing controller is specifically configured to adjust the respective clock signals to be sequentially driven and output the display data of each pixel row in response to the switching trigger signal.

Optionally, the display processor comprises a system-on-chip.

In order to solve the above problem, the present invention also discloses a display mode switching method, which is applied to the above display mode switching system, and the method includes:

when the display processor obtains a first instruction for switching a display mode, sending a switching trigger signal to the time schedule controller; the switching of the display modes comprises switching of refresh frequency and switching of resolution;

and the time sequence controller responds to the switching trigger signal and adjusts the time sequence of the clock signal so as to realize the switching of the display mode.

In order to solve the above problem, the present invention further discloses a display device, including the above display mode switching system.

Optionally, the display device further includes a display panel and a backlight module, the display panel is connected to the timing controller in the display mode switching system, and the backlight module is connected to the display processor in the display mode switching system.

Compared with the prior art, the invention has the following advantages:

in the embodiment of the invention, when the display processor obtains the first instruction for switching the display mode, the display processor can send the switching trigger signal to the time schedule controller, and the time schedule controller responds to the switching trigger signal and can realize the switching of the refreshing frequency and the resolution ratio by adjusting the time sequence of the clock signal.

Drawings

Fig. 1 is a block diagram illustrating a display mode switching system according to a first embodiment of the present invention;

FIG. 2 is a timing diagram of clock signals in a first display mode according to a first embodiment of the present invention;

FIG. 3 is a timing diagram of clock signals in a second display mode according to a first embodiment of the present invention;

fig. 4 is a schematic diagram illustrating a display data signal interface of a display processor and a timing controller according to a first embodiment of the present invention;

FIG. 5 is a schematic diagram of an interface pin according to a first embodiment of the present invention;

fig. 6 is a schematic diagram illustrating an input/output port of a display processor and a timing controller according to a first embodiment of the present invention;

FIG. 7 is a diagram illustrating a default screen including a pattern area according to a first embodiment of the present invention;

FIG. 8 is a flowchart illustrating steps of a display mode switching method according to a second embodiment of the present invention;

fig. 9 is a block diagram showing a display device according to a third embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Example one

Referring to fig. 1, a block diagram of a display mode switching system according to a first embodiment of the present invention is shown, where the system 100 is applied to a display device, and the system 100 includes a display processor 110 and a timing controller 120 connected to each other.

A display processor 110 configured to transmit a switching trigger signal to the timing controller 120 when a first instruction for switching a display mode is obtained; the switching of the display mode comprises the switching of refreshing frequency and the switching of resolution;

and a timing controller 120 configured to adjust a timing of the clock signal in response to the switching trigger signal to enable switching of the display mode.

In a normal display process, the display data signal may be output to the display processor 110, the display processor 110 outputs the display data signal to the timing controller 120 after performing format conversion and the like, and the timing controller 120 may further output a clock signal and a display data signal to a connected display panel.

In an embodiment of the present invention, optionally, the display processor 110 includes a System On Chip (SOC).

In the embodiment of the invention, in the process of normal display of the display device, the switching function of the display mode can be triggered through the first instruction for switching the display mode.

In an alternative implementation manner, a user may trigger a switching function of the display mode through a key on a remote controller of the display device, a virtual touch key displayed on the display device, a physical key outside the display device, and the like, and when the relevant key is triggered, the display processor 110 may obtain a first instruction for switching the display mode.

In practical applications, a user may manually trigger the first instruction to match the switched display mode with the current signal source when the current display mode does not match the current signal source (for example, display insufficiency occurs, and a picture size is much smaller than a display area size). Or, the user may manually trigger the first instruction when the current display mode is matched with the current signal source, and correspondingly, the display processor 110 may switch the signal source when the timing controller 120 switches the display mode, so that the switched display mode is matched with the switched signal source.

In another alternative implementation, in the case that the signal source can be automatically switched, when the display processor 110 detects that the refresh frequency and/or resolution of the signal source changes, a first instruction for switching the display mode can be generated.

After the display processor 110 obtains the first instruction, it may send a switching trigger signal to the timing controller 120, and the timing controller 120 responds to the switching trigger signal, and may implement the switching of the refresh frequency by adjusting the timing sequence of the clock signal, and may implement the switching of the resolution by adjusting the output of the display data signal.

Alternatively, referring to fig. 1, a target line X is disposed between the display processor 110 and the timing controller 120;

a display processor 110 configured to transmit a switching trigger signal to the timing controller 120 through the target line X; the signal form of the switching trigger signal is related to the target line. That is, the target line determines the form in which the switching trigger signal is transmitted to the timing controller 120, and the processing of the timing controller 120 will be different depending on the signal form.

The manner in which the display processor 110 sends the switching trigger signal to the timing controller 120, and the specific form of the switching trigger signal will be described below.

1, optional implementation:

referring to fig. 4, optionally, the display processor 110 includes a first display data signal interface 1101, the timing controller 120 includes a second display data signal interface 1201, the first display data signal interface 1101 is connected to the second display data signal interface 1201, a signal line between the first display data signal interface 1101 and the second display data signal interface 1201 includes an Integrated Circuit bus (I2C) signal line 10A, and correspondingly, the target line X is the Integrated Circuit bus signal line 10A;

a display processor 110 specifically configured to transmit a switching trigger signal to the timing controller 120 through the integrated circuit bus signal line 10A; the signal form of the switching trigger signal is an integrated circuit bus instruction signal.

In practical applications, the first display data signal interface 1101 and the second display data signal interface 1201 can be, for example, V-By-One (VBO) interfaces. Referring to fig. 5, an interface connector of a V-By-One interface is shown, the V-By-One interface is generally provided with an I2C pin 02 in addition to a V-By-One pin 01, and an I2C channel can be established between a first display data signal interface 1101 and a second display data signal interface 1201 through the I2C pin 02.

In implementation 1, the switching trigger signal may specifically be an I2C signal, and the display processor 110 may send the switching trigger signal to the timing controller 120 through an I2C signal line. In this way, the display processor 110 can transmit the switching trigger signal to the timing controller 120 by using the I2C channel of the display data signal interface itself, without adding additional signal lines or interfaces.

Specifically, referring to fig. 5, the I2C pin 02 includes an SDA pin and an SCL pin, and correspondingly, the I2C signal line 10A includes an SDA signal line and an SCL signal line, where the SDA signal line is an I2C data signal line and the SCL signal line is an I2C clock signal line.

Alternative implementation of 2:

referring to fig. 6, optionally, the display processor 110 includes a first input/output (IO) port 1102, the timing controller 120 includes a second IO port 1202, and the target line X is a connection line between the first IO port 1102 and the second IO port 1202.

A display processor 110 specifically configured to send a switching trigger signal to the timing controller 120 through the first input/output port 1102; the signal form of the switching trigger signal is a level signal.

In practical applications, some spare IO ports are usually disposed between the display processor 110 and the timing controller 120. Correspondingly, in the implementation manner of fig. 2, the switching trigger signal may specifically be a level signal, and the first display mode may be switched to the second display mode through a high level indication, and the second display mode may be switched to the first display mode through a low level indication, or vice versa. In this way, the display processor 110 can transmit the switching trigger signal to the timing controller 120 by using the spare IO port without additionally adding a signal line or an interface.

Alternative implementation of 3:

referring to fig. 4, optionally, the display processor 110 includes a first display data signal interface 1101, the timing controller 120 includes a second display data signal interface 1201, the first display data signal interface 1101 is connected to the second display data signal interface 1201, a signal line between the first display data signal interface 1101 and the second display data signal interface 1201 includes a display data signal line 10B, and accordingly, the target line X is the display data signal line 10B.

A display processor 110 specifically configured to transmit a switching trigger signal to the timing controller 120 through the display data signal line 10B; the signal form of the switching trigger signal is a display data signal.

For example, the first display data signal interface 1101 and the second display data signal interface 1201 are both VBO (V-By-One) interfaces, the display data signal line 10B is a signal line between the above mentioned VBO pins 01, and a VBO channel can be established between the first display data signal interface 1101 and the second display data signal interface 1201 through the VBO pins 01.

In the implementation manner 3, the switching trigger signal may specifically be a VBO signal, and the display processor 110 may send the switching trigger signal to the timing controller 120 through a VBO signal line. In this way, the display processor 110 can transmit the switching trigger signal to the timing controller 120 by using the display data signal channel of the display data signal interface itself, without adding additional signal lines or interfaces.

Of course, in the embodiment of the present invention, the first display data signal interface 1101 and the second display data signal interface 1201 may also be other types of signal interfaces, which is not limited in the embodiment of the present invention.

Further, in the above-mentioned implementation manner 3, since the timing controller 120 has a function of detecting the display data signal, a special pattern in the frame can be identified (a pattern detect function, which may refer to related technologies specifically), and therefore, the trigger timing of the display mode switching can be determined by using the function of the timing controller 120. In the above-mentioned implementation manner 3, the switching trigger signal is in the form of a display data signal, that is, a specific picture can be displayed based on the switching trigger signal, when the timing controller 120 receives the switching trigger signal, the pattern detect function is triggered, some patterns in the picture corresponding to the switching trigger signal can be determined by detecting the switching trigger signal, and if some features in the patterns meet a preset condition, the display mode can be switched.

Correspondingly, the switching trigger signal may be a target display data signal corresponding to a preset frame, where the preset frame includes at least one pattern area;

a timing controller 120 specifically configured to determine a size and a pixel arrangement manner of each pattern region according to a target display data signal; when the size and the pixel arrangement mode of each pattern area meet the first switching condition, switching from the current first display mode to a second display mode; and when the size and the pixel arrangement mode of each pattern area meet the second switching condition, switching from the current second display mode to the first display mode.

The first switching condition includes: the size of each pattern area is larger than the corresponding first preset size, and the pixel arrangement mode of each pattern area is the corresponding first preset arrangement mode.

The second switching condition includes: when the size of each pattern area is larger than the second preset size corresponding to each pattern area, the pixel arrangement mode of each pattern area is the second preset arrangement mode corresponding to each pattern area.

In an alternative embodiment, the first predetermined size of each pattern area may be the same (hereinafter, this is taken as an example), and may be different. The second predetermined dimension of each pattern area may be the same (hereinafter, this is taken as an example), and may be different.

Taking the default frame shown in fig. 7 as an example, the default frame is default frame 1, pattern area 2, pattern area 3, and pattern area 4.

When the size (X1, Y1) of the pattern region 1, the size (X2, Y2) of the pattern region 2, the size (X3, Y3) of the pattern region 3, the size (X4, Y4) of the pattern region 4 are all larger than the first preset size (a1, B1), and the pixel arrangement manner of the pattern region 1 is a first preset arrangement manner corresponding to the pattern region 1 (for example, one horizontal row black and one horizontal row white are sequentially arranged), the pixel arrangement manner of the pattern region 2 is a first preset arrangement manner corresponding to the pattern region 2 (for example, one vertical row black and one vertical row white are sequentially arranged), the pixel arrangement manner of the pattern region 3 is a first preset arrangement manner corresponding to the pattern region 3 (for example, two horizontal rows white and two horizontal rows black are sequentially arranged), and the pixel arrangement manner of the pattern region 4 is a first preset arrangement manner corresponding to the pattern region 4 (for example, two vertical rows black and two vertical rows and white are sequentially arranged), it is determined that the sizes of the pattern regions 1-4 and the pixel arrangement manner satisfy a first switching condition, and the timing controller 120 may switch from the current first display mode to the second display mode.

When the size (X1, Y1) of the pattern region 1, the size (X2, Y2) of the pattern region 2, the size (X3, Y3) of the pattern region 3, the size (X4, Y4) of the pattern region 4 are all larger than the second preset size (a2, B2), the pixel arrangement manner of the pattern region 1 is a second preset arrangement manner corresponding to the pattern region 1 (for example, one vertical row black and one vertical row white are sequentially arranged), the pixel arrangement manner of the pattern region 2 is a second preset arrangement manner corresponding to the pattern region 2 (for example, one horizontal row black and one horizontal row white are sequentially arranged), the pixel arrangement manner of the pattern region 3 is a second preset arrangement manner corresponding to the pattern region 3 (for example, two vertical rows black and two vertical rows white are sequentially arranged), the pixel arrangement manner of the pattern region 4 is a second preset arrangement manner corresponding to the pattern region 4 (for example, two horizontal rows and two horizontal rows black and two horizontal rows are sequentially arranged), it is determined that the sizes of the pattern regions 1-4 and the pixel arrangement manner satisfy the second switching condition, and the timing controller 120 may switch from the current second display mode to the first display mode.

In specific application, the number of the pattern areas is too small or too large, the too small number can cause the increase of misjudgment, the too large number can cause the increase of detection amount, and the calculation efficiency is low.

In addition, in practical applications, image quality problems such as flicker and abnormal images may occur during the switching of the display modes, and in order to avoid the user from seeing the image quality problems during the switching process and improve the experience, the switching process of the display modes may be performed in an abnormal display mode (for example, an aging mode) having a specific image, or the display modes may be switched when the backlight module is turned off.

In an alternative embodiment:

optionally, the timing controller 120 is further configured to output a display data signal corresponding to a preset aging mode picture to enter an aging mode, and perform switching of the display mode in the aging mode.

In practical applications, the display device further includes a display panel, the display panel is connected to the output end of the timing controller 120, and the timing controller 120 can enter the aging mode by outputting the display data signal corresponding to the aging mode picture to the display panel, and perform switching of the display mode in the aging mode.

Corresponding to the above-described first alternative implementation (sending the switch trigger signal through the I2C channel), specifically optionally, the display processor 110 is specifically configured to send a second instruction for entering the burn-in mode to the timing controller 120 through the integrated circuit bus signal line 10A when a first instruction for switching the display mode is obtained.

The timing controller 120 is specifically configured to output a display data signal corresponding to the aging mode screen to the display panel in response to the second instruction to enter the aging mode, and perform switching of the display mode in the aging mode.

In this embodiment, the display processor 110 may send a second instruction for displaying an aging mode screen (screen may be customized, full black or a specific screen) to the timing controller 120 through the I2C channel.

Corresponding to the above-mentioned optional implementation manner of type 2 (sending the switching trigger signal through the IO port), specifically, optionally, referring to fig. 6, the display processor 110 further includes a third input/output port 1103, the timing controller 120 further includes a fourth input/output port 1203, and the third input/output port 1103 is connected to the fourth input/output port 1203;

a display processor 110 specifically configured to, when a first instruction for switching the display mode is obtained, send a second instruction for entering the aging mode to the timing controller 120 through the third input/output port 1103;

In this embodiment, the display processor 110 may transmit a second instruction for displaying the burn-in mode screen to the timing controller 120 through the IO port.

In the above two embodiments, the display processor 110 may first send the second instruction to the timing controller 120 to enable the timing controller 120 to enter the aging mode, and then send the switching trigger signal to the timing controller 120 to enable the timing controller 120 to switch the display mode, so as to ensure that the display mode enters the aging mode before being switched, and avoid the user seeing the image quality problem occurring in the switching process.

Corresponding to the above-mentioned 3 rd optional implementation manners (sending a switching trigger signal through a display data signal line), specifically, optionally, the timing controller 120 is specifically configured to, when it is determined that the size and the pixel arrangement manner of each pattern area satisfy the first switching condition, output a display data signal corresponding to an aging mode picture to the display panel to enter an aging mode, and switch from the current first display mode to the second display mode in the aging mode;

and when the size and the pixel arrangement mode of each pattern area meet the second switching condition, outputting a display data signal corresponding to the aging mode picture to the display panel to enter the aging mode, and switching from the current second display mode to the first display mode in the aging mode.

In the third embodiment, the display processor 110 may first send a switching trigger signal to the timing controller 120, then the timing controller 120 performs pattern region detection, and when it is determined that the characteristics of the pattern region satisfy the switching condition, the timing controller 120 enters the aging mode, and then performs display mode switching, thereby ensuring that the display mode enters the aging mode before switching, and avoiding the user seeing the image quality problem occurring in the switching process.

In the third embodiment, the switching trigger signal is transmitted in the form of the display data signal, and if the second command is also transmitted in the form of the display data signal through the same channel, the detection of the pattern area is affected, so that the timing controller 120 may enter the burn-in mode after the detection of the pattern area is completed, and further perform the switching of the display mode in the burn-in mode.

In the embodiment of the present invention, after the display mode is switched, the timing controller 120 may exit the aging mode.

In another alternative embodiment:

optionally, the display device further includes a backlight module, and the backlight module is connected to the display processor 110.

The display processor 110 is further configured to control the backlight module to be turned off after obtaining the first instruction for switching the display mode.

And the timing controller 120 is further configured to switch the display mode when the backlight module is turned off.

Corresponding to the above 1 st and 2 nd optional implementation manners, the display processor 110 may first control the backlight module to be turned off, and then send a switching trigger signal to the timing controller 120, so that the timing controller 120 switches the display modes, thereby ensuring that the backlight module is turned off before the display modes are switched, and avoiding the user from seeing the image quality problem occurring in the switching process.

Corresponding to the above-mentioned optional implementation manner of the third embodiment, the display processor 110 may first send a switching trigger signal to the timing controller 120, and at the same time, control the backlight module to be turned off, then the timing controller 120 performs the detection of the pattern region (the detection function may be implemented when the backlight module is turned off), and then performs the switching of the display mode when it is determined that the characteristics of the pattern region meet the switching condition, so as to ensure that the backlight module is turned off before the display mode is switched, and avoid the user from seeing the image quality problem occurring in the switching process.

Further optionally, the display processor 110 is further configured to control the backlight module to turn on when a turn-on condition of the backlight module is satisfied.

Wherein, backlight unit's opening condition includes: the display processor 110 receives a third instruction for turning on the backlight module, which is sent by the timing controller 120 after the switching of the display mode is completed; or, the preset duration is reached after the display processor 110 turns off the backlight module, and the preset duration is longer than the duration required by the timing controller 120 to perform the display mode switching.

Corresponding to the above 1 st and 2 nd optional implementation manners, the third instruction may be transmitted through a channel (I2C channel or IO port) for transmitting the switching trigger signal between the display processor 110 and the timing controller 120, after the switching of the display mode is completed, the timing controller 120 may send the third instruction for turning on the backlight module to the display processor 110, and then the display processor 110 may control the backlight module to be turned on.

Corresponding to the above-mentioned alternative implementation manner of 3, since the switching trigger signal does not occupy the I2C channel or the IO port, the timing controller 120 cannot control the display processor 110 to turn on the backlight module according to the instruction. In one embodiment, the display processor 110 may wait for a period of time after the backlight module is turned off, and reserve a certain time for the timing controller 120 to complete the switching, and the display processor 110 controls the backlight module to be turned on after the backlight module is turned off for a period of time.

The following specifically describes the switching manner from the first display mode (high resolution, low refresh rate) to the second display mode (low resolution, high refresh rate), and from the second display mode to the first display mode, respectively.

Firstly, the switching mode from the first display mode to the second display mode is as follows:

optionally, the first instruction is specifically configured to switch from the first display mode to a second display mode, where a refresh frequency (e.g., 120Hz) of the second display mode is higher than a refresh frequency (e.g., 60Hz) of the first display mode, and a resolution (e.g., horizontal resolution 8K × vertical resolution 2K, hereinafter referred to as 8K × 2K) of the second display mode is lower than a resolution (e.g., horizontal resolution 8K × vertical resolution 4K, hereinafter referred to as 8K × 4K) of the first display mode; in the first display mode, the respective clock signals are sequentially driven, as shown in fig. 2.

Referring to fig. 2, at least two adjacent clock signals are divided into one clock signal group, the number of clock signals included in each clock signal group is the same, and the clock signals included in each clock signal group are not repeated.

In one mode, the display processor 110 is further configured to send the display data of the pixel row corresponding to the target clock signal to the timing controller 120 after sending the switching trigger signal to the timing controller 120; the timing controller 120 is specifically configured to adjust each clock signal in the clock signal group to be driven in synchronization with the target clock signal (as shown in fig. 3) in response to the switching trigger signal, and output the display data of the pixel row corresponding to the target clock signal. Alternatively, the first and second electrodes may be,

in another mode, the display processor 110 is further configured to transmit the display data signal of each pixel row to the timing controller 120 after transmitting the switching trigger signal to the timing controller 120; and a timing controller, specifically configured to adjust each clock signal in the clock signal group to be driven in synchronization with the target clock signal (as shown in fig. 3) in response to the switching trigger signal, and output display data of the pixel row corresponding to the target clock signal.

In the same clock signal group, the target clock signal is any one of the clock signal groups.

Referring to fig. 3, in one specific embodiment, STV0 is a reset signal of the last GOA cell, and STV1 is a start input signal of the first GOA cell. In this embodiment, two adjacent clock signals may be divided into one clock signal group, one group of CLK1 and CLK2, one group of CLK3 and CLK4, one group of CLK5 and CLK6, one group of CLK7 and CLK8, one group of CLK9 and CLK10, and one group of CLK11 and CLK 12.

When the display mode needs to be switched, the display data of the even pixel lines may be discarded first, and the display data of the odd pixel lines may be retained (or vice versa), and then the timing controller 120 may adjust the second clock signal in the clock signal group to be driven in synchronization with the first clock signal in the clock signal group, i.e., CLK2 is adjusted to be driven in synchronization with CLK1, CLK4 is adjusted to be driven in synchronization with CLK3, CLK6 is adjusted to be driven in synchronization with CLK5, CLK8 is adjusted to be driven in synchronization with CLK7, CLK10 is adjusted to be driven in synchronization with CLK9, and CLK12 is adjusted to be driven in synchronization with CLK11 (or vice versa). Therefore, the two rows of grid lines can be simultaneously opened, the two rows of pixel lines can be simultaneously charged, the refreshing frequency of the picture can be adjusted to 120Hz from 60Hz, the resolution of the picture can be adjusted to 8 Kx 2K from 8 Kx 4K, and the switching from the first display mode to the second display mode is realized.

It should be noted that the step of discarding the display data of a part of the pixel rows (for example, the step of discarding the display data of the even pixel rows in the above example) may be executed by the display processor 110, or may be executed by the timing controller 120, which is not specifically limited in this embodiment of the invention.

Second, the switching mode from the second display mode to the first display mode:

optionally, the first instruction is specifically configured to switch from the second display mode to the first display mode, a refresh frequency (for example, 120Hz) of the second display mode is higher than a refresh frequency (for example, 60Hz) of the first display mode, and a resolution (for example, 8K × 2K) of the second display mode is lower than a resolution (for example, 8K × 4K) of the first display mode.

Referring to fig. 3, at least two adjacent clock signals are divided into one clock signal group, the number of clock signals included in each clock signal group is the same, and the clock signals included in each clock signal group are not repeated.

In the second display mode, each clock signal of the clock signal group is driven in synchronization with the target clock signal (as shown in fig. 3); the target clock signal is any one of the clock signal groups.

A display processor 110 further configured to transmit display data of each pixel row to the timing controller 120 after transmitting the switching trigger signal to the timing controller 120;

the timing controller 120 is specifically configured to adjust the respective clock signals to be sequentially driven in response to the switching trigger signal, as shown in fig. 2, and output (output to the display panel) the display data of each pixel row.

The second switching method and the first switching method are opposite processes. Referring to fig. 2, in one embodiment, the timing controller 120 may adjust CLK1-CLK12 to sequential driving in response to a switching trigger signal, and display data is not partially discarded. In this way, the refresh frequency of the picture can be adjusted from 120Hz to 60Hz, the resolution of the picture can be adjusted from 8K × 2K to 8K × 4K, and the switching from the first display mode to the first display mode is realized.

The following will provide 3 specific examples:

the first embodiment: the TCON (timing controller 120) receives an instruction (switching trigger signal) through an I2C channel of the VBO interface of the SOC (display processor 110), thereby controlling switching of the display mode.

Starting up an initial state: the power supply was defaulted to normal display mode (8K 4K60 Hz).

And (3) a display mode switching process: when the display mode needs to be switched, the SOC sends a Force imaging instruction (a second instruction) to the TCON and enters an imaging (aging) mode;

normal display mode → high brush display mode (8K × 2K120 Hz): in the aging mode, the SOC sends a high-brush GIP mode instruction (switching trigger signal) to the TCON through the I2C channel, and discards display data corresponding to even pixel rows, the VBO signal is switched from 8K × 4K60Hz to 8K × 2K120Hz, and when the TCON receives the high-brush GIP mode instruction, the display mode is switched from the normal display mode to the high-brush display mode (fig. 2 is changed to fig. 3);

high-brush display mode → normal display mode: in the aging mode, the SOC sends a normal GIP mode instruction (switching trigger signal) through the I2C channel, and retains display data corresponding to even pixel rows, the VBO signal is switched from 8K × 2K120Hz to 8K × 4K60Hz, and when the TCON receives the normal GIP mode instruction, the display mode is switched from the high-brush display mode to the normal display mode (fig. 3 is changed to fig. 2).

The SOC sends an Exit-logging instruction to the TCON through the I2C channel, and the TCON exits the logging mode.

Shutdown state: the display device can be normally powered off in any display mode, and is still in a normal display mode after being powered on.

The I2C communication instructions for SOC are as follows (see HX8898ATCON IC for example) in Table 1 below.

TABLE 1

Second embodiment: the TCON sets the respective IO1 and IO2 ports for receiving the Level signal (H/L Level) provided by the SOC, thereby controlling the switching of the display mode.

The voltage range of the high level is set to be 2.7-3.3V, and the voltage range of the low level is set to be 0-0.6V.

IO1 is used to control normal display mode/imaging mode, high level: aging mode, low level: normal display mode.

IO2 is used to control display mode switching, H: normal display mode → high brush display mode, L: high-brush display mode → normal display mode.

Starting up an initial mode: IO1 is low level, IO2 does not make level judgment, and the default is normal display mode.

And (3) a display mode switching process: the IO1 is set to be from low level → high level, the SOC controls the TCON to enter the imaging mode, and the TCON starts to detect the state of the IO 2;

normal display mode → high-brush display mode: in the aging mode, the SOC inputs high level to the TCON IO2, display data corresponding to even pixel rows are abandoned, a VBO signal is switched from 8 Kx 4K60Hz to 8 Kx 2K120Hz, and the TCON switches the display mode from the normal display mode to the high-brushing display mode;

high-brush display mode → normal display mode: in the aging mode, the SOC inputs a low level to the TCON IO2, retains display data corresponding to even pixel rows, switches the VBO signal from 8K × 2K120Hz to 8K × 4K60Hz, and switches the display mode from the high-brush display mode to the normal display mode.

And (3) completing the display mode switching: the SOC completes the VBO signal switching, the IO1 goes from high → low, and the TCON exits the aging mode.

The IO port level signals are as follows in table 2.

TABLE 2

It should be noted that in the initial power-on mode, IO2 may be set to high level in advance, but in the power-on mode, TCON does not determine the state of IO 2.

In addition, after entering the aging mode, the TCON may start detecting the state of the IO2 again after delaying the display time of at least 1 frame of picture.

The third embodiment: by using the pattern detect function of the TCON, after the TCON detects the special pattern sent by the SOC, the TCON switches the display mode.

Starting up an initial mode: the power-up defaults to the normal display mode.

And (3) a display mode switching process: when the display mode needs to be switched, the SOC sends a specific pattern, the TCON triggers a pattern detect function, meanwhile, the SOC controls the backlight module to be closed, and after the SOC sends the specific pattern and delays for 500ms, the backlight module is controlled to be opened again. Wherein 500ms is a theoretical value, and different display devices can be set according to the actual SOC and the display mode switching time of TCON.

normal display mode → high-brush display mode: and when the TCON detects Pattern, entering an imaging mode, discarding display data corresponding to even pixel rows by the SOC, switching the VBO signal from 8 Kx 4K60Hz to 8 Kx 2K120Hz, and switching the display mode from a normal display mode to a high-brush display mode by the TCON.

High-brush display mode → normal display mode: and when the TCON detects Pattern B, entering an imaging mode, entering the imaging mode, keeping the display data corresponding to the even pixel rows by the SOC, switching the VBO signal from 8 Kx 2K120Hz to 8 Kx 4K60Hz, and switching the display mode from the high-brushing display mode to the normal display mode by the TCON.

In the embodiment of the invention, when the display processor obtains the first instruction for switching the display mode, the display processor can send a switching trigger signal to the time schedule controller, the time schedule controller responds to the switching trigger signal, the switching of the refresh frequency can be realized by adjusting the time sequence of the clock signal, and the switching of the resolution can be realized by adjusting the output of the display data signal, so that the switching of the display mode can be realized, the display mode is matched with the refresh frequency and the resolution corresponding to the current signal source, and the abnormal display of the picture is avoided.

Example two

Fig. 8 is a flowchart illustrating steps of a display mode switching method according to a second embodiment of the present invention, where the method is applied to the display mode switching system, and the method includes the following steps:

step 801: when the display processor obtains a first instruction for switching a display mode, sending a switching trigger signal to the time schedule controller; the switching of the display modes includes switching of refresh frequency and switching of resolution.

Step 802: and the time sequence controller responds to the switching trigger signal and adjusts the time sequence of the clock signal so as to realize the switching of the display mode.

the sending of the switching trigger signal to the timing controller includes:

the display processor sends a switching trigger signal to the time sequence controller through the target line; the signal form of the switching trigger signal is related to the target line.

the sending of the switching trigger signal to the timing controller includes: the display processor sends a switching trigger signal to the time schedule controller through the integrated circuit bus signal line; the signal form of the switching trigger signal is an integrated circuit bus instruction signal.

the sending of the switching trigger signal to the timing controller includes: the display processor sends a switching trigger signal to the time schedule controller through the first input/output port; the signal form of the switching trigger signal is a level signal.

the sending of the switching trigger signal to the timing controller includes: the display processor sends a switching trigger signal to the time schedule controller through the display data signal wire; the signal form of the switching trigger signal is a display data signal.

the step 802 includes: the time schedule controller determines the size and the pixel arrangement mode of each pattern area according to the target display data signal; when the size and the pixel arrangement mode of each pattern area meet the first switching condition, switching from the current first display mode to a second display mode; when the size and the pixel arrangement mode of each pattern area meet second switching conditions, switching from the current second display mode to the first display mode;

Optionally, the method further comprises: the time sequence controller outputs a display data signal corresponding to a preset aging mode picture so as to enter an aging mode, and the display mode is switched in the aging mode.

Optionally, the timing controller outputs a display data signal corresponding to a preset aging mode picture to the display panel to enter an aging mode, and before the display mode is switched in the aging mode, the method further includes: when the display processor obtains a first instruction for switching a display mode, sending a second instruction for entering the aging mode to the time schedule controller through the integrated circuit bus signal line;

the time schedule controller outputs a display data signal corresponding to a preset aging mode picture to the display panel to enter an aging mode, and switches the display mode in the aging mode, and the time schedule controller comprises: and the time sequence controller responds to the second instruction, outputs a display data signal corresponding to the aging mode picture to the display panel so as to enter the aging mode, and switches the display mode in the aging mode.

the time schedule controller outputs a display data signal corresponding to a preset aging mode picture to the display panel to enter an aging mode, and before switching the display mode in the aging mode, the method further comprises the following steps: when the display processor obtains a first instruction for switching a display mode, a second instruction for entering the aging mode is sent to the time schedule controller through the third input/output port;

Optionally, the outputting, by the timing controller, a display data signal corresponding to a preset aging mode picture to the display panel to enter an aging mode, and switching the display mode in the aging mode includes: when the time schedule controller determines that the size and the pixel arrangement mode of each pattern area meet the first switching condition, the time schedule controller outputs display data signals corresponding to the aging mode pictures to the display panel so as to enter the aging mode, and switches from the current first display mode to the second display mode in the aging mode;

the method further comprises the following steps: the display processor controls the backlight module to be closed after obtaining a first instruction for switching a display mode;

and the time sequence controller switches the display mode under the condition that the backlight module is closed.

Optionally, the method further comprises: when the display processor meets the starting condition of the backlight module, the display processor controls the backlight module to be started;

the method further comprises the following steps: after the display processor sends the switching trigger signal to the time schedule controller, sending display data of a pixel row corresponding to a target clock signal to the time schedule controller; the time schedule controller responds to the switching trigger signal, adjusts each clock signal in the clock signal group to be driven synchronously with a target clock signal, and outputs display data of a pixel row corresponding to the target clock signal; alternatively, the first and second electrodes may be,

the method further comprises the following steps: the display processor sends the display data of each pixel row to the time sequence controller after sending the switching trigger signal to the time sequence controller; the time schedule controller responds to the switching trigger signal, adjusts each clock signal in the clock signal group to be driven synchronously with a target clock signal, and outputs display data of a pixel row corresponding to the target clock signal;

the method further comprises the following steps: the display processor sends the display data of each pixel row to the time sequence controller after sending the switching trigger signal to the time sequence controller;

the timing controller adjusts the respective clock signals to be sequentially driven in response to the switching trigger signal, and outputs display data of each pixel row.

It should be noted that, for specific implementation manners of each step in this embodiment, reference may be made to relevant contents in the first embodiment, and details of this embodiment are not described herein again.

EXAMPLE III

The embodiment of the invention also discloses a display device which comprises the display mode switching system.

Fig. 9 shows a block diagram of a display device according to a third embodiment of the present invention, where the display device 1000 further includes a display panel 130 and a backlight module 140, the display panel 130 is connected to the timing controller 120 in the display mode switching system 100, and the backlight module 140 is connected to the display processor 110 in the display mode switching system 100.

While, for purposes of simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present invention is not limited by the illustrated ordering of acts, as some steps may occur in other orders or concurrently with other steps in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The display mode switching system, method and display device provided by the present invention are introduced in detail, and the principle and the implementation manner of the present invention are explained in the present document by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A display mode switching system is characterized by being applied to a display device and comprising a display processor and a time schedule controller which are connected;

2. The system of claim 1, wherein a target line is disposed between the display processor and the timing controller;

3. The system of claim 2, wherein the display processor comprises a first display data signal interface, the timing controller comprises a second display data signal interface, the first display data signal interface is connected to the second display data signal interface, the signal lines between the first display data signal interface and the second display data signal interface comprise integrated circuit bus signal lines, and the target lines are the integrated circuit bus signal lines;

4. The system of claim 2, wherein the display processor comprises a first input output port, the timing controller comprises a second input output port, and the target line is a connection line between the first input output port and the second input output port;

5. The system of claim 2, wherein the display processor comprises a first display data signal interface, the timing controller comprises a second display data signal interface, the first display data signal interface is connected with the second display data signal interface, the signal line between the first display data signal interface and the second display data signal interface comprises a display data signal line, and the target line is the display data signal line;

6. The system according to claim 5, wherein the switching trigger signal is a target display data signal corresponding to a predetermined frame, the predetermined frame including at least one pattern area;

7. The system according to any one of claims 1 to 6, wherein the timing controller is further configured to output a display data signal corresponding to a preset burn-in mode screen to enter a burn-in mode, and perform switching of the display mode in the burn-in mode.

8. The system of claim 7, wherein the display processor is specifically configured to send a second instruction to enter the burn-in mode to the timing controller via the integrated circuit bus signal line when the first instruction to switch the display mode is obtained;

9. The system of claim 7, wherein the display processor further comprises a third input-output port, wherein the timing controller further comprises a fourth input-output port, and wherein the third input-output port is coupled to the fourth input-output port;

10. The system according to claim 7, wherein the timing controller is specifically configured to output a display data signal corresponding to the burn-in mode picture to the display panel to enter the burn-in mode when it is determined that the size and the pixel arrangement of each of the pattern areas satisfy the first switching condition, and to switch from the current first display mode to the second display mode in the burn-in mode;

11. The system of claim 1, wherein the display device further comprises a backlight module, the backlight module being coupled to the display processor;

12. The system of claim 11, wherein the display processor is further configured to control the backlight module to turn on when a turn-on condition of the backlight module is satisfied;

13. The system of claim 1, wherein the first instructions are specifically configured to switch from a first display mode to a second display mode, wherein the second display mode has a higher refresh rate than the first display mode, and wherein the second display mode has a lower resolution than the first display mode; in the first display mode, the clock signals are sequentially driven;

14. The system of claim 1, wherein the first instructions are specifically configured to switch from a second display mode to a first display mode, wherein a refresh rate of the second display mode is higher than a refresh rate of the first display mode, and wherein a resolution of the second display mode is lower than a resolution of the first display mode;

15. The system of claim 1, wherein the display processor comprises a system-on-chip.

16. A display mode switching method applied to the display mode switching system according to any one of claims 1 to 15, the method comprising:

17. A display device characterized by comprising the display mode switching system according to any one of claims 1 to 15.

18. The display device according to claim 17, further comprising a display panel and a backlight module, wherein the display panel is connected to the timing controller of the display mode switching system, and the backlight module is connected to the display processor of the display mode switching system.