CN113574641A - Multi-chip package with high thermal conductivity die attach - Google Patents

Multi-chip package with high thermal conductivity die attach Download PDF

Info

Publication number
CN113574641A
CN113574641A CN202080021334.0A CN202080021334A CN113574641A CN 113574641 A CN113574641 A CN 113574641A CN 202080021334 A CN202080021334 A CN 202080021334A CN 113574641 A CN113574641 A CN 113574641A
Authority
CN
China
Prior art keywords
metal
layer
die
aperture
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202080021334.0A
Other languages
Chinese (zh)
Inventor
N·达沃德
S·科杜里
B·S·库克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN113574641A publication Critical patent/CN113574641A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2746—Plating
    • H01L2224/27462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48101—Connecting bonding areas at the same height, e.g. horizontal bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H01L2224/49176—Wire connectors having the same loop shape and height
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/2064—Length ranges larger or equal to 1 micron less than 100 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/20641—Length ranges larger or equal to 100 microns less than 200 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/20642—Length ranges larger or equal to 200 microns less than 300 microns

Abstract

A packaged semiconductor device (200) includes a metal substrate (120) having first and second via apertures (120a, 120b), and a metal pad (125b) surrounding the apertures on the dielectric pad (125a), the via apertures (120a, 120b) having an outer ring. The first and second semiconductor dies (180a, 180b) have a Back Side Metal (BSM) layer (186) on their bottom surfaces, the top surfaces being mounted upwardly on top portions of the apertures. A metal die attach layer (187) is located directly between the BSM layer and walls of the metal substrate that define the aperture to provide die attachment for the first and second semiconductor dies that fill a bottom portion of the aperture. A lead (126) contacts the metal pad, wherein the lead includes a distal portion that extends beyond the metal substrate. Bonding wires (133) are located between the metal pads and the bonding pads on the first and second semiconductor dies, and the molding compound provides packaging for the packaged semiconductor device.

Description

Multi-chip package with high thermal conductivity die attach
Technical Field
The present disclosure relates to semiconductor device assembly, and more particularly to metal die attachment to a substrate.
Background
Packaged semiconductor devices typically include an Integrated Circuit (IC) die, which is typically a silicon die mounted on a die pad of a workpiece, such as a lead frame, using a die attach adhesive. Other workpieces include an interposer, a Printed Circuit Board (PCB), and another IC die. For IC dies that are assembled with the top (active) side up and the back side down, the die attach adhesive provides mechanical attachment and typically also provides electrical and/or thermal access to the die pads. Die attach adhesives typically include polymers such as polyimides or epoxy-based adhesives. Silver is often added as a filler in the form of particulate flakes to improve both the electrical and thermal conductivity of the polymeric material.
Disclosure of Invention
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description, including the drawings that are provided. This summary is not intended to limit the scope of the claimed subject matter.
The disclosed aspects recognize that conventional die attach solutions including metal particle filled polymers have significant thermal and electrical resistance. As thermal management becomes increasingly important as more compact and higher integration electronic systems trend to have smaller features and to operate at higher operating currents, higher thermal conductivity die attach arrangements are required which also provide low electrical resistance when electrical contact to the back side of the semiconductor die is used. It is well known that although solder die attach, such as eutectic gold and tin (AuSn), may provide electrical contact to the back side of a semiconductor die with relatively good thermal and resistive properties compared to metal particle filled polymers, solder die attach is relatively expensive and limited to solderable die surfaces. In addition, the solder die attach process involves an inert reflow process, the temperature of which may create temperature-induced stress on the metal interconnects of the semiconductor die.
Disclosed aspects include a packaged semiconductor device including a metal substrate having first and second via apertures, each having an outer ring, and a metal pad surrounding the aperture on a dielectric pad on the metal substrate. The first and second semiconductor dies are mounted atop face up on the top portion of the aperture with a Back Side Metal (BSM) layer on a bottom surface thereof. A metal die attach layer is located between the BSM layer and walls of the metal substrate that define an aperture to provide die attachment for the first and second semiconductor dies that fill a bottom portion of the aperture. A lead contacts the metal pad, wherein the lead includes a distal portion that extends beyond the metal substrate. The bonding wires are located between the metal pads and the bonding pads on the first and second semiconductor dies, and the molding compound provides a device package for the packaged semiconductor device.
Drawings
Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:
fig. 1A-1F illustrate components used and assembly process progression of an assembly process for forming the disclosed multi-chip package semiconductor device having first and second semiconductor dies on a metal substrate having raised metal pads including metal pads on dielectric pads on a surface of the metal substrate, wherein each semiconductor die having a BSM layer is directly attached to the metal substrate by the disclosed electroplated (plated) metal die attachment layer, according to example aspects.
Fig. 2A shows an exemplary leaded multi-chip semiconductor device having first and second semiconductor dies on a metallic substrate, after dicing (singulation) and then wire bonding the bond pads on the respective semiconductor dies to raised metal pads connected to the leads, and wire bonding the bond pads between the respective semiconductor dies.
Fig. 2B illustrates the leaded multi-chip package semiconductor device shown in fig. 2A after molding to form a molding compound to provide a molded leaded multi-chip package semiconductor device.
Detailed Description
Example aspects are described with reference to the drawings, wherein like reference numerals are used to refer to like or equivalent elements. The illustrated ordering of acts or events should not be construed as limiting, as some acts or events may occur in different orders and/or concurrently with other acts or events. Moreover, some illustrated acts or events may not be required to implement a methodology in accordance with the present disclosure.
The disclosed aspects include a multi-chip semiconductor package in which die attachment of first and at least second semiconductor die is established by a plated metal layer, such as comprising copper, nickel, cobalt, or alloys thereof, as opposed to conventional soldering. Thus, the voiding problem of the solder die attach process associated with Sn-Cu intermetallic formation is eliminated in the disclosed multi-chip package.
Fig. 1A shows an example dielectric cap 130 for capping a metal substrate (see metal substrate 120 in fig. 1B) to form a capped substrate stack, wherein the dielectric cap 130 has a repeating pattern, each pattern comprising a pair of grooves 130a, 130B, the pair of grooves comprising a first groove 130a and a second groove 130B. The covered substrate stack is configured for immersion in a plating vessel providing an electroplating bath, shown at 150, described below with respect to fig. 1E.
The dielectric cover 130 may comprise plastic. The first recess 130a is for covering a first semiconductor die and the second recess 130b is for covering a second semiconductor die, each of which is shown, for example, as a rectangle shaped and sized to match the size of the respective semiconductor die to be covered. The recesses 130a, 130b are slightly larger in area than the first and second semiconductor dies to be able to accommodate the respective semiconductor dies. Although shown as being the same size and shape, the first and second recesses 130a and 130b may be sized and shaped differently relative to one another to match the respective sizes of the first and second semiconductor dies.
Alternatively, a UV curable plating solution resistant tape may be used as the dielectric cover 130. In the case of an adhesive tape instead of a dielectric cover, no grooves would be required. A dielectric cap on the top surfaces of the first and second semiconductor die prevents the die from falling out of the plating solution.
Fig. 1B shows an example metal substrate 120 with an inset enlarged to show corresponding components of bump pads 125, each component including a metal pad 125B on a dielectric pad 125a (e.g., polyimide) on the surface of metal substrate 120. The metal substrate 120 is typically in the form of a substrate sheet/panel having a plurality of dual die-site via apertures, including a first aperture 120a and a second aperture 120b configured for use with the first and second semiconductor dies 180a, 180b shown in fig. 1C, the first and second semiconductor dies 180a, 180b being positioned with top surfaces facing upward within the apertures 120a, 120 b. The metal substrate sheet/panel may have about 50 to 1,000 dual die sites. The thickness of the metal substrate 120 is typically about 0.1mm (3.94 mils) to 0.3mm (11.81 mils).
The metal substrate 120 may include copper, such as a copper alloy. Other example metals for the metal substrate 120 may also include nickel, cobalt, tin, or alloys thereof. The first and second apertures 120a, 120b are in a repeating pattern whose location matches the size(s) and repeating pattern of the pair of grooves 130a, 130b of the dielectric lid 130 shown in fig. 1A. Apertures 120a and 120b each have an outer ring 120a1 and 120b1 for seating the first and second semiconductor die, with bump pads 125 on the sides generally surrounding the via apertures 120a and 120 b. The metal pad 125b may be printed on the dielectric pad 125 a. The printing is typically registered by alignment marks on the metal substrate 120.
Fig. 1C shows first and second semiconductor dies 180a and 180B seated with their top (active) facing up and their back facing down on outer rings 120a1 and 120B1 (shown in fig. 1B) within apertures 120a and 120B of metal substrate 120. Bond pads 181 coupled to nodes in circuits 170a, 170b are shown on the active top surfaces of semiconductor dies 180a and 180 b. Circuits 170a, 170b include circuit elements (including transistors, and typically diodes, resistors, capacitors, etc.) formed in a semiconductor layer (an epitaxial layer on a bulk substrate) that are configured together to typically implement at least circuit functionality. Example circuit functions include analog (e.g., amplifier or power converter), Radio Frequency (RF), digital, or non-volatile memory functions.
The first and second semiconductor dies 180a and 180b have a BSM layer 186, for example comprising copper. Although not shown, there may be an optional refractory metal barrier layer (e.g., TiW, TaN or Cr) below the BSM layer 186. The bond pad 181 may include a copper pillar or solder bump thereon.
Fig. 1D shows the dielectric cap 130 after placement on the metal substrate 120 over the semiconductor dies 180a, 180b, with the view reversed to look down at the bottom of the metal substrate 120, showing the portions of the apertures 120a and 120b not occupied by the semiconductor dies 180a, 180 b. A BSM layer 186 is shown on the backside of the semiconductor dies 180a, 180 b.
Fig. 1E illustrates immersing the disclosed covered substrate stack including the dielectric cover 130 on the metal substrate 120 having the first and second semiconductor die (not shown) therein, within a plating vessel 150 that provides an electroplating bath. The components are immersed in a plating solution 145, the plating solution 145 including an electrolyte containing one or more dissolved metal salts including the metal of interest for electroplating, as well as other ions in the solution that allow current to flow.
In the case of a dielectric cover, an encapsulant, such as an electroplating solution resistant tape, is also typically present between the dielectric cover 130 and the metal substrate 120 to avoid plating the plated metal die attach layer on the top surface of the semiconductor die 180a, 180 b. For electroplating, the metal substrate 120 is connected to the negative terminal (cathode) of the power supply 190, and a conductive structure spaced apart from the metal substrate 120, such as a metal block shown as an anode 135 spaced apart from the metal substrate 120, is connected to the positive terminal (anode) of the power supply 190.
Electroplating is typically performed at a temperature of 15 ℃ to 30 ℃ to avoid the introduction of temperature-induced stresses, such as the introduction of interconnects on a semiconductor die. At the cathode, metal ions (e.g., dissolved in the plating solution 145)Cu+2) Are reduced at the interface between the solution and the cathode so that they plate out zero-valent metal (e.g., Cu metal) on the cathode. The plating is generally performed using Direct Current (DC), but may be performed as pulse plating.
A plated metal die attach layer, shown here as a single layer (such as comprising copper) including 187 in fig. 1F, is electroplated to fill the volume between the BSM layer 186 on the bottom surfaces of the semiconductor dies 180a and 180b and the walls of the metal substrate 120 defining the apertures 120a, 120b to provide die attachment. The time for the electroplating process may be calculated by dividing the desired thickness of the metal die attach layer 187 by the deposition rate. The thickness of the plated metal die attach layer 187 is designed to fill the apertures 120a, 120b, such as 10 to 250 μm thick, for example 40 to 250 μm thick.
Fig. 1F shows the portion of the apertures 120a, 120b not occupied by the semiconductor die 180 (under the die), now filled with a plated metal die attach layer 187, which is deposited as a sheet over the entire bottom surface of the metal substrate 120. Although the plated metal die attach layer 187 is shown as planar, there is typically a slight depression when over the respective apertures 120a, 120 b.
Plated metal die attach layer 187, which is a plated metal layer, is a unique layer even when compared to other layers of the same metal material deposited by other methods, such as a sputtered metal layer. Unlike sputtered layers, electrodeposited layers are known to fill areas outside of the line of sight. It is also known that electrodeposited layers have a unique microstructure that includes an initially deposited Nernst diffusion layer having a density and microstructure that is different from the density and microstructure of the bulk portion of the electrodeposited layer.
Fig. 2A shows a single leaded multi-chip semiconductor device 200 after the covered substrate stack is removed from the plating solution 145, the dielectric cover 130 is removed, the metal substrate 120 is cut, and the leads 126 are added, such as by soldering, to the metal pads 125b of the bump pads 125. The leaded multi-chip semiconductor device 200 may be considered an 18-lead package. The leads 126 comprise strips of metal (e.g., the same metal as the leadframe), such as commercially available or internally produced copper, copper alloy, or tin plated leads 126. For example, a metal sheet may be cut into metal strips for the leads 126.
The lead 126 has at least one bend and includes a distal portion that extends beyond the metal substrate 120. Although not shown, the leads 126 may be in a gull-wing arrangement. The wire 126 is typically soldered to the metal pad 125b, but may also be attached via soldering or by a conductive adhesive material. The bond wires 133 and 134 are shown as being added prior to dicing, including the bond wire 133 connected between the metal pad 125b of the bump pad 125 and the bond pad 181 on the semiconductor die 180a, 180 b. Also optional bond wires 134 are shown connected between bond pads 181 on respective semiconductor dies 180a, 180 b. Fig. 2B shows the disclosed leaded multi-chip packaged semiconductor device after a molding compound 290 is formed to provide a package for the packaged semiconductor device, now shown as 250.
The disclosed aspects can be integrated into a variety of assembly processes to form a variety of different multi-chip semiconductor package devices and related products. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements, and passive elements (including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc.). In addition, semiconductor die may be formed by a variety of processes including bipolar, Insulated Gate Bipolar Transistor (IGBT), CMOS, BiCMOS, and MEMS.
Those skilled in the art to which the disclosure relates will appreciate that many variations of the disclosed aspects are possible within the scope of the claimed invention, and that further additions, deletions, substitutions and modifications may be made to the above-described aspects without departing from the scope of the disclosure.

Claims (19)

1. A packaged semiconductor device, comprising:
a metal substrate having a first via aperture and a second via aperture, and a plurality of metal pads on a dielectric pad surrounding the first via aperture and the second via aperture, each via aperture having an outer ring;
a first semiconductor die and a second semiconductor die mounted with their top surfaces up on a top portion of the aperture, each die having a back side metal layer, or BSM, layer on its bottom surface;
a metal die attach layer located directly between the BSM layer and walls of the metal substrate that define the aperture to provide die attach for the first semiconductor die and the second semiconductor die that fill a bottom portion of the aperture;
a lead contacting the plurality of metal pads, wherein the lead includes a distal portion extending beyond the metal substrate;
bonding wires between the plurality of metal pads and bonding pads on the first semiconductor die and the second semiconductor die, an
A molding compound that provides a package for the packaged semiconductor device.
2. The packaged semiconductor device of claim 1 wherein said dielectric pad comprises a polymer.
3. The packaged semiconductor device of claim 1, wherein the metal die attach layer is comprised of a single layer.
4. The packaged semiconductor device of claim 1, wherein the BSM layer, the metal substrate, and the metal die attach layer each comprise copper.
5. The packaged semiconductor device of claim 1, wherein the metal die attach layer is a plated metal layer.
6. The packaged semiconductor device of claim 1, further comprising other bond wires between other bond pads on the first semiconductor die and other bond pads on the second semiconductor die.
7. The packaged semiconductor device of claim 1 wherein the metal die attach layer has a thickness of 40 to 250 μ ι η.
8. The packaged semiconductor device of claim 1 wherein the metal substrate has a thickness of 0.1mm to 0.3 mm.
9. A packaged semiconductor device, comprising:
a metal substrate having a first via aperture and a second via aperture, and a plurality of metal pads surrounding the first aperture and the second aperture on a dielectric pad, each via aperture having an outer ring;
a first semiconductor die and a second semiconductor die mounted with their top surfaces up on a top portion of the aperture, each die having a back side metal layer, or BSM, layer on its bottom surface;
a metal die attach layer located directly between the BSM layer and walls of the metal substrate that define the aperture to provide die attach for the first semiconductor die and the second semiconductor die that fill a bottom portion of the aperture;
a lead contacting the plurality of metal pads, wherein the lead includes a distal portion extending beyond the metal substrate;
bonding wires between the plurality of metal pads and bonding pads on the first and second semiconductor dies, an
A molding compound providing a package for the packaged semiconductor device,
wherein the metal die attach layer is comprised of a single layer, and
wherein the BSM layer, the metal substrate, and the metal die attach layer all comprise copper.
10. The packaged semiconductor device of claim 9, further comprising other bonding wires between other bonding pads on the first semiconductor die and on the second semiconductor die.
11. The packaged semiconductor device of claim 9 wherein the metal die attach layer has a thickness of 40 to 250 μ ι η.
12. A semiconductor assembly method for a multi-chip package, comprising:
providing a metal substrate comprising a repeating pattern of first and second via apertures each having an outer ring, and a plurality of metal pads on the dielectric pads surrounding the apertures, the outer rings being positioned to match the first and second semiconductor die, each having a backside metal (BSM) layer thereon;
inserting the first and second semiconductor dies, each having a bond pad, into a respective one of a plurality of apertures top-side up to sit on the outer ring;
sealing the top surfaces of the first and second semiconductor dies to secure the first and second semiconductor dies in the aperture to provide a plurality of covered substrate stacks;
immersing the plurality of covered substrate stacks in a metal plating solution within a solution container, wherein the metal substrate is connected to a negative terminal of a power supply and a conductive structure spaced apart from the metal substrate is connected to a positive terminal of the power supply, and
electroplating to deposit an electroplated metal die attach layer to fill a volume between the BSM layer and walls of the metal substrate defining the aperture to provide die attachment for the first semiconductor die and the second semiconductor die.
13. The method of claim 12, wherein sealing is performed using a dielectric cap, the method further comprising removing the dielectric cap after the electroplating and then wire bonding between the plurality of metal pads and the bond pads on the first and second semiconductor dies.
14. The method of claim 12, wherein an Ultraviolet (UV) light curable adhesive tape is used for the sealing.
15. The method of claim 12, further comprising printing on a dielectric pad of the metal substrate and then printing the metal pad on the dielectric pad.
16. The method of claim 12, wherein the metal plating solution comprises a copper plating solution, and wherein the BSM layer, the metal substrate, and the metal die attach layer each comprise copper.
17. The method of claim 12, wherein the dielectric pad comprises a polymer.
18. The method of claim 16, wherein wire bonding further comprises placing bonding wires between other bonding pads on the first semiconductor die and other bonding pads on the second semiconductor die.
19. The method of claim 12, further comprising forming a molding compound for encapsulating the packaged semiconductor device.
CN202080021334.0A 2019-03-20 2020-03-13 Multi-chip package with high thermal conductivity die attach Pending CN113574641A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/359,628 2019-03-20
US16/359,628 US10957635B2 (en) 2019-03-20 2019-03-20 Multi-chip package with high thermal conductivity die attach
PCT/US2020/022553 WO2020190680A1 (en) 2019-03-20 2020-03-13 Multi-chip package with high thermal conductivity die attach

Publications (1)

Publication Number Publication Date
CN113574641A true CN113574641A (en) 2021-10-29

Family

ID=72513877

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080021334.0A Pending CN113574641A (en) 2019-03-20 2020-03-13 Multi-chip package with high thermal conductivity die attach

Country Status (3)

Country Link
US (1) US10957635B2 (en)
CN (1) CN113574641A (en)
WO (1) WO2020190680A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220199502A1 (en) * 2020-12-18 2022-06-23 Semiconductor Components Industries, Llc Multiple substrate package systems and related methods
EP4292743A1 (en) * 2021-02-12 2023-12-20 NHK Spring Co., Ltd. Circuit board and manufacturing method

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6277672B1 (en) 1999-09-03 2001-08-21 Thin Film Module, Inc. BGA package for high density cavity-up wire bond device connections using a metal panel, thin film and build up multilayer technology
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
MY146344A (en) * 2007-10-23 2012-08-15 Semiconductor Components Ind Method of manufacturing a semiconductor component with a low cost leadframe using a non-metallic base structure
US7972905B2 (en) 2009-04-16 2011-07-05 Texas Instruments Incorporated Packaged electronic device having metal comprising self-healing die attach material
US20120199960A1 (en) 2011-02-07 2012-08-09 Texas Instruments Incorporated Wire bonding for interconnection between interposer and flip chip die
KR101264251B1 (en) 2011-08-03 2013-05-22 장종진 Metal substrate having multi reflective layer and Lighting emitting diode package using the same
US20130175704A1 (en) 2012-01-05 2013-07-11 Ixys Corporation Discrete power transistor package having solderless dbc to leadframe attach
US8994190B2 (en) 2012-05-22 2015-03-31 Freescale Semiconductor, Inc. Low-temperature flip chip die attach
US10879146B2 (en) * 2018-04-06 2020-12-29 Rohm Co., Ltd. Electronic component and manufacturing method thereof

Also Published As

Publication number Publication date
US20200303285A1 (en) 2020-09-24
WO2020190680A1 (en) 2020-09-24
US10957635B2 (en) 2021-03-23

Similar Documents

Publication Publication Date Title
US6350633B1 (en) Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint
US6830959B2 (en) Semiconductor die package with semiconductor die having side electrical connection
US6645791B2 (en) Semiconductor die package including carrier with mask
US7838978B2 (en) Semiconductor device
US6562709B1 (en) Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint
US10714417B2 (en) Semiconductor device with electroplated die attach
KR20010029402A (en) Chip scale surface mount package for semiconductor device and process of fabricating the same
KR20080070068A (en) Semiconductor die package using leadframe and clip and method of manufacturing
JP2019176034A (en) Semiconductor device and method for manufacturing semiconductor device
CN113574641A (en) Multi-chip package with high thermal conductivity die attach
US10109564B2 (en) Wafer level chip scale semiconductor package
US11282770B2 (en) Leadless packaged device with metal die attach
US20230143539A1 (en) Method of manufacturing semiconductor devices and corresponding semiconductor device
US10832993B1 (en) Packaged multichip device with stacked die having a metal die attach
US11908776B2 (en) Semiconductor device with metal die attach to substrate with multi-size cavity
US20210143107A1 (en) Semiconductor device package assemblies and methods of manufacture
US11004823B2 (en) Chip assembly and method of manufacturing thereof
US20240120247A1 (en) Method of Manufacturing a Semiconductor Package, Such Semiconductor Package as well as an Electronic System Comprising a PCB Element and at Least Such Semiconductor Package
CN114944341A (en) Packaging method of semiconductor structure, packaging structure and electronic equipment
CN116110871A (en) Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
Yue Planar packaging and electrical characterization of high temperature SiC power electronic devices

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination