CN113571570A

CN113571570A - Display panel and display device

Info

Publication number: CN113571570A
Application number: CN202110863579.4A
Authority: CN
Inventors: 王守坤; 秦韶阳; 郭子栋; 赵成雨; 孙增标; 顾维杰; 刘翔; 杜哲; 王刚
Original assignee: Hefei Visionox Technology Co Ltd
Current assignee: Hefei Visionox Technology Co Ltd
Priority date: 2021-07-29
Filing date: 2021-07-29
Publication date: 2021-10-29

Abstract

The application discloses a display panel and a display device. The display panel has a display area and a functional area which are adjacent to each other, and the display panel includes: a substrate; the driving device layer comprises a semiconductor layer, a gate insulating layer and a gate metal layer which are arranged in a stacked mode, the semiconductor layer is located on one side of the substrate, the gate insulating layer is located on one side, back to the substrate, of the semiconductor layer, and the gate metal layer is located on one side, back to the substrate, of the gate insulating layer; and the connecting lines are used for connecting two signal lines which are separated by the functional region and transmit the same signal, or the connecting lines are used for connecting the pixel circuit arranged in the display region and the light-emitting element arranged in the functional region, and at least part of the connecting lines is positioned on one side of the grid metal layer facing the substrate. According to the embodiment of the application, the display effect can be improved.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display device.

Background

With the rapid development of electronic equipment, the requirement of a user on the screen occupation ratio is higher and higher, and technologies such as a camera under the screen, a punching screen and the like are in the process of operation. For technologies such as a camera under a screen, a punching screen and the like, signal lines around a camera area or a perforated area need to be connected in a one-to-one correspondence manner by using a winding, or a light-emitting element in the camera area and a pixel circuit outside the camera area need to be connected in a one-to-one correspondence manner by using a winding, so that the wiring density of a display area provided with the winding and other display areas is different, and the display effect is influenced.

Disclosure of Invention

The embodiment of the application provides a display panel and a display device, which can improve the display effect.

In a first aspect, an embodiment of the present application provides a display panel, which has a display area and a functional area that are adjacent to each other, and the display panel includes: a substrate; the driving device layer comprises a semiconductor layer, a gate insulating layer and a gate metal layer which are arranged in a stacked mode, the semiconductor layer is located on one side of the substrate, the gate insulating layer is located on one side, back to the substrate, of the semiconductor layer, and the gate metal layer is located on one side, back to the substrate, of the gate insulating layer; and the connecting lines are used for connecting two signal lines which are separated by the functional region and transmit the same signal, or the connecting lines are used for connecting the pixel circuit arranged in the display region and the light-emitting element arranged in the functional region, and at least part of the connecting lines is positioned on one side of the grid metal layer facing the substrate.

In a possible implementation manner of the first aspect, at least a part of the plurality of connection lines is located between the semiconductor layer and the gate metal layer;

preferably, in the case where the connection line is used to connect the pixel circuit disposed within the display region and the light emitting element disposed within the functional region, the connection line is in direct contact with a source region or a drain region of an active layer of at least one transistor of the pixel circuit.

In one possible implementation of the first aspect, at least a portion of the plurality of connection lines is located between the semiconductor layer and the substrate;

preferably, in the case where the connection line connects the pixel circuit disposed within the display region and the light emitting element disposed within the functional region, the connection line is directly connected in contact with a source region or a drain region of an active layer of at least one transistor of the pixel circuit;

or, a buffer layer is disposed between the connection line and the semiconductor layer, and the connection line is connected to a pixel circuit disposed in the display region and a light emitting element disposed in the functional region, and the connection line is connected to a source region or a drain region of an active layer of at least one transistor of the pixel circuit through a via hole.

In a possible implementation of the first aspect, a buffer layer is provided between the connection line and the semiconductor layer, and an orthographic projection of the connection line on the substrate at least partially overlaps with an orthographic projection of a channel region of an active layer of at least one transistor of the pixel circuit on the substrate.

In a possible embodiment of the first aspect, the display area includes a main display area and a transition display area, the main display area and the transition display area are adjacent to each other, the transition display area surrounds at least a part of the functional area, the functional area is a light-transmitting display area, the functional area includes a first light-emitting element, the transition display area includes a first pixel circuit, and the connection line is used for connecting the first light-emitting element and the first pixel circuit;

the transitional display area further comprises a second light-emitting element and a second pixel circuit for driving the second light-emitting element, the main display area further comprises a third light-emitting element and a third pixel circuit for driving the third light-emitting element, the orthographic projection area of the first pixel circuit on the substrate is smaller than that of the third pixel circuit on the substrate, and/or the orthographic projection area of the second pixel circuit on the substrate is smaller than that of the third pixel circuit on the substrate, or the orthographic projection areas of the first pixel circuit, the second pixel circuit and the third pixel circuit on the substrate are the same.

In one possible implementation manner of the first aspect, the display area includes a main display area and a winding display area that are adjacent to each other, the winding display area surrounds at least a part of the functional area, and the display panel further includes:

a plurality of signal lines, each of which is electrically connected to a pixel circuit disposed in the display region and extends in a first direction, the plurality of signal lines including a plurality of first-type signal lines and a plurality of second-type signal lines, each of the second-type signal lines including a first section and a second section separated by a functional region;

the connecting wires are used for connecting the first section and the second section, and at least part of the connecting wires are positioned in the winding display area.

In a possible implementation manner of the first aspect, the first direction is a column direction, and the signal lines are data signal lines;

alternatively, the first direction is a row direction, and the signal line is a scanning signal line or a light emission control signal line or a reference voltage signal line.

In a possible implementation manner of the first aspect, the display area comprises a main display area and an auxiliary display area which are adjacent, and the function area is adjacent to the auxiliary display area;

the functional area comprises a gate drive circuit and a fourth light-emitting element, the auxiliary display area comprises a fourth pixel circuit, and the connecting line is used for connecting the fourth light-emitting element and the fourth pixel circuit;

preferably, the auxiliary display area further includes a fifth light emitting element and a fifth pixel circuit for driving the fifth light emitting element, the main display area further includes a third light emitting element and a third pixel circuit for driving the third light emitting element, an orthographic projection area of the fourth pixel circuit on the substrate is smaller than an orthographic projection area of the third pixel circuit on the substrate, and/or an orthographic projection area of the fifth pixel circuit on the substrate is smaller than an orthographic projection area of the third pixel circuit on the substrate, or the orthographic projection areas of the fourth pixel circuit, the second pixel circuit and the third pixel circuit on the substrate are the same.

In a possible embodiment of the first aspect, among the plurality of connection lines, the longer the connection line has the larger line width, and the shorter the connection line has the smaller line width.

In a second aspect, an embodiment of the present application provides a display device, including the display panel according to the first aspect.

According to the display panel and the display device provided by the embodiment of the application, at least part of the connecting lines are positioned on one side of the gate metal layer facing the substrate, so that the difference of the wiring density of other metal film layers arranged on one sides of the gate metal layer and the gate metal layer back to the substrate in the display area can be reduced.

Drawings

Other features, objects, and advantages of the present application will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.

Fig. 1 is a schematic top view illustrating a display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic top view illustrating a display panel according to an embodiment of the present disclosure;

fig. 3 is a schematic top view illustrating a display panel provided in an embodiment of the present application;

FIG. 4 shows an enlarged schematic view of the area Q1 of FIG. 1;

FIG. 5 shows another enlarged schematic view of the area Q2 of FIG. 2;

FIG. 6 shows an enlarged schematic view of the area Q3 of FIG. 3;

FIG. 7 shows a schematic cross-sectional view taken along line A-A of FIG. 4;

FIG. 8 shows a schematic cross-sectional view along line B-B of FIG. 5;

FIG. 9 shows another cross-sectional view in the direction B-B of FIG. 5;

FIG. 10 shows a schematic cross-sectional view in the direction C-C of FIG. 6;

fig. 11 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.

For technologies such as an off-screen camera and a punching screen, signal lines around a camera area or a hole area need to be connected in a one-to-one correspondence manner by using a winding, or a light-emitting element in the camera area needs to be connected with a pixel circuit outside the camera area in a correspondence manner by using a winding. Because the winding is additionally arranged in the winding display area, the wiring density of the winding display area and other display areas is different, the wiring density is different, and the reflection degree of ambient light or other light is different, so that the display effect of the winding display area and other display areas is different, and the whole display effect of the display panel is influenced.

In view of the above technical problems, embodiments of the present invention provide a display panel and a display device, which will be described below with reference to the accompanying drawings.

As shown in fig. 1 to 10, an embodiment of the present application provides a display panel 100 having a display area AA and a functional area UA adjacent to each other. The display panel 100 may be an Organic Light Emitting Diode (OLED) display panel.

It is to be understood that the display area AA may display, a light emitting device is disposed in the display area AA, and a pixel circuit for driving the light emitting device to emit light may be disposed in the display area AA. For example, the functional area UA may be a non-display area of a display panel, or the functional area UA may be a display area of a display panel. It is to be understood that when the functional region UA is a display region, a light-emitting element may be provided in the functional region UA, and when the functional region UA is a non-display region, a light-emitting element may not be provided in the functional region UA.

The functional area UA may be a rectangular area, a circular area, an elliptical area, or a square area, and the like, and the shape of the functional area UA may be set according to actual requirements, which is not limited in this application.

The functional area UA may be used to place a photosensitive element or a gate driving circuit may be disposed within the functional area UA. The photosensitive component can be an image acquisition device and is used for acquiring external image information. For example, the photosensitive component is a camera. The photosensitive component may not be limited to an image capture device, for example, in some embodiments, the photosensitive component may also be an infrared sensor, a proximity sensor, an infrared lens, a floodlight sensing element, an ambient light sensor, a dot matrix projector, and the like. The gate driving circuit is used for generating a scanning signal and/or a light emitting control signal.

The display panel 100 may include a substrate 10, a driving device layer 20, and a plurality of connection lines 30.

Illustratively, the substrate 10 may be a glass substrate or a flexible substrate. For example, as shown in any one of fig. 7 to 10, the substrate 10 may include a Glass base Glass, a first flexible layer PI1, a first barrier layer BL1, a second flexible layer PI2, and a second barrier layer BL2, which are stacked. The material of the first and second flexible layers PI1 and PI2 may include Polyimide (PI). The materials of the first barrier layer BL1 and the second barrier layer BL2 may include silicon oxide (SiOx).

The driving device layer 20 may also be referred to as an array layer, and a driving circuit of the display panel and at least a portion of signal lines (e.g., pixel circuits, gate driving circuits, scanning signal lines, data signal lines, light emission control signal lines, reference voltage signal lines, etc.) may be disposed on the driving device layer 20.

The driving device layer 20 includes a semiconductor layer B, a gate insulating layer GI and a gate metal layer M1, which are stacked, the semiconductor layer B is located on one side of the substrate 10, the gate insulating layer GI is located on one side of the semiconductor layer B opposite to the substrate 10, and the gate metal layer M1 is located on one side of the gate insulating layer GI opposite to the substrate 10.

Illustratively, the driving device layer 20 may further include a capacitor metal layer M2, a source/drain metal layer M3, an auxiliary metal layer M4, a capacitor insulating layer CI, an interlayer insulating layer ILD, a first planarizing layer PLN1, and a second planarizing layer PLN 2. The display panel may further include a light emitting layer 40. The light emitting layer 40 may include a pixel defining layer PDL and a light emitting element, and the light emitting element may include a first electrode RE, an organic light emitting layer OM, and a second electrode SE, which are stacked. Illustratively, the first electrode RE may be an anode, and the second electrode SE may be a cathode. The cathode of the display panel 100 may be a plane electrode.

The capacitor insulating layer CI is located between the gate metal layer M1 and the capacitor metal layer M2, the interlayer insulating layer ILD is located between the capacitor metal layer M2 and the source/drain metal layer M3, and the first planarization layer PLN1 is located between the source/drain metal layer M3 and the auxiliary metal layer M4. The second planarization layer PLN2 is located between the auxiliary metal layer M4 and the light emitting layer.

For example, the pixel circuit (not shown) of the display panel 100 may include transistors and capacitors, and the active layer of each transistor may be disposed on the semiconductor layer B. One plate of the capacitor may be disposed on the gate metal layer M1, and the other plate of the capacitor may be disposed on the capacitor metal layer M2.

For example, the display panel 100 may include a Scan signal line (Scan), a Data signal line (Data), a light emission control signal line (Emit), a reference voltage signal line (Vref), a power signal line (PVDD), and the like, which are not shown in the above signal line diagram, the Scan signal line and the light emission control signal line may be disposed on the gate metal layer M1, the reference voltage signal line may be disposed on the capacitor metal layer M2, and the Data signal line and the power signal line may be disposed on the source drain metal layer M3. For example, in order to reduce the voltage drop of the power signal line, the power signal line may have a mesh structure, a portion of the power signal line may be disposed on the source-drain metal layer M3, and another portion of the power signal line may be disposed on the auxiliary metal layer M4. It is understood that the extending direction of the power signal line disposed in the source-drain metal layer M3 may be the same as the extending direction of the data signal line, and the extending direction of the power signal line disposed in the auxiliary metal layer M4 may cross the extending direction of the data signal line.

In this case, the functional region UA may be referred to as a hole region, an open region, a grooved region, a blind hole region, a through hole region, or the like, and the functional region UA shown in fig. 4 is taken as an example of a non-display region, and the present application is not limited thereto. The functional area UA divides a part of the signal line 50 into two signal lines, which may be a data signal line, a scanning signal line, a light emission control signal line, a reference voltage signal line, and the like. In order to ensure the normal transmission of signals, two signal lines separated by the functional area UA need to be connected. Illustratively, the connection line 30 may be used to connect two signal lines that are separated by the functional area UA and transmit the same signal. For example, a part of the data signal line is divided into two segments of data signal traces by the functional area UA, and the connection line 30 may connect the two segments of data signal traces.

Taking the functional area UA shown in fig. 5 as a display area as an example, in this case, the functional area UA may also be referred to as a transparent display area, an off-screen camera area, or the like. Alternatively, taking the functional region UA shown in fig. 6 as a display region as an example, in this case, the functional region UA may also be referred to as a frame display region, a gate driver circuit region, or the like. Since the functional area UA is a display area, it is understood that a light emitting element is disposed in the functional area UA, and the light emitting element disposed in the functional area UA may be referred to as a first light emitting element PX 1. In order to increase the light transmittance of the functional area UA or because the space of the functional area UA is limited, a pixel circuit driving the first light emitting element PX1 may be disposed in the display area AA, and the pixel circuit driving the first light emitting element PX1 may be referred to as a first pixel circuit PU 1. In order to ensure that the first light-emitting element PX1 emits light, it is necessary to connect the first light-emitting element PX1 and the first pixel circuit PU 1. For example, the connection line 30 may be used to connect a pixel circuit (e.g., the first pixel circuit PU1) disposed within the display area AA and a light emitting element (e.g., the first light emitting element PX1) disposed within the functional area UA.

It is understood that, for the whole display area AA, the connection line 30 is disposed in a partial area, and the connection line 30 is not disposed in a partial area. That is to say, the area of the display area AA where the connecting lines 30 are disposed has a larger number of traces than the area where the connecting lines 30 are not disposed, so that the difference between the trace density of the area of the display area AA where the connecting lines 30 are disposed and the trace density of the area where the connecting lines 30 are not disposed is caused, and the reflection degree of the ambient light or other light is different.

The applicant finds that the influence of the reflection of light on the display effect is mainly reflected in the gate metal layer M1 and other metal film layers (e.g., the capacitor metal layer M2, the source/drain metal layer M3, and the auxiliary metal layer M4) on the side of the gate metal layer M1 opposite to the substrate 10, so that the difference in the trace density of the other metal film layers disposed in the display area AA on the side of the gate metal layer M1 and the gate metal layer M1 opposite to the substrate 10 can be reduced to reduce the display difference degree of the entire display area AA.

Based on the above findings, the display panel 100 according to the embodiment of the present application provides that at least some of the plurality of wires 30 are located on the side of the gate metal layer M1 facing the substrate 10. It is understood that at least a portion of the connection line 30 is located under the gate metal layer M1. For example, the total number of the connection lines 30 is 1000, at least 50% of the 1000 connection lines may be located on the side of the gate metal layer M1 facing the substrate 10, the other connection lines 30 may be located on the side of the gate metal layer M1 or the side of the gate metal layer M1 facing away from the substrate 10, or all the connection lines 30 may be located on the side of the gate metal layer M1 facing the substrate 10. The above numerical values are merely examples and are not intended to limit the present application.

Since at least a portion of the connecting lines 30 are located on the side of the gate metal layer M1 facing the substrate 10, the difference in the routing density of the other metal layers disposed on the side of the gate metal layer M1 and the side of the gate metal layer M1 facing away from the substrate 10 in the display area AA can be reduced, and it can be understood that, in the case that all the connecting lines 30 are located on the side of the gate metal layer M1 facing the substrate 10, the routing densities of the other metal layers disposed on the side of the gate metal layer M1 and the side of the gate metal layer M1 facing away from the substrate 10 in the display area AA can be considered to be equal, so that by disposing at least a portion of the connecting lines 30 on the side of the gate metal layer M1 facing the substrate 10, the difference in the reflection of light caused by the routing densities in different areas of the display area AA can be improved or eliminated, thereby reducing the display difference of the entire display area AA.

For example, at least a portion of the connection lines 30 in the plurality of connection lines 30 may be located on a side of the gate metal layer M1 facing the substrate 10, for example, at least a portion of the connection lines 30 may be located between the semiconductor layer B and the gate metal layer M1, for example, at least a portion of the connection lines 30 may be located between the semiconductor layer B and the substrate 10, for example, a portion of the connection lines 30 may be located between the semiconductor layer B and the gate metal layer M1, and another portion of the connection lines may be located between the semiconductor layer B and the substrate 10, and specific positions of the connection lines may be set according to specific needs.

In some alternative embodiments, in the case where the connection line 30 is located between the semiconductor layer B and the gate metal layer M1, and the connection line 30 is used to connect the pixel circuit disposed within the display area AA and the light emitting element disposed within the functional area UA, the connection line 30 is connected in direct contact with a source region or a drain region of an active layer of at least one transistor of the pixel circuit.

For example, as shown in fig. 8, the connection line 30 is used to connect the first pixel circuit PU1 disposed within the display area AA and the first light emitting element PX1 disposed within the functional area UA, and the first pixel circuit PU1 may include a plurality of transistors. As shown in fig. 8, an active layer of the transistor T may be disposed on the semiconductor layer B, the active layer may include a source region S, a drain region D, and a channel region P, the gate electrode G of the transistor T1 in the first pixel circuit PU1 may be disposed on the gate metal layer M1, an orthographic projection of the channel region P of the active layer on the substrate 10 overlaps an orthographic projection of the gate electrode G on the substrate 10, and neither the orthographic projection of the source region S, the orthographic projection of the drain region D on the substrate 10 nor the orthographic projection of the gate electrode G on the substrate 10 overlaps. The source region S and the drain region D may be understood as a heavily doped region of the active layer, and the channel region P may be understood as a lightly doped region of the active layer. The source region S and the drain region D may be a source and a drain of the transistor T1, respectively. The connection line 30 may be directly connected to the drain region D of the transistor T1 of the first pixel circuit PU1, that is, the connection line 30 may directly overlap the drain region D of the transistor T1 of the first pixel circuit PU1 without a via hole therebetween, so as to reduce the process complexity.

For example, in the process of manufacturing the display panel, the active layer of each transistor of the first pixel circuit PU1 may be formed first, then the connection line 30 may be formed, the formed connection line 30 may be directly overlapped with the drain region D of the active layer of at least one transistor, and then the gate insulating layer GI covering the active layer and the connection line 30 may be formed.

It is understood that, in the case that the connection line 30 is located between the semiconductor layer B and the gate metal layer M1, and the connection line 30 is used to connect two signal lines separated by the functional region UA and transmitting the same signal, the connection line 30 and the semiconductor layer B and the gate metal layer M1 are required to be insulated from each other, and the connection line 30 cannot constitute a gate of a transistor in a pixel circuit, so as to avoid signal crosstalk.

In some alternative embodiments, in the case where the connection line 30 is located between the semiconductor layer B and the substrate 10, and the connection line 30 is used to connect the pixel circuit disposed within the display area AA and the light emitting element disposed within the functional area UA, the connection line is connected in direct contact with a source region or a drain region of an active layer of at least one transistor of the pixel circuit.

For example, as shown in fig. 9, the connection line 30 is used to connect the first pixel circuit PU1 disposed within the display area AA and the first light emitting element PX1 disposed within the functional area UA, and the first pixel circuit PU1 may include a plurality of transistors. As shown in fig. 9, the active layer of the transistor T1 in the first pixel circuit PU1 may also be disposed on the semiconductor layer B, the active layer of the transistor T1 may also include a source region S, a drain region D, and a channel region P, and the gate G of the transistor T1 may be disposed on the gate metal layer M1. The source region S and the drain region D of the active layer of the transistor T1 may be a source and a drain of the transistor T1, respectively. The connection line 30 may be directly connected to the drain region D of the transistor T1 of the first pixel circuit PU1, that is, the drain region D of the transistor T1 of the first pixel circuit PU1 may be directly overlapped on the connection line 30 without a via hole therebetween, so that the process complexity may be reduced.

For example, in the process of manufacturing the display panel, the connection line 30 may be formed, the active layer of each transistor of the first pixel circuit PU1 may be formed, the drain region D of the active layer of at least one transistor of the first pixel circuit PU1 may be formed to directly overlap the connection line 30, and then the gate insulating layer GI may be formed to cover the active layer and the connection line 30.

It is understood that, in the case where the connection line 30 is located between the semiconductor layer B and the substrate 10, and the connection line 30 is used to connect two signal lines separated by the functional region UA and transmitting the same signal, the connection line 30 and the semiconductor layer B and the gate metal layer M1 are required to be insulated from each other, and the connection line 30 cannot constitute a gate of a transistor in the pixel circuit, so as to avoid signal crosstalk.

In some alternative embodiments, as shown in fig. 10, a buffer layer B2 is disposed between the connection line 30 and the semiconductor layer B. The buffer layer B2 between the connection line 30 and the semiconductor layer B is referred to herein as a second buffer layer. Illustratively, the display panel 100 further includes a first buffer layer B1. The first buffer layer B1 is located on a side of the substrate 10, the second buffer layer B2 is located on a side of the first buffer layer B1 facing away from the substrate 10, and the semiconductor layer B is located on a side of the second buffer layer B2 facing away from the substrate 10. The first buffer layer B1 and the second buffer layer B2 are both insulating layers. For example, the material of the first buffer layer B1 may include silicon nitride (SiNx), and the material of the second buffer layer B2 may include silicon oxide (SiOx).

The connection line 30 may be disposed between the first buffer layer B1 and the second buffer layer B2, and in the case where the connection line 30 is used to connect the pixel circuit disposed within the display area AA and the light emitting element disposed within the functional area UA, the connection line 30 is connected with a source region or a drain region of an active layer of at least one transistor of the pixel circuit through a via hole.

For example, as shown in fig. 10, the connection line 30 is used to connect the fourth pixel circuit PU4 disposed in the display area AA and the fourth light emitting element PX4 disposed in the functional area UA, and the fourth pixel circuit PU4 may also include a plurality of transistors. Fig. 10 is the same as fig. 8 or fig. 9, and the difference is that the connection line 30 is connected to the drain region D of the transistor T4 of the fourth pixel circuit PU4 through the via h1, so as to avoid the short circuit between the connection line 30 and the active layer of the other transistor in the fourth pixel circuit PU 4.

In some alternative embodiments, with continued reference to fig. 10, the connection line 30 is disposed between the first buffer layer B1 and the second buffer layer B2, and an orthographic projection of the connection line 30 on the substrate 10 at least partially overlaps with an orthographic projection of a channel region of an active layer of at least one transistor of the pixel circuit on the substrate 10. Fig. 10 shows that an orthographic projection of the connection line 30 on the substrate 10 at least partially overlaps with an orthographic projection of the channel region P of the active layer of the transistor T4 of the fourth pixel circuit PU4 on the substrate 10. The light irradiation may have an irreversible effect on the characteristics of the transistor, and the connection line 30 blocks the channel region of the active layer of the transistor, thereby preventing the light from being incident on the channel region, and thus preventing the light irradiation from affecting the characteristics of the transistor.

In some alternative embodiments, the material of the connection line 30 may include molybdenum (Mo), Indium Tin Oxide (ITO), or the connection line 30 may be a titanium/aluminum/titanium (Ti/Al/Ti) metal stack structure, which is not limited in this application.

For example, in the case where the connection line 30 is used to connect the light emitting element and the pixel circuit, as shown in any one of fig. 8 to 10, the connection line 30 may be connected to the first electrode RE of the light emitting element through a via hole. In order to reduce the difficulty in preparing the connection via hole between the connection line 30 and the light emitting element, the via hole between the connection line 30 and the light emitting element may include at least two via holes, thereby reducing the depth of a single via hole and reducing the difficulty in preparing the via hole.

In some alternative embodiments, the lengths of the plurality of connection lines 30 are different, and the line width of the connection lines 30 with longer lengths may be larger, and the line width of the connection lines 30 with shorter lengths may be smaller. Therefore, the resistances of different connecting lines 30 tend to be consistent, and the display difference caused by the different resistances of the connecting lines 30 is improved.

In some alternative embodiments, with reference to fig. 2, fig. 5 and fig. 8, the display area AA includes a main display area a1 and a transition display area A3, the transition display area A3 surrounds at least a portion of the functional area UA, the functional area UA is a light-transmissive display area, the functional area UA includes a first light-emitting element PX1, the transition display area A3 includes a first pixel circuit PU1, and the connection line 30 connects the first light-emitting element PX1 and the first pixel circuit PU 1. Fig. 5 shows the pixel circuits in the respective regions in a hidden manner for clarity.

The transition display area A3 further includes a second light emitting element PX2 and a second pixel circuit PU2 for driving the second light emitting element PX2, and the main display area a1 further includes a third light emitting element PX3 and a third pixel circuit PU3 for driving the third light emitting element PX 3. Optionally, an orthographic projection area of the first pixel circuit PU1 on the substrate 10 is smaller than an orthographic projection area of the third pixel circuit PU3 on the substrate 10, and/or an orthographic projection area of the second pixel circuit PU2 on the substrate 10 is smaller than an orthographic projection area of the third pixel circuit PU3 on the substrate 10. That is, the size of the first pixel circuit PU1 and/or the second pixel circuit PU2 may be compressed. Illustratively, alternatively, the orthographic projection area of the first pixel circuit PU1 on the substrate 10 may be equal to the orthographic projection area of the second pixel circuit PU2 on the substrate 10.

In the case of a high pixel density of the display panel, the density of the pixel circuits on the display panel 100 is also high, and usually the pixel circuits on the whole display panel are arranged in close proximity, that is, if the second pixel circuit PU2 originally in the transition display area A3 or the first pixel circuit PU1 driving the first light-emitting element PX1 is not compressed, the transition display area A3 has no extra space for placing the first pixel circuit PU1, but in the embodiment of the present application, by compressing the size of the first pixel circuit PU1 and/or the second pixel circuit PU2, there is enough space for placing the first pixel circuit PU1 in the transition display area A3.

Alternatively, the orthographic projection area of the first pixel circuit PU1 on the substrate 10, the orthographic projection area of the second pixel circuit PU2 on the substrate 10, and the orthographic projection area of the third pixel circuit PU3 on the substrate 10 may be equal. That is to say, under the condition that the pixel density of the display panel is high, the sizes of the first pixel circuit PU1, the second pixel circuit PU2 and the third pixel circuit PU3 can be compressed, so that not only the transition display area A3 is provided with enough space for placing the first pixel circuit PU1, but also the driving capability difference caused by the different sizes of the pixel circuits can be avoided, and the display unevenness is avoided.

Alternatively, the pixel density of the transition display area a3 and the functional area UA may be reduced, and the sizes of the first pixel circuit PU1 and the second pixel circuit PU2 may not be compressed, so that the orthographic projection area of the first pixel circuit PU1 on the substrate 10, the orthographic projection area of the second pixel circuit PU2 on the substrate 10, and the orthographic projection area of the third pixel circuit PU3 on the substrate 10 are also equal.

In some alternative embodiments, the circuit structures of the first pixel circuit PU1, the second pixel circuit PU2 and the third pixel circuit PU3 may be the same, and the first pixel circuit PU1, the second pixel circuit PU2 and the third pixel circuit PU3 each include a transistor and a capacitor. The compression of the sizes of the first pixel circuit PU1, the second pixel circuit PU2, and the third pixel circuit PU3 may be achieved by compressing the sizes of transistors in each pixel circuit.

Exemplarily, the forward projection area of the pixel circuit on the substrate 10 may be understood as the sum of the forward projection areas of the transistors included in the pixel circuit and the capacitor on the substrate 10.

For example, the first pixel circuits PU1 and the second pixel circuits PU2 in the transition display area a3 may be alternately distributed in the first direction X, and all the first pixel circuits PU1 may also be distributed close to the functional area. The first pixel circuit PU1, the second pixel circuit PU2, and the third pixel circuit PU3 may be distributed in an array.

Illustratively, the circuit structures of the first pixel circuit PU1, the second pixel circuit PU2, and the third pixel circuit PU3 are all the circuit structures of 7T1C as shown in fig. 11. In fig. 11, T11 to T17 indicate 7 transistors, Cst indicates a storage capacitor, D indicates a light emitting element, Scan1 indicates a first Scan signal line, Scan2 indicates a second Scan signal line, Data indicates a Data signal line, Emit indicates a light emission control signal line, Vref indicates a reference voltage signal line, PVDD power supply signal line, and PVEE indicates a common voltage terminal.

Of course, the circuit structures of the first pixel circuit PU1, the second pixel circuit PU2, and the third pixel circuit PU3 may be 2T1C, 4T1C, 6T1C, 6T2C, 7T2C, and the like, which is not limited in this application. Where "T" represents a transistor, "C" represents a capacitance, "7T 1C" represents having 7 transistors and 1 capacitance, and so on.

In some alternative embodiments, referring to fig. 1 and 4 in combination, display area AA includes contiguous main display area a1 and winding display area a2, winding display area a2 surrounding at least part of functional area UA. For example, the functional area UA may be a display area or a non-display area.

The display panel 100 further includes a plurality of signal lines 50, each signal line 50 is electrically connected to a pixel circuit disposed in the display area AA and extends along the first direction X, the plurality of signal lines 50 includes a plurality of first type signal lines 51 and a plurality of second type signal lines 52, and each second type signal line 52 includes a first segment 521 and a second segment 522 separated by the functional area UA. In order to provide signals to the pixel driving circuit electrically connected to the same second-type signal line 52, the first and

second segments

521 and 522, which are separated from each other, may be connected by a connection line 30 (the connection line 30 is illustrated by a dotted line).

For example, the connection line 30 may be disposed in the winding display area a2, taking the functional area UA as the non-display area as an example, since the connection line 30 is located in the winding display area a2, the frame area of the functional area UA can be reduced, that is, the area of the non-display area can be reduced, thereby increasing the screen area of the display panel.

The plurality of signal lines 50 extend in a first direction X and are spaced apart in a second direction Y, the first direction X intersecting the second direction Y, for example, the first direction X and the second direction Y may be perpendicular.

Alternatively, the first direction X may be a column direction, and the signal lines 50 may be Data signal lines (Data).

Alternatively, the first direction X may be a row direction, and the signal line 50 may be a Scan signal line (Scan), a light emission control signal line (Emit), or a reference voltage signal line (Vref).

In some alternative embodiments, referring to fig. 3, 6 and 9 in combination, display area AA includes adjacent main display area a1 and auxiliary display area a4, and functional area UA is adjacent to auxiliary display area a 4. The functional region UA includes the gate driving circuit VSR and the fourth light emitting element PX4, the auxiliary display region a4 includes a fourth pixel circuit PU2, and the connection line 30 is used to connect the fourth light emitting element PX4 and the fourth pixel circuit PU 4.

According to the embodiment of the application, the non-display area originally provided with the gate driving circuit VSR is also designed as the display area, so that the whole display area of the display panel is increased, and the screen occupation ratio is increased.

Illustratively, the auxiliary display area a4 further includes a fifth light emitting element PX5 and a second pixel circuit PU5 for driving the fifth light emitting element PX5, and the main display area a1 further includes a third light emitting element PX3 and a third pixel circuit PU3 for driving the third light emitting element PX 3. Alternatively, the orthographic projection area of the fourth pixel circuit PU4 on the substrate 10 is smaller than the orthographic projection area of the third pixel circuit PU3 on the substrate 10, and/or the orthographic projection area of the fifth pixel circuit PU5 on the substrate 10 is smaller than the orthographic projection area of the third pixel circuit PU3 on the substrate 10. That is, the size of the fourth pixel circuit PU4 and/or the second pixel circuit PU2 may be compressed. Illustratively, alternatively, the orthographic projection area of the fourth pixel circuit PU4 on the substrate 10 may be equal to the orthographic projection area of the fifth pixel circuit PU5 on the substrate 10. As described above, in the case of a high pixel density of the display panel, the density of the pixel circuits on the display panel 100 is also high, and the pixel circuits on the whole display panel are usually arranged in close proximity, that is, if the fifth pixel circuit PU5 originally in the auxiliary display area a4 or the fourth pixel circuit PU4 driving the fourth light-emitting element PX4 is not compressed, the auxiliary display area a4 has no extra space for placing the fourth pixel circuit PU4, but in the embodiment of the present application, the fourth pixel circuit PU4 and/or the fifth pixel circuit PU5 are/is compressed in size, so that there is enough space for placing the fourth pixel circuit PU4 in the auxiliary display area a 4.

Alternatively, the forward projection area of the fourth pixel circuit PU4 on the substrate 10, the forward projection area of the fifth pixel circuit PU5 on the substrate 10, and the forward projection area of the third pixel circuit PU3 on the substrate 10 may be equal. That is to say, under the condition that the pixel density of the display panel is high, the sizes of the fourth pixel circuit PU4, the fifth pixel circuit PU5 and the third pixel circuit PU3 can be compressed, so that not only is there enough space in the auxiliary display area a4 for placing the fourth pixel circuit PU4, but also the driving capability difference caused by the different sizes of the pixel circuits can be avoided, thereby avoiding the display unevenness.

For example, the pixel density of the functional area UA and the auxiliary display area a4 may be reduced, the sizes of the fourth pixel circuit PU4 and the fifth pixel circuit PU5 are not compressed, and the forward projection area of the fourth pixel circuit PU4 on the substrate 10, the forward projection area of the fifth pixel circuit PU5 on the substrate 10, and the forward projection area of the third pixel circuit PU3 on the substrate 10 may be equal.

In some alternative embodiments, the circuit structures of the fourth pixel circuit PU4, the fifth pixel circuit PU5, and the third pixel circuit PU3 may be the same, and the first pixel circuit PU1, the fifth pixel circuit PU5, and the third pixel circuit PU3 may include transistors. The compression of the sizes of the fourth pixel circuit PU4, the fifth pixel circuit PU5, and the third pixel circuit PU3 may be achieved by compressing the sizes of the transistors in the respective pixel circuits.

For example, the fourth pixel circuits PU4 and the fifth pixel circuits PU5 in the auxiliary display area a4 may be alternately distributed in the first direction X, and all the fourth pixel circuits PU4 may also be distributed close to the functional area. The fourth pixel circuit PU4, the fifth pixel circuit PU5, and the third pixel circuit PU3 may be distributed in an array.

Illustratively, the circuit structures of the fourth pixel circuit PU4, the fifth pixel circuit PU5, and the third pixel circuit PU3 are all the circuit structures of 7T1C as shown in fig. 10. In fig. 10, T11 to T17 indicate 7 transistors, Cst indicates a storage capacitor, D indicates a light emitting element, Scan1 indicates a first Scan signal line, Scan2 indicates a second Scan signal line, Data indicates a Data signal line, Emit indicates a light emission control signal line, Vref indicates a reference voltage signal line, PVDD power supply signal line, and PVEE indicates a common voltage terminal.

Of course, the circuit structures of the fourth pixel circuit PU4, the fifth pixel circuit PU5, and the third pixel circuit PU3 may be 2T1C, 4T1C, 6T1C, 6T2C, 7T2C, and the like, which is not limited in this application. Where "T" represents a transistor, "C" represents a capacitance, "7T 1C" represents having 7 transistors and 1 capacitance, and so on.

It should be noted that the above embodiments may be combined with each other without contradiction.

As shown in fig. 12, an embodiment of the present application further provides a display device 1000 including the display panel 100 according to the above embodiment. Since the display device 1000 includes the display panel 100 according to the above embodiment, the display device 1000 has the advantages of the display panel 100 according to the above embodiment, and will not be described in detail herein.

The display device can be any electronic equipment with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic paper book or a television.

In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel having a display area and a function area which are adjacent to each other, the display panel comprising:

a substrate;

the driving device layer comprises a semiconductor layer, a gate insulating layer and a gate metal layer which are arranged in a stacked mode, the semiconductor layer is located on one side of the substrate, the gate insulating layer is located on one side, back to the substrate, of the semiconductor layer, and the gate metal layer is located on one side, back to the substrate, of the gate insulating layer;

and a plurality of connection lines for connecting two signal lines separated by the functional region and transmitting the same signal, or for connecting a pixel circuit disposed in the display region and a light emitting element disposed in the functional region, wherein at least a part of the plurality of connection lines is located on a side of the gate metal layer facing the substrate.

2. The display panel according to claim 1, wherein at least a part of the plurality of connection lines is located between the semiconductor layer and the gate metal layer;

preferably, in a case where the connection line is used to connect a pixel circuit provided in the display region and a light emitting element provided in the functional region, the connection line is in direct contact with a source region or a drain region of an active layer of at least one transistor of the pixel circuit.

3. The display panel according to claim 1, wherein at least part of the plurality of connection lines is located between the semiconductor layer and the substrate;

preferably, in the case where the connection line connects the pixel circuit disposed within the display region and the light emitting element disposed within the functional region, the connection line is in direct contact with a source region or a drain region of an active layer of at least one transistor of the pixel circuit;

or, a buffer layer is disposed between the connection line and the semiconductor layer, and the connection line is used to connect a pixel circuit disposed in the display region and a light emitting element disposed in the functional region, and the connection line is connected to a source region or a drain region of an active layer of at least one transistor of the pixel circuit through a via hole.

4. A display panel as claimed in claim 3 characterized in that a buffer layer is arranged between the connection line and the semiconductor layer, an orthographic projection of the connection line on the substrate at least partially overlapping an orthographic projection of a channel region of an active layer of at least one transistor of the pixel circuit on the substrate.

5. The display panel according to any one of claims 1 to 4, wherein the display region comprises a main display region and a transition display region which are adjacent to each other, the transition display region surrounds at least a part of the functional region, the functional region is a light-transmitting display region, the functional region includes a first light-emitting element, the transition display region includes a first pixel circuit, and the connection line is used for connecting the first light-emitting element and the first pixel circuit;

the transition display area further comprises a second light-emitting element and a second pixel circuit for driving the second light-emitting element, the main display area further comprises a third light-emitting element and a third pixel circuit for driving the third light-emitting element, the orthographic projection area of the first pixel circuit on the substrate is smaller than that of the third pixel circuit on the substrate, and/or the orthographic projection area of the second pixel circuit on the substrate is smaller than that of the third pixel circuit on the substrate, or the orthographic projection areas of the first pixel circuit, the second pixel circuit and the third pixel circuit on the substrate are the same.

6. The display panel according to any one of claims 1 to 4, wherein the display region includes a main display region and a winding display region that are adjacent to each other, the winding display region surrounding at least a part of the functional region, the display panel further comprising:

a plurality of signal lines, each of which is electrically connected to a pixel circuit disposed in the display region and extends in a first direction, the plurality of signal lines including a plurality of first-type signal lines and a plurality of second-type signal lines, each of the second-type signal lines including a first section and a second section separated by the functional region;

the connecting line is used for connecting the first section and the second section, and at least part of the connecting line is positioned in the winding display area.

7. The display panel according to claim 6, wherein the first direction is a column direction, and the signal lines are data signal lines;

or, the first direction is a row direction, and the signal line is a scanning signal line or a light-emitting control signal line or a reference voltage signal line.

8. The display panel according to any one of claims 1 to 4, wherein the display region includes a main display region and an auxiliary display region which are adjacent, and the function region is adjacent to the auxiliary display region;

the functional region comprises a gate drive circuit and a fourth light-emitting element, the auxiliary display region comprises a fourth pixel circuit, and the connecting line is used for connecting the fourth light-emitting element and the fourth pixel circuit;

preferably, the auxiliary display area further includes a fifth light emitting element and a fifth pixel circuit for driving the fifth light emitting element, the main display area further includes a third light emitting element and a third pixel circuit for driving the third light emitting element, an orthographic projection area of the fourth pixel circuit on the substrate is smaller than an orthographic projection area of the third pixel circuit on the substrate, and/or an orthographic projection area of the fifth pixel circuit on the substrate is smaller than an orthographic projection area of the third pixel circuit on the substrate, or the orthographic projection areas of the fourth pixel circuit, the fifth pixel circuit and the third pixel circuit on the substrate are the same.

9. The display panel according to claim 1, wherein the longer the connection line among the plurality of connection lines, the larger the line width of the connection line, and the shorter the line width of the connection line.

10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.