CN113380830A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
- Publication number
- CN113380830A CN113380830A CN202010115764.0A CN202010115764A CN113380830A CN 113380830 A CN113380830 A CN 113380830A CN 202010115764 A CN202010115764 A CN 202010115764A CN 113380830 A CN113380830 A CN 113380830A
- Authority
- CN
- China
- Prior art keywords
- signal line
- electrically connected
- thin film
- film transistor
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 34
- 239000010409 thin film Substances 0.000 claims description 90
- 238000004804 winding Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 9
- 230000009471 action Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses an array substrate, a display panel and a display device. The array substrate is provided with a light-transmitting area, a frame area surrounding the light-transmitting area and a display area surrounding the frame area; the display area is provided with a first signal line group and a second signal line group which are used for connecting the pixel circuits, extend along a first direction and are positioned on two sides of the light-transmitting area; the frame area is provided with a general connecting line which extends around the light-transmitting area; the first signal line group comprises more than one first signal line electrically connected with the main connecting line, and the second signal line group comprises more than one second signal line electrically connected with the main connecting line; at least part of the more than one first signal lines and the more than one second signal lines are electrically connected with the main connecting line through the switching device. According to the embodiment of the invention, the number of the winding wires in the frame area can be reduced, and the mutual influence between the signal wires can be avoided.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
With the rapid development of electronic devices, the requirement of users on screen occupation ratio is higher and higher, and traditional electronic devices such as mobile phones, tablet computers and the like need to integrate front cameras, earphones, infrared sensing elements and the like. In the prior art, a groove (Notch) or an opening may be formed in a display screen, and external light may enter a photosensitive component located below the screen through the groove or the opening. Because the signal lines around the slot or the open hole need to be connected in a one-to-one correspondence manner, a larger wiring space needs to be arranged around the slot or the open hole, and the screen occupation ratio of the display screen is influenced.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a display panel and a display device, which can reduce the number of winding wires in a frame area and can avoid the mutual influence between adjacent signal wires.
In a first aspect, an embodiment of the present invention provides an array substrate, which has a light-transmissive region, a frame region surrounding the light-transmissive region, and a display region surrounding the frame region;
the display area is provided with a first signal line group and a second signal line group which are used for connecting the pixel circuits, extend along a first direction and are positioned on two sides of the light-transmitting area;
the frame area is provided with a general connecting line which extends around the light-transmitting area;
the first signal line group comprises more than one first signal line electrically connected with the main connecting line, and the second signal line group comprises more than one second signal line electrically connected with the main connecting line;
at least part of the more than one first signal lines and the more than one second signal lines are electrically connected with the main connecting line through the switching device.
In one possible implementation of the first aspect, the switching device comprises a thin film transistor.
In one possible implementation of the first aspect, the thin film transistor includes a first thin film transistor and a second thin film transistor, the first signal line is electrically connected to the bus connection line through the first thin film transistor, and the second signal line is electrically connected to the bus connection line through the second thin film transistor.
In a possible implementation manner of the first aspect, a first end of the first thin film transistor is electrically connected to the first signal line, a second end of the first thin film transistor is electrically connected to the bus connection line, and a control end of the first thin film transistor is electrically connected to the scan line arranged in the same row as the first signal line;
the first end of the second thin film transistor is electrically connected with the second signal line, the second end of the second thin film transistor is electrically connected with the general connecting line, and the control end of the second thin film transistor is electrically connected with the scanning line arranged in the same row as the second signal line.
In a possible implementation manner of the first aspect, the display area has two opposite edges in the first direction, one of the two edges is a first edge, and the light-transmitting area and the frame area are disposed near the first edge of the display area;
the signal wire far away from the first edge in the first signal wire and the second signal wire is electrically connected with the main connecting wire through the thin film transistor, one signal wire in the signal wire close to the first edge in the first signal wire and the second signal wire is directly and electrically connected with the main connecting wire, and other signal wires extend to the edge of the frame area.
In a possible implementation manner of the first aspect, the first signal line is close to the first edge, any one of the outermost first signal lines in the first signal line group in the second direction is directly electrically connected with the bus connection line, and the other first signal lines extend to the edge of the frame region; or the second signal line is close to the first edge, any one second signal line on the outermost side in the second signal line group is directly and electrically connected with the total connecting line in the second direction, and other second signal lines extend to the edge of the frame area; wherein the second direction intersects the first direction.
In one possible implementation of the first aspect, the first signal line is electrically connected to the first driving circuit, and the second signal line is electrically connected to the second driving circuit.
In one possible implementation of the first aspect, the thin film transistor is of the same type as the thin film transistor in the pixel circuit.
In a second aspect, an embodiment of the present invention provides a display panel, including the array substrate according to any one of the embodiments of the first aspect.
In a third aspect, an embodiment of the present invention provides a display device, including the display panel according to the second aspect.
According to the array substrate, the display panel and the display device provided by the embodiment of the invention, only one main connecting line is arranged in the frame area surrounding the light-transmitting area, so that the number of winding wires in the frame area can be reduced, and a narrow frame is realized. In addition, at least part of the first signal line group and the second signal line group which are positioned at two sides of the light-transmitting area are electrically connected with the main connecting line through the switching device, so that the communication of the signal lines can be controlled by controlling the on and off of the switching device, and the mutual influence between the signal lines can be avoided.
Drawings
Other features, objects and advantages of the invention will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.
Fig. 1 is a schematic top view illustrating an array substrate according to a first embodiment of the present invention;
FIG. 2 is an enlarged schematic view of region A of FIG. 1 according to one embodiment of the present invention;
fig. 3 is a schematic top view illustrating an array substrate according to a second embodiment of the present invention;
FIG. 4 is an enlarged schematic view of region B of FIG. 3 according to one embodiment of the present invention;
fig. 5 is a schematic top view illustrating an array substrate according to a second embodiment of the invention;
FIG. 6 is an enlarged schematic view of region C of FIG. 5 in accordance with an embodiment of the present invention;
fig. 7 is a schematic top view illustrating a display panel according to an embodiment of the invention.
Description of reference numerals:
100-an array substrate;
10-a light-transmitting region; 20-a frame area; 30-a display area; NA-non-display area;
21-bus connection line; 31-pixel circuits; 32-a switching device; 321-a first thin film transistor; 322-a second thin film transistor; 33L-a first signal line group; 33R-second signal line group; 331-a first signal line; 332-a second signal line; 34-scan line; s-a first edge; 35-a third signal line;
x-a first direction; y-a second direction;
200-a display panel; 201-light emitting layer.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
Fig. 1 is a schematic top view illustrating an array substrate according to a first embodiment of the present invention. Fig. 2 is an enlarged schematic view of the area a in fig. 1 according to an embodiment of the present invention. As shown in fig. 1 and 2, an array substrate 100 according to an embodiment of the present invention includes a transparent region 10, a frame region 20, and a display region 30. A border region 20 is disposed around the light-transmissive region. The display area 30 is disposed around the rim area 20.
Illustratively, the light-transmissive region 10 may be an open region or a grooved region for placing the photosensitive element. The photosensitive component can be an image acquisition device and is used for acquiring external image information. For example, the photosensitive component is a camera. The photosensitive component may not be limited to an image capture device, for example, in some embodiments, the photosensitive component may also be an infrared sensor, a proximity sensor, an infrared lens, a floodlight sensing element, an ambient light sensor, a dot matrix projector, and the like.
The light-transmitting area 10 may be a circular area, an elliptical area, a square area, or the like, and the shape of the light-transmitting area 10 may be set according to actual requirements, which is not limited in the present invention.
Illustratively, the array substrate 100 may further include a non-display area NA disposed around the display area 30.
The display region 30 is provided with a pixel circuit 31 and a signal line electrically connected to the pixel circuit 31. The pixel circuit 31 is used to drive the sub-pixel to emit light for display. The signal lines extend along a first direction X, and in the first direction X, the signal lines are divided into a first signal line group 33L and a second signal line group 33R located at two sides of the light-transmitting region 10. The first signal line group 33L includes one or more first signal lines 331, and the second signal line group 33R includes one or more second signal lines 332. Illustratively, the number of the first signal lines 331 is equal to the number of the second signal lines 332, for example, the number of the first signal lines 331 and the number of the second signal lines 332 are both N, N is a positive integer, and N first signal lines 331 and N second signal lines 332 are arranged at intervals in the second direction Y. Wherein the first direction X intersects the second direction Y. The first direction X and the second direction Y may be perpendicular.
The border area 20 is provided with a global connection line 21 extending around the light-transmitting area 10. The bus connection line 21 may be provided in a ladder type according to the arrangement of the pixel circuits 31 to further reduce the occupied area of the frame region 20.
The one or more first signal lines 331 are electrically connected to the bus connection line 21, and the one or more second signal lines 332 are electrically connected to the bus connection line 21. The frame area 20 is only provided with one bus connection line 21, and compared with the case where a plurality of connection lines are provided to connect the corresponding first signal lines 331 and the second signal lines 332, the number of the connection lines can be reduced, so that the occupied area of the frame area 20 is reduced, and the narrow frame design is realized.
Further, at least a part of the one or more first signal lines 331 and the one or more second signal lines 332 is electrically connected to the bus connection line 21 through the switching device 32.
According to the embodiment of the invention, the connection of the corresponding first signal line 331 and/or the second signal line 332 can be controlled by controlling the on and off of the switching device 32, and the mutual influence between the signal lines can be avoided.
Illustratively, herein, the first signal line 331 and the second signal line 332 may be a reference voltage (Vref) signal line, and may also be a power supply voltage (Vdd) signal line.
For example, the switching device 32 may receive a control signal and perform an on or off action in response to the received control signal. For example, when the switching device 32 is turned on, the corresponding first signal line 331 and/or second signal line 332 and the bus connection line 21 are electrically connected, and when the switching device 32 is turned off, the corresponding first signal line 331 and/or second signal line 332 and the bus connection line 21 are not electrically connected.
In some embodiments, switching device 32 may comprise a thin film transistor. As shown in fig. 2, each switching device 32 may be a thin film transistor. The thin film transistor includes a source electrode, a drain electrode, and a gate electrode, the gate electrode may receive a control signal, the source electrode and the drain electrode are turned on, and the corresponding first signal line 331 and/or the second signal line 332 are turned on with the bus connection line 21. Illustratively, the pixel circuit 31 includes a plurality of thin film transistors, and the thin film transistors connecting the first signal line 331 and/or the second signal line 332 with the bus connection line 21 and the thin film transistors in the pixel circuit 31 may be formed simultaneously in the same process step. I.e., the switching device 32 is a thin film transistor, the process steps can be simplified.
In some embodiments, for example, as shown in fig. 1 and fig. 2, the light-transmitting region 10 is located approximately in the middle region of the array substrate 100 in the first direction X, and each of the first signal lines 331 may be electrically connected to the bus connection line 21 through one switching device 32, and each of the second signal lines 332 may be electrically connected to the bus connection line 21 through one switching device 32. When the switching device 32 is a thin film transistor, the thin film transistor includes a first thin film transistor 321 and a second thin film transistor 322, the first signal line 331 is electrically connected to the bus connection line 21 through the first thin film transistor 321, and the second signal line 332 is electrically connected to the bus connection line 21 through the second thin film transistor 322. So set up, guarantee that every signal line can both be controlled alone, further reduce the influence each other between the signal line.
In some embodiments, as shown in fig. 2, a first terminal of the first thin film transistor 321 is electrically connected to the first signal line, a second terminal of the first thin film transistor 321 is electrically connected to the bus line, and a control terminal of the first thin film transistor 321 is electrically connected to the scan line 34 disposed in the same row as the first signal line 331.
Illustratively, N rows of pixel circuits 31 are disposed on the left and right sides of the light-transmitting region 10, respectively, and correspondingly, the number of the first thin film transistors 321 and the number of the second thin film transistors 322 are N, the number of the first signal lines 331 is N, and the N rows of pixel circuits 31 correspond to N scan lines. A first terminal of the ith first thin film transistor 321 in the second direction Y is electrically connected to the ith first signal line 331 in the second direction Y, a second terminal of the first thin film transistor 321 is electrically connected to the bus connection line 21, and a control terminal of the first thin film transistor 321 is electrically connected to the ith scan line 34 in the second direction Y.
Referring to fig. 2, a first end of the second thin film transistor 322 is electrically connected to the second signal line 332, a second end of the second thin film transistor 322 is electrically connected to the bus connection line 21, and a control end of the second thin film transistor 322 is electrically connected to the scan line 34 disposed in the same row as the second signal line 332. A first terminal of the ith second thin film transistor 322 in the second direction Y is electrically connected to the ith second signal line 332 in the second direction Y, a second terminal of the second thin film transistor 322 is electrically connected to the bus connection line 21, and a control terminal of the second thin film transistor 322 is electrically connected to the ith scan line 34 in the second direction Y.
In the above example, the first terminal of the first thin film transistor 321 may be a source, and the second terminal of the first thin film transistor 321 may be a drain. The first terminal of the second thin film transistor 322 may be a drain, and the second terminal of the second thin film transistor 322 may be a source. The control terminal of the first thin film transistor 321 and the control terminal of the second thin film transistor 322 are both gates.
The gates of the tfts are electrically connected to the scan lines 34 in the corresponding row, and the first tft 321 and the second tft 322 can be controlled to be turned on by the scan signals provided by the scan lines 34. For example, when the ith scan line 34 scans the ith row, the ith first thin film transistor 321 and the ith second thin film transistor 322 are turned on, and the first signal line 331 and the second signal line 332 in the ith row are connected; when the (i + 1) th scanning line 34 scans the (i + 1) th row, the (i + 1) th first thin film transistor 321 and the second thin film transistor 322 are turned on, and the first signal line 331 and the second signal line 332 in the (i + 1) th row are communicated; in this way, when only the scan line 34 of the row scans the row, the first tft 321 and the second tft 322 of the row are turned on by the scan line 34, and the first signal line 331 and the second signal line 332 are connected to the bus 21 and provide signals to the pixel circuits 31 of the row. With this arrangement, the first signal line 331 and the second signal line 332 are disconnected from each other without being affected.
Herein, in order to clearly show the connection relationship among the first thin film transistor 321, the second thin film transistor 322, the first signal line 331, the second signal line 332, and the bus connection line 21, the scanning lines 34 corresponding to the light-transmitting region 10 in the first direction X are broken, and actually, the scanning lines 34 on two sides of the light-transmitting region 10 corresponding to the first direction X are electrically connected through the plurality of winding lines located in the frame region 20. In addition, the third signal lines 35 are located on both sides of the frame area 20 in the second direction Y. The third signal line 35 need not bypass the light transmission region 10, and the third signal line 35 extends from one edge to the other edge of the display region 30 in the first direction X. Similarly, the scan lines 34 on both sides of the frame region 20 in the second direction Y do not need to bypass the light-transmitting region 10, and the scan lines 34 extend from one edge of the display region 30 to the other edge in the first direction X.
In some embodiments, the display area 30 has two opposite edges in the first direction X, one of the two edges is a first edge S, and the light-transmitting area 10 and the frame area 20 are disposed near the first edge S of the display area 30. The first edge S may be a left edge or a right edge of the display area 30 in the first direction X. The signal line far from the first edge S of the first signal line 331 and the second signal line 332 is electrically connected to the bus connection line 21 through the thin film transistor, one signal line of the signal lines near the first edge S of the first signal line 331 and the second signal line 332 is directly electrically connected to the bus connection line 21, and the other signal lines extend to the edge of the frame area 20. Compared with the case that the first signal line 331 and the second signal line 332 are electrically connected with the bus connection line 21 through the thin film transistor, one of the first signal line 331 and the second signal line 332 is electrically connected with the bus connection line 21 through the thin film transistor, the mutual disconnection of the first signal line 331 and the second signal line 332 is realized without influence, and meanwhile, the resistance difference caused by the thin film transistor can be reduced, so that the display uniformity is improved.
In some embodiments, as shown in fig. 3 and 4, in the first direction X, the light-transmitting area 10 and the frame area 20 are close to the left edge of the display area 30, i.e., the first edge S is the left edge of the display area 30. At this time, the first signal line 331 is close to the first edge S, any one of the outermost first signal lines 331 in the second direction Y is directly electrically connected to the bus connection line 21, and the other first signal lines 331 extend to the edge of the frame region 20. The second signal line 332 is electrically connected to the bus connection line 21 through the second thin film transistor 322.
Illustratively, as shown in fig. 4, the transparent region 10 is a circular region, and the transparent region 10 is disposed near a first edge of the display region 30. N first signal lines 331 are disposed in the second direction Y, the two outermost first signal lines 331 in the second direction Y are the first and nth, respectively, any one of the two outermost first signal lines 331 may be directly electrically connected to the bus connection line 21, and the other first signal lines 331 are not electrically connected to the bus connection line 21. Further, the first signal line 331 may be electrically connected to a first driving circuit, and the second signal line 332 may be electrically connected to a second driving circuit. The second signal line 332 is electrically connected to the bus connection line 21 through a thin film transistor, and any one of the first signal lines 331 at the outermost side in the second direction Y is directly electrically connected to the bus connection line 21, that is, the second signal lines 332 are electrically connected to the first signal lines 331, that is, the second signal lines 332 are driven bilaterally. In the plurality of first signal lines 331, the other first signal lines 331 except for the one directly electrically connected to the bus connection line 21 have relatively short routing, and the driving load is small, and single-side driving is adopted.
In some embodiments, as shown in fig. 5 and 6, in the first direction X, the light-transmitting area 10 and the frame area 20 are close to the right edge of the display area 30, i.e., the first edge S is the right edge of the display area 30. The second signal lines 332 are disposed near the first edge S, N second signal lines 332 are disposed in the second direction Y, any one of the second signal lines 332 outermost in the second direction Y is directly electrically connected to the bus connection line 21, and the other second signal lines 332 extend to the edge of the frame region 20. For example, the first or nth second signal line 332 in the second direction Y is directly electrically connected to the bus connection line 21. The first signal line 331 is electrically connected to the bus connection line 21 through the first thin film transistor 321.
Illustratively, the transparent region 10 is a circular region, and the transparent region 10 is disposed near a second edge of the display region 30. In the plurality of second signal lines 332 corresponding to the transparent region 10, any one of the two outermost second signal lines 332 may be selected to be directly electrically connected to the bus connection line 21, and the other second signal lines 332 may not be electrically connected to the bus connection line 21. Further, the first signal line 331 may be electrically connected to a first driving circuit, and the second signal line 332 may be electrically connected to a second driving circuit. The first signal line 331 is electrically connected to the bus connection line 21 through a thin film transistor, and any one of the second signal lines 332 at the outermost side in the second direction Y is directly electrically connected to the bus connection line 21, that is, the first signal line 331 is electrically connected to the second signal line 332, that is, the first signal line 331 is driven bilaterally. In the plurality of second signal lines 332, the other second signal lines 332 except for the one signal line directly electrically connected to the bus connection line 21 have relatively short routing, and the driving load is small, and single-side driving is adopted.
In the above example, the first driving circuit and the second driving circuit are located in the non-display area NA. In some embodiments, the first driving circuit and the second driving circuit may be located on left and right sides of the array substrate 100 in the first direction X. In other embodiments, the first driving circuit and the second driving circuit may also be located on the left and right sides of the array substrate 100 in the first direction X, for example, the first driving circuit and the second driving circuit are located on the lower edge of the array substrate 100.
According to the embodiment of the invention, one of the first signal line 331 and the second signal line 332 is selected to be electrically connected to the bus connection line 21 through the thin film transistor based on different positions of the light-transmitting area 10, so that the first signal line 331 and the second signal line 332 are disconnected from each other without influence, and meanwhile, the resistance difference caused by the thin film transistor can be reduced, thereby improving the display uniformity.
In some embodiments, the pixel circuit 31 includes a plurality of thin film transistors. The pixel circuit 31 may be any one of a 7T1C circuit, a 7T2C circuit, or a 9T1C circuit, for example. Herein, the "7T 1C circuit" refers to a pixel circuit including 7 thin film transistors (T) and 1 capacitor (C) in the pixel circuit, and the other "7T 2C circuit", "9T 1C circuit", and the like are analogized. The type of the thin film transistor electrically connecting the bus connection line 21 and the first signal line 331 and/or the second signal line 332 is set to be the same as the type of the thin film transistor in the pixel circuit 31. For example, the types of the first thin film transistor 321, the second thin film transistor 322, and the thin film transistors in the pixel circuit 31 are all P-type thin film transistors or all N-type thin film transistors.
With this arrangement, the first signal line 331 and the second signal line 332 are disconnected from each other without being affected by the disconnection, and the process steps are simplified.
An embodiment of the present invention provides a display panel, including the array substrate according to any one of the above embodiments. Fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 7, the display panel 200 includes the array substrate 100 according to any of the embodiments and the light emitting layer 201 on the array substrate 100. Illustratively, the Light Emitting layer 201 may be an Organic Light Emitting layer, i.e., the display panel 200 may be an Organic Light Emitting Diode (OLED) display panel.
The principle of the display panel to solve the problem is similar to the array substrate, so the implementation of the display panel can be referred to the implementation of the array substrate, and repeated details are not repeated herein.
The embodiment of the present invention further provides a display device, which includes the display panel 200 according to the above embodiment. The display device can be any electronic equipment with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic paper book or a television.
In accordance with the above-described embodiments of the present invention, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. An array substrate is characterized by comprising a light-transmitting area, a frame area surrounding the light-transmitting area and a display area surrounding the frame area;
the display area is provided with a first signal line group and a second signal line group which are used for connecting the pixel circuits, extend along a first direction and are positioned on two sides of the light-transmitting area;
the frame area is provided with a main connecting line extending around the light-transmitting area;
the first signal line group comprises more than one first signal line electrically connected to the main connecting line, and the second signal line group comprises more than one second signal line electrically connected to the main connecting line;
at least a portion of the one or more first signal lines and the one or more second signal lines is electrically connected to the bus connection line through a switching device.
2. The array substrate of claim 1, wherein the switching device comprises a thin film transistor.
3. The array substrate of claim 2, wherein the thin film transistors comprise a first thin film transistor and a second thin film transistor, the first signal line is electrically connected to the bus connection line through the first thin film transistor, and the second signal line is electrically connected to the bus connection line through the second thin film transistor.
4. The array substrate of claim 3, wherein a first end of the first thin film transistor is electrically connected to the first signal line, a second end of the first thin film transistor is electrically connected to the bus connection line, and a control end of the first thin film transistor is electrically connected to the scan lines disposed in the same row as the first signal line;
the first end of the second thin film transistor is electrically connected with the second signal line, the second end of the second thin film transistor is electrically connected with the general connecting line, and the control end of the second thin film transistor is electrically connected with the scanning line arranged in the same row as the second signal line.
5. The array substrate of claim 2, wherein the display area has two opposite edges in the first direction, one of the two edges is a first edge, and the light-transmissive area and the frame area are disposed near the first edge;
the signal line far away from the first edge in the first signal line and the second signal line is electrically connected with the bus connection line through the thin film transistor, one signal line in the signal line close to the first edge in the first signal line and the second signal line is directly and electrically connected with the bus connection line, and other signal lines extend to the edge of the frame area.
6. The array substrate of claim 5, wherein the first signal line is close to the first edge, any one of the outermost first signal lines in the first signal line group in the second direction is directly electrically connected to the bus connection line, and the other first signal lines extend to the edge of the frame region; or, the second signal line is close to the first edge, any one of the second signal lines at the outermost side in the second signal line group is directly electrically connected to the bus connection line in the second direction, and the other second signal lines extend to the edge of the frame region; wherein the second direction intersects the first direction.
7. The array substrate of claim 6, wherein the first signal line is electrically connected to a first driving circuit, and the second signal line is electrically connected to a second driving circuit.
8. The array substrate of any of claims 2-7, wherein the thin film transistors are of the same type as the thin film transistors in the pixel circuits.
9. A display panel comprising the array substrate according to any one of claims 1 to 8.
10. A display device characterized by comprising the display panel according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010115764.0A CN113380830B (en) | 2020-02-25 | 2020-02-25 | Array substrate, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010115764.0A CN113380830B (en) | 2020-02-25 | 2020-02-25 | Array substrate, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113380830A true CN113380830A (en) | 2021-09-10 |
| CN113380830B CN113380830B (en) | 2022-07-12 |
Family
ID=77569162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010115764.0A Active CN113380830B (en) | 2020-02-25 | 2020-02-25 | Array substrate, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113380830B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023226023A1 (en) * | 2022-05-27 | 2023-11-30 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107154218A (en) * | 2017-06-29 | 2017-09-12 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
| CN107203080A (en) * | 2017-07-27 | 2017-09-26 | 厦门天马微电子有限公司 | A kind of array base palte and display panel |
| CN108182886A (en) * | 2018-01-02 | 2018-06-19 | 上海天马微电子有限公司 | Array substrate, display panel and display device |
| CN109541865A (en) * | 2018-12-26 | 2019-03-29 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
-
2020
- 2020-02-25 CN CN202010115764.0A patent/CN113380830B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107154218A (en) * | 2017-06-29 | 2017-09-12 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
| CN107203080A (en) * | 2017-07-27 | 2017-09-26 | 厦门天马微电子有限公司 | A kind of array base palte and display panel |
| CN108182886A (en) * | 2018-01-02 | 2018-06-19 | 上海天马微电子有限公司 | Array substrate, display panel and display device |
| CN109541865A (en) * | 2018-12-26 | 2019-03-29 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023226023A1 (en) * | 2022-05-27 | 2023-11-30 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113380830B (en) | 2022-07-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112117320B (en) | Display panel and display device | |
| CN111785853B (en) | Display panel and display device | |
| CN107863374B (en) | OLED display panel and display device | |
| CN111048005B (en) | Display panel and display device | |
| US20230337492A1 (en) | Array substrate, display panel and display device | |
| CN113160743B (en) | Array substrate, display panel and display device | |
| CN111969027A (en) | Display panel and display device | |
| CN111952343B (en) | Array substrate and display panel | |
| EP4053904B1 (en) | Display substrate and manufacturing method therefor, and display device | |
| EP4068260A1 (en) | Display substrate and display device | |
| CN113410257B (en) | Array substrate, display panel and display device | |
| CN210955904U (en) | Display substrate, display panel and display device | |
| CN112186021A (en) | Display panel and display device | |
| US20230345785A1 (en) | Array substrate, display panel and display device | |
| CN210627870U (en) | Display panel and display device | |
| WO2022001435A1 (en) | Display substrate, and display device | |
| CN113571570A (en) | Display panel and display device | |
| US20230133588A1 (en) | Display panel and display apparatus | |
| US20230402467A1 (en) | Array substrate, display panel and display apparatus | |
| CN114784073A (en) | Display panel and display device | |
| CN110491905A (en) | The manufacturing method of display panel, display device and display panel | |
| CN113380830B (en) | Array substrate, display panel and display device | |
| CN114242759A (en) | Display panel and display device | |
| CN113421896A (en) | Display panel and display device | |
| CN111833811B (en) | Display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |