CN113568866B - DSP processor, system and method for interaction between DSP processor and external slave equipment - Google Patents
DSP processor, system and method for interaction between DSP processor and external slave equipment Download PDFInfo
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Abstract
The invention discloses a DSP processor, a system and a method for interacting with external slave equipment, wherein the DSP processor comprises: the instruction fetching module is used for reading a target assembly program instruction from an instruction memory of the DSP processor, wherein the operation corresponding to the target assembly program instruction is that the DSP processor is used as a main device to perform data interaction with an external slave device, the decoding module is used for decoding the read target assembly program instruction to obtain a decoded instruction, the execution module is used for generating a main interface control signal according to the decoded instruction, the main interface module is used for generating a bus control signal according to the main interface control signal, and the instruction fetching module is also used for receiving information returned by the bus in response to the bus control signal to operate the external device to complete the execution of the target assembly program instruction. The DSP processor has the function of accessing the external slave equipment by the master equipment and has high operation efficiency.
Description
Technical Field
The invention relates to the technical field of DSP processors, in particular to a DSP processor, a system and a method for interaction between the DSP processor and external slave equipment.
Background
In the prior art, a DSP instruction cannot directly access an external device, for example, in an audio application, as shown in fig. 1, a DSP processor needs to obtain audio data in an I2S module, because the DSP processor is a slave device in the system, the DSP processor cannot directly access the I2S module, the DSP processor first initiates an interrupt command to an MCU (micro control unit), and after receiving a terminal of the DSP, the MCU reads audio data from I2S through a bus, and then sends the read I2S data to the DSP through the bus, thereby completing the DSP obtaining the audio data in I2S. The processing mode needs the intervention of the MCU, so that the working efficiency of the MCU can be influenced, and the working efficiency of the DSP processor can also be influenced.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a DSP processor, a system and a method for performing data interaction with an external slave device, so as to improve the processing efficiency of the DSP.
To solve the above technical problems, an aspect of the present invention provides a DSP processor, including:
the instruction fetching module is used for reading a target assembly program instruction from an instruction memory of the DSP processor, wherein the operation corresponding to the target assembly program instruction is that the DSP processor is used as a master device to perform data interaction with an external slave device;
the decoding module is used for decoding the target assembler program instruction to obtain a decoded instruction;
the execution module is used for generating a main interface module control signal according to the decoded instruction;
and the main interface module is used for generating a bus control signal according to the main interface module control signal, wherein the bus control signal is used for controlling the bus to access the external slave device and executing the operation corresponding to the target assembly program instruction, and is also used for receiving information returned by the bus in response to the bus control signal to access the external device and finishing the execution of the target assembly program instruction.
In a specific embodiment, the DSP processor further includes:
a FIFO module for storing the read enable control signal, the write enable control signal, the read address information, the write address information, the data to be written into the external slave device, and the data read from the external slave device in the decoded instruction.
In one embodiment, the FIFO module includes:
the read data FIFO unit is used for caching the data read by the DSP processor from the external slave device;
a write data FIFO unit for caching data to be written into the external slave device by the DSP processor;
and the address FIFO unit is used for caching the read enabling control signal, the write enabling control signal, the read address information and the write address information.
In a specific embodiment, the DSP processor further includes:
and the slave interface module is used for performing information interaction with the bus when the DSP processor is used as a slave device to interact with the external slave device.
A second aspect of the present invention provides a method for data interaction between the DSP processor and an external slave device, where the method includes the following steps:
the instruction fetching module reads a first object assembler program instruction from an instruction memory of the DSP processor, wherein the operation corresponding to the first object assembler program instruction is that the DSP processor is used as a master device to read data in the external slave device;
the decoding module decodes the first target assembler program instruction to obtain a decoded first instruction;
the execution module outputs a first read enabling control signal and first read address information according to the first instruction;
the main interface module outputs a bus first control signal according to the first read enable control signal and the first read address information, wherein the bus first control signal is used for controlling the bus to read first data from the first read address of the external slave device;
the primary interface module receives the first data.
A third aspect of the present invention provides a method for data interaction between the DSP processor and an external slave device, where the method includes the following steps:
the instruction fetching module reads a second object assembler program instruction from an instruction memory of the DSP processor, wherein the operation corresponding to the second object assembler program instruction is that the DSP processor is used as a master device to write second data into the external slave device;
the decoding module decodes the second target assembler program instruction to obtain a decoded second instruction;
the execution module outputs a first write enable control signal, first write address information and second data to be written according to the second instruction;
the master interface module outputs a bus second control signal according to the first write enable control signal, the first write address information and the second data, wherein the bus second control signal is used for controlling the bus to write the second data into a first write address of the external slave device;
and the main interface receives feedback information which is returned by the bus and completes the writing of the second data.
A fourth aspect of the present invention provides a method for data interaction between the DSP processor and an external slave device, including the following steps:
the instruction fetching module reads a third object assembler program instruction from an instruction memory of the DSP processor, wherein the third object assembler program instruction corresponds to an operation that the DSP processor serves as a master device to read third data in the external slave device;
the decoding module decodes the third target assembler program instruction to obtain a decoded third instruction;
the execution module outputs a second read enable control signal and second read address information according to the third instruction;
the FIFO module stores the second read enabling control signal and corresponding second read address information;
the main interface module reads the second read enable control signal and the second read address information from the FIFO module, and generates a bus third control signal according to the second read enable control signal and the second read address information, wherein the bus third control signal is used for controlling the bus to read corresponding third data from the second read address of the external slave device;
the main interface module receives the third data sent by the bus and sends the third data to the FIFO module;
the FIFO module stores the third data.
In a specific embodiment, the method further comprises:
the instruction fetching module reads a fourth object assembly program instruction from an instruction memory of the DSP processor, wherein the operation corresponding to the fourth object assembly program instruction is to read the third data from the FIFO module and write the third data into a general register of the DSP processor;
the decoding module decodes the fourth target assembler program instruction to obtain a decoded fourth instruction;
the execution module outputs a third read enable control signal according to the fourth instruction, and reads the third data from the FIFO module;
saving the third data in a general purpose register of the DSP processor.
A fifth aspect of the present invention provides a method for data interaction between the DSP processor and an external slave device, where the method includes the following steps:
the instruction fetching module reads a fifth object assembler program instruction from an instruction register of the DSP processor, wherein the operation corresponding to the fifth object assembler program instruction is that the DSP processor is used as a main device to write fourth data into the external device;
the decoding module decodes the fifth target assembler program instruction to obtain a decoded fifth instruction;
the execution module outputs a second write enable control signal, second write address information and the fourth data according to the fifth instruction;
the FIFO module stores the second write enable control signal, the second write address information and the fourth data;
the master interface module reads the second write enable control signal, the second write address information and the fourth data from the FIFO module, and generates a bus fourth control signal according to the second write enable control signal, the second write address information and the fourth data, wherein the bus fourth control signal is used for controlling the bus to write the fourth data into a second write address of the external slave device;
and the main interface module also receives feedback information which is sent by the bus and completes the writing of the fourth data.
A sixth aspect of the present invention provides a processing system comprising: a micro control unit, a bus, at least one external slave device and a DSP processor as described above, wherein
The micro control unit, the at least one external slave device and the DSP processor are all in communication with the bus.
The embodiment of the invention has the following beneficial effects: the DSP processor of the embodiment of the invention is integrated with the main interface, and when the DSP processor needs to perform data interaction with other external equipment, the DSP processor can be used as the main equipment to directly access the external slave equipment without interrupt access through the MCU. The DSP processor has the function of accessing the external slave equipment by the master equipment and has high operation efficiency.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is within the scope of the present invention for those skilled in the art to obtain other drawings based on the drawings without inventive exercise.
FIG. 1 shows a schematic diagram of a prior art processing system;
FIG. 2 is a schematic structural diagram of a DSP processor according to a first embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a main interface module according to a first embodiment of the present invention;
FIG. 4 is a diagram showing another structure of a DSP processor according to a first embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a FIFO module according to a first embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating the signal flow of the FIFO module according to the first embodiment of the present invention;
FIG. 7 is a flow chart showing the signal interaction between the DSP processor and the external slave device according to the embodiment of the invention;
FIG. 8 is another flow chart illustrating the interaction of the DSP processor with the external slave device according to an embodiment of the present invention;
FIG. 9 is another flow chart of the DSP processor interacting with the external slave device according to the embodiment of the invention;
fig. 10 is another flow chart of the DSP processor interacting with the external slave device according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
As shown in fig. 2, a schematic structural diagram of a DSP processor according to an embodiment of the present invention is shown, where the DSP processor 10 includes an instruction fetching module 1, a decoding module 2, an execution module 3, and a master interface module 4, where the instruction fetching module 1 is configured to read an object assembler instruction from an instruction memory of the DSP processor 10, where an operation corresponding to the object assembler instruction is that the DSP processor 10 serves as a master device to perform data interaction with an external slave device, the decoding module 2 is configured to decode the read object assembler instruction to obtain a decoded instruction, the execution module 3 is configured to generate a master interface control signal according to the decoded instruction, the master interface module 4 is configured to generate a bus control signal according to the master interface control signal, where the bus control signal is used to control the bus to execute an operation corresponding to the object assembler instruction on the external slave device, the main interface module 4 is further configured to receive information returned by the bus in response to the bus control signal operating the external device, and complete execution of the target assembler instruction.
The instruction operation corresponding to the object assembler may be that the DSP processor serves as a master device to read data of an external slave device, or that the DSP processor serves as a master device to write data to an external slave device.
The main interface module 4 may be an AHB main interface or other types of main interface modules, as shown in fig. 3, where the AHB main interface includes a read enable control signal Ren, a write enable control signal Wen, read address information Raddr, write data Wdata, and the like.
The DSP processor is integrated with the main interface module, when the DSP processor needs to perform data interaction with other external slave devices, the DSP processor can be used as a main device to interact with a bus, the bus interacts with the external slave devices, and interrupt access does not need to be performed through an MCU. The DSP processor has the function of accessing external slave equipment by the master equipment, and has high operation efficiency. When the DSP processor forms a dual-core or multi-core processing system, the DSP processor can be used as a master device to access external slave devices, and an MCU is not needed for interrupt processing, so that the running efficiency of the MCU is improved.
In a specific embodiment, as shown in fig. 4, the DSP processor further includes a FIFO module 5 and a write-back module 6, where the FIFO module 5 is configured to store a read enable control signal, a write enable control signal, read address information, write address information, data to be written into the external slave device, and data read from the external slave device in the decoded instruction.
Referring to fig. 5, in an embodiment, the FIFO module 5 specifically includes: a read data FIFO unit 51, a write data FIFO unit 52 and an address FIFO unit 53, wherein the read data FIFO unit 51 is used for buffering the data read by the DSP processor from the external slave device, the write data FIFO unit 52 is used for buffering the data to be written by the DSP processor into the external slave device, and the address FIFO unit 53 is used for buffering the read enable control signal, the write enable control signal, the read address information and the write address information.
In one embodiment, the read data FIFO element 51, write data FIFO element 52, and address FIFO element 53 are each 8 levels deep.
Referring to fig. 6, a signal flow diagram of the FIFO block is shown. The hready is a response signal sent to the FIFO module by the main interface module, wherein the address signal includes read address information Raddr and write address information Raddr, and Rdata is data read back by the main interface.
The FIFO module is used for caching data to be read or written, so that the defect of resource waste caused by the fact that a plurality of null instructions need to be inserted every time a read instruction or a write instruction is executed in the prior art can be overcome, and the operating efficiency of the DSP processor is further improved.
In a specific embodiment, the DSP processor further comprises a slave interface module for data interaction with the bus when the DSP processor is acting as a slave. The slave interface module is any slave interface module in the prior art.
Based on the first embodiment of the present invention, the second embodiment of the present invention provides a method for data interaction between a DSP processor and an external slave device, as shown in fig. 7, where the method includes the following steps:
and S11, the instruction fetching module reads a first object assembler program instruction from an instruction memory of the DSP processor, wherein the operation corresponding to the first object assembler program instruction is that the DSP processor is used as a master device to read data in the external slave device.
In a specific embodiment, the first object assembler instruction corresponds to an operation that the DSP processor needs to read data in the external slave device, specifically, audio data in the external I2S, or sampling data in the ADC.
And S12, the decoding module is used for decoding the read object assembler program instruction to obtain a decoded first instruction.
And S13, the execution module is used for outputting a first read enable control signal and first read address information according to the decoded first instruction.
Specifically, the execution module outputs a first read enable control signal Ren and first read address information Raddr according to the decoded first instruction.
S14, the master interface module outputs a first bus control signal according to the first read enable control signal and the first read address information, wherein the first bus control signal is used to control the bus to read first data from the first read address of the external slave device.
After the execution module outputs Ren and Raddr signals, the AHB main interface module performs information interaction with a bus, and the main interface outputs a first bus control signal, wherein the first bus control signal comprises: locked bus signal HLOCKx, transition type signal HTRANS [1:0], read address information HADDR [31:0], and so on.
After receiving the bus control signal, the bus interacts with the external slave device, and reads first data from a first read address of the corresponding external slave device.
S15, the main interface module also receives the first data.
After the bus reads first data from a first read address corresponding to the external slave device, the bus performs data interaction with the master interface and sends the read first data to the master interface, and the master interface receives the first data and stores the first data in a register of the master interface.
Based on the first embodiment of the present invention, a third embodiment of the present invention provides a method for data interaction between a DSP processor and an external slave device, as shown in fig. 8, where the method includes the following steps:
and S21, the instruction fetching module is used for reading a first object assembler program instruction from an instruction register of the DSP processor, wherein the operation corresponding to the first object assembler program instruction is that the DSP processor is used as a master device to write data into the external slave device.
Specifically, in one embodiment, the first object assembler instruction writes the first write data into external I2S for the DSP processor as a master.
And S22, the decoding module is used for decoding the read object assembler program instruction to obtain a decoded second instruction.
And S23, the execution module is used for outputting a first write enable control signal, first write address information and second data to be written according to the decoded second instruction.
Specifically, the execution module outputs a first write enable control signal Wen, first write address information Waddr, first write data Wdata.
And S24, the master interface module is used for outputting a bus second control signal according to the first write enable control signal, the first write address information and the second data, and the bus second control signal is used for controlling the bus to write the second data into the corresponding write address of the external slave device.
Specifically, after receiving the first write enable control signal Wen, the first write address information Waddr, and the first write data Wdata, the host interface module generates a second bus control signal, where the second bus control signal at least includes: a locked bus signal HLOCKx, a transition type signal HTRANS [1:0], first write address information HWRITE, HWDATA [31:0], and so forth.
S25, the main interface is also used for receiving feedback information of the second data write completion returned by the bus.
When the bus receives the second bus control signal, the bus performs signal interaction with the external slave device, the first write data is written into the first write address corresponding to the external slave device, and after the first write data is written, the bus sends feedback information of data writing completion to the master interface.
Based on the first embodiment of the present invention, a fourth embodiment of the present invention provides a method for data interaction between a DSP processor and an external slave device, as shown in fig. 9, where the method includes the following steps:
and S31, the instruction fetching module reads a third object assembler program instruction from an instruction register of the DSP processor, wherein the operation corresponding to the first object assembler program instruction is that the DSP processor serves as a master device to read third data in the external slave device.
And S32, the decoding module decodes the read third target assembler program instruction to obtain a decoded fourth instruction.
And S33, the execution module outputs a second read enable control signal and second read address information according to the fourth decoded instruction.
S34, the FIFO module stores the second read enable control signal and the corresponding second read address information.
Specifically, the address FIFO unit of the FIFO module temporarily stores the second read enable control signal and the corresponding second read address information.
S35, the master interface module reads the second read enable control signal and the corresponding second read address information from the FIFO module, and generates a bus third control signal according to the second read enable control signal and the corresponding second read address information, so as to control the bus to read corresponding third data from the read address in the external slave device.
S36, the main interface module also receives the third data sent by the bus and sends the third data to the FIFO module.
And S37, the FIFO module stores the third data.
Specifically, the main interface module sends the third data to the read data FIFO unit for storage.
In a specific embodiment, the method further comprises:
the instruction fetching module reads a fourth object assembler program instruction from an instruction memory of the DSP processor, wherein the operation corresponding to the fourth object assembler program instruction is to read the third data from the FIFO module, the decoding module decodes the fourth object assembler program instruction to obtain a decoded fourth instruction, the execution module outputs a third read enable control signal according to the fourth instruction, reads the third data from the FIFO module, and stores the third data in a general processor of the DSP processor.
Based on the first embodiment of the present invention, a fifth embodiment of the present invention provides a method for data interaction between a DSP processor and an external slave device, as shown in fig. 10, where the method includes the following steps:
and S41, the instruction fetching module reads a fifth object assembly program instruction from an instruction register of the DSP processor, wherein the operation corresponding to the object assembly program instruction is that the DSP processor serves as a main device, and fourth data is written into the external device.
And S42, the decoding module decodes the fifth target assembler program instruction to obtain a decoded fifth instruction.
And S43, the execution module outputs a second write enable control signal, second write address information and the fourth data according to the fifth instruction.
S44, the FIFO module stores the second write enable control signal, the second write address information, and the fourth data.
Specifically, the address FIFO unit of the FIFO module temporarily stores the second write enable control signal and the second write address information, and the write data FIFO unit of the FIFO module temporarily stores the fourth data.
S45, the master interface module reads the second write enable control signal, the second write address information, and the fourth data from the FIFO module, and generates a bus control signal according to the second write enable control signal, the second write address information, and the fourth data, so as to control the bus to write the fourth data into a corresponding second write address of the external slave device.
Specifically, the host interface module reads the second write enable control signal, the second write address information, and the fourth data from the write data FIFO unit.
And S46, the master interface module further receives feedback information sent by the bus and used for finishing the fourth data writing.
Based on the first embodiment of the present invention, a sixth embodiment of the present invention provides a processing system, including: a micro control unit, a bus, at least one external slave device, and the DSP processor according to embodiment one, wherein the micro control unit, the at least one external slave device, and the DSP processor are all in communication with the bus.
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (10)
1. A DSP processor, comprising:
the instruction fetching module is used for reading a target assembly program instruction from an instruction memory of the DSP processor, wherein the operation corresponding to the target assembly program instruction is that the DSP processor is used as a master device to perform data interaction with an external slave device;
the decoding module is used for decoding the target assembler program instruction to obtain a decoded instruction;
the execution module is used for generating a main interface module control signal according to the decoded instruction;
and the main interface module is used for generating a bus control signal according to the main interface module control signal, wherein the bus control signal is used for controlling the bus to access the external slave device and executing the operation corresponding to the target assembly program instruction, and is also used for receiving information returned by the bus in response to the bus control signal to access the external device and finishing the execution of the target assembly program instruction.
2. The DSP processor defined in claim 1 further comprising:
a FIFO module for storing the read enable control signal, the write enable control signal, the read address information, the write address information, the data to be written into the external slave device, and the data read from the external slave device in the decoded instruction.
3. The DSP processor defined in claim 2 wherein the FIFO module comprises:
the read data FIFO unit is used for caching the data read by the DSP processor from the external slave device;
a write data FIFO unit for caching data to be written into the external slave device by the DSP processor;
and the address FIFO unit is used for caching the read enabling control signal, the write enabling control signal, the read address information and the write address information.
4. The DSP processor defined in any one of claims 1-3 further comprising:
and the slave interface module is used for performing information interaction with the bus when the DSP processor is used as a slave device to interact with the external slave device.
5. A method of an external slave device interacting with the DSP processor of claim 1, the method comprising the steps of:
the instruction fetching module reads a first object assembler program instruction from an instruction memory of the DSP processor, wherein the operation corresponding to the first object assembler program instruction is that the DSP processor is used as a master device to read data in the external slave device;
the decoding module decodes the first target assembler program instruction to obtain a decoded first instruction;
the execution module outputs a first read enabling control signal and first read address information according to the first instruction;
the main interface module outputs a bus first control signal according to the first read enable control signal and the first read address information, wherein the bus first control signal is used for controlling the bus to read first data from the first read address of the external slave device;
the primary interface module receives the first data.
6. A method of an external slave device interacting with the DSP processor of claim 1, the method comprising the steps of:
the instruction fetching module reads a second object assembler program instruction from an instruction memory of the DSP processor, wherein the operation corresponding to the second object assembler program instruction is that the DSP processor is used as a master device to write second data into the external slave device;
the decoding module decodes the second target assembler program instruction to obtain a decoded second instruction;
the execution module outputs a first write enable control signal, first write address information and second data to be written according to the second instruction;
the master interface module outputs a bus second control signal according to the first write enable control signal, the first write address information and the second data, wherein the bus second control signal is used for controlling the bus to write the second data into a first write address of the external slave device;
and the main interface receives feedback information which is returned by the bus and completes the writing of the second data.
7. A method of an external slave device interacting with a DSP processor as claimed in claim 2 or 3, comprising the steps of:
the instruction fetching module reads a third object assembler program instruction from an instruction memory of the DSP processor, wherein the third object assembler program instruction corresponds to an operation that the DSP processor serves as a master device to read third data in the external slave device;
the decoding module decodes the third target assembler program instruction to obtain a decoded third instruction;
the execution module outputs a second read enable control signal and second read address information according to the third instruction;
the FIFO module stores the second read enabling control signal and corresponding second read address information;
the main interface module reads the second read enable control signal and the second read address information from the FIFO module, and generates a bus third control signal according to the second read enable control signal and the second read address information, wherein the bus third control signal is used for controlling the bus to read corresponding third data from the second read address of the external slave device;
the main interface module receives the third data sent by the bus and sends the third data to the FIFO module;
the FIFO module stores the third data.
8. The method of claim 7, further comprising:
the instruction fetching module reads a fourth object assembly program instruction from an instruction memory of the DSP processor, wherein the operation corresponding to the fourth object assembly program instruction is to read the third data from the FIFO module and write the third data into a general register of the DSP processor;
the decoding module decodes the fourth target assembler program instruction to obtain a decoded fourth instruction;
the execution module outputs a third read enable control signal according to the fourth instruction, and reads the third data from the FIFO module;
saving the third data in a general purpose register of the DSP processor.
9. A method of an external slave device interacting with a DSP processor as claimed in claim 2 or 3, the method comprising the steps of:
the instruction fetching module reads a fifth object assembler program instruction from an instruction register of the DSP processor, wherein the operation corresponding to the fifth object assembler program instruction is that the DSP processor is used as a main device to write fourth data into the external device;
the decoding module decodes the fifth target assembler program instruction to obtain a decoded fifth instruction;
the execution module outputs a second write enable control signal, second write address information and the fourth data according to the fifth instruction;
the FIFO module stores the second write enable control signal, the second write address information and the fourth data;
the master interface module reads the second write enable control signal, the second write address information and the fourth data from the FIFO module, and generates a bus fourth control signal according to the second write enable control signal, the second write address information and the fourth data, wherein the bus fourth control signal is used for controlling the bus to write the fourth data into a second write address of the external slave device;
and the main interface module also receives feedback information which is sent by the bus and completes the writing of the fourth data.
10. A processing system, comprising: micro control unit, bus, at least one external slave device and DSP processor according to any of claims 1-4, wherein
The micro control unit, the at least one external slave device and the DSP processor are all in communication with the bus.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101135993A (en) * | 2007-09-20 | 2008-03-05 | 华为技术有限公司 | Embedded system chip and data read-write processing method |
| CN103092798A (en) * | 2012-12-28 | 2013-05-08 | 华为技术有限公司 | On-chip system and method for accessing to equipment under bus |
| CN112817897A (en) * | 2021-02-05 | 2021-05-18 | 中国电子科技集团公司第五十八研究所 | Communication method and communication system for interconnecting bare chip and DSP/FPGA |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6738845B1 (en) * | 1999-11-05 | 2004-05-18 | Analog Devices, Inc. | Bus architecture and shared bus arbitration method for a communication device |
| CN103226541A (en) * | 2013-03-29 | 2013-07-31 | 江苏复芯物联网科技有限公司 | Embedded high-performance heterogeneous computing platform based on FPGA and ARM |
-
2021
- 2021-09-23 CN CN202111113524.8A patent/CN113568866B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101135993A (en) * | 2007-09-20 | 2008-03-05 | 华为技术有限公司 | Embedded system chip and data read-write processing method |
| CN103092798A (en) * | 2012-12-28 | 2013-05-08 | 华为技术有限公司 | On-chip system and method for accessing to equipment under bus |
| CN112817897A (en) * | 2021-02-05 | 2021-05-18 | 中国电子科技集团公司第五十八研究所 | Communication method and communication system for interconnecting bare chip and DSP/FPGA |
Non-Patent Citations (1)
| Title |
|---|
| 基于DSP与TLV320AIC23B的音频处理系统;黎泽清等;《自动化与仪表》;20090815(第08期);全文 * |
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