CN113568390B - DCS (distributed control system) dynamic layered communication method and system based on multi-level processor - Google Patents
DCS (distributed control system) dynamic layered communication method and system based on multi-level processor Download PDFInfo
- Publication number
- CN113568390B CN113568390B CN202111104165.XA CN202111104165A CN113568390B CN 113568390 B CN113568390 B CN 113568390B CN 202111104165 A CN202111104165 A CN 202111104165A CN 113568390 B CN113568390 B CN 113568390B
- Authority
- CN
- China
- Prior art keywords
- processor
- performance index
- processors
- performance
- difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004891 communication Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 30
- 230000003993 interaction Effects 0.000 claims abstract description 29
- 238000012545 processing Methods 0.000 abstract description 33
- 230000009467 reduction Effects 0.000 abstract description 8
- 230000008569 process Effects 0.000 description 8
- 230000002452 interceptive effect Effects 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
- G05B19/41865—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by job scheduling, process planning, material flow
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/33—Director till display
- G05B2219/33273—DCS distributed, decentralised controlsystem, multiprocessor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Hardware Redundancy (AREA)
Abstract
The invention discloses a DCS dynamic layered communication method and a DCS dynamic layered communication system based on a multi-stage processor, which comprises the following steps: acquiring performance indexes of a plurality of processors in a multi-stage processor; acquiring a performance index difference d; and when the performance index difference D is greater than or equal to the threshold D, the processor with high performance index executes at least one function of the processor with low performance index according to the level priority in the two processors with corresponding service interaction, and the processor with low performance index stops executing the corresponding function. The invention aims to provide a DCS dynamic layered communication method and a DCS dynamic layered communication system based on a multi-stage processor, by the method, the multi-stage processor in each node of the DCS judges according to the processing performance index of the adjacent processor, dynamically adjusts the communication task born by each processor, and effectively solves the problem of communication quality reduction caused by performance reduction of a single processor.
Description
Technical Field
The invention relates to the technical field of safety-level digital control of a nuclear power plant, in particular to a DCS (distributed control system) dynamic layered communication method and system based on a multi-level processor.
Background
A nuclear power plant dedicated safety level instrument control system (DCS) provides monitoring of deviation of a nuclear power plant from a normal operation condition, and simultaneously drives corresponding safety functions to enable the power plant to be safely shut down and maintain a safe state, so that safety of a reactor, nuclear power plant equipment, personnel and the environment under an accident condition is guaranteed.
The reactor working condition detection devices in the nuclear power plants are various, and a reactor distributed control system needs to detect all operation parameters and report the operation parameters at any time, so that the communication data volume in and among stations of the system is large. The function card is used as a function unit with minimum signal processing and is also a unit with the most intensive data use in the DCS. Most node cards are currently designed based on multi-level processor architectures, such as dual-core, three-core, and even four-core architectures. In such a multi-chip architecture, there is usually a definite division of tasks between the processing cores, and the data processing also has an obvious hierarchical structure, for example, the upper processor undertakes the functions of signal analysis, data generation and operation, the lower processor undertakes the function of data processing, and the lower processor takes charge of the function of data transmission of the lower layer. Such a multi-level architecture helps to improve the overall performance of a single functional node, but has a problem of reducing the efficiency of interactive communication of the overall node due to the increase of single processor burst tasks.
Disclosure of Invention
The invention aims to provide a DCS dynamic layered communication method and a DCS dynamic layered communication system based on a multi-stage processor, by the method, the multi-stage processor in each node of the DCS judges according to the processing performance index of the adjacent processor, dynamically adjusts the communication task born by each processor, and effectively solves the problem of communication quality reduction caused by performance reduction of a single processor.
The invention is realized by the following technical scheme:
the DCS system dynamic layered communication method based on the multi-level processor comprises the following steps:
acquiring performance indexes of a plurality of processors in a multi-stage processor;
acquiring a performance index difference d, wherein the performance index difference d is the difference between the performance indexes of any two processors with service interaction;
and when the performance index difference D is greater than or equal to the threshold value D, the processor with high performance index executes at least one function of the processor with low performance index according to the level priority in the network model in the two processors with corresponding service interaction, and the processor with low performance index stops executing the corresponding function.
In a multi-level processor architecture, there is usually a definite division of tasks between processing cores, and data processing also has an obvious hierarchical structure, for example, an upper-level processor undertakes signal analysis, data generation and operation functions, a lower-level processor undertakes data processing functions, a lower-level processor undertakes data transmission functions, and the like. But there is a problem in that the efficiency of interactive communication of the entire node is reduced due to an increase in single processor burst tasks. Based on this, the present application provides a DCS system dynamic hierarchical communication method based on multiple processors, by increasing interaction of processing performance state information between processors with service interaction, when the processing performance of one processor (for convenience of subsequent description, hereinafter referred to as processor 1) is reduced and more processor resources are still available in the other processor (for convenience of subsequent description, hereinafter referred to as processor 2), the processor 2 instead processes some data in the processor 1 or instead implements some functions of the processor 1, so that the processor 1 can release more resources to other tasks, and the reduction of the interactive communication efficiency of the whole node due to the reduction of the processing performance of the processor 1 is avoided.
Preferably, the obtaining of the performance index of the processor comprises the following steps:
the processor executes the test program once every time period T;
recording the execution time of the processor after the test program is executed;
and acquiring the performance index of the processor from a performance index table according to the execution time.
Preferably, the performance index table includes a plurality of performance index values, and any one of the performance index values corresponds to an execution time range.
Preferably, the step of obtaining the performance index difference d comprises the following steps:
judging whether any two processors have service interaction;
and when service interaction exists between the two processors, calculating the performance index difference of the two processors, and solving an absolute value to obtain the performance index difference d.
Preferably, the processor with high performance level executes at least one function of the processor with low performance level according to the hierarchy priority in the network model, and the method comprises the following steps:
step 1: acquiring the hierarchy priority relation in the processor with low performance index;
step 2: closing the function corresponding to the highest level priority of the processor with low performance index, and simultaneously opening the corresponding function in the processor with high performance index;
and step 3: acquiring a performance index difference d of the processor with low performance index and the processor with high performance index;
and 4, step 4: and when the performance index difference D is larger than or equal to the threshold value D, repeating the steps 1-3.
The DCS dynamic layered communication system based on the multi-level processor comprises a first acquisition module, a second acquisition module and a control module;
the first obtaining module is used for obtaining the performance indexes of a plurality of processors in the multi-stage processor;
the second obtaining module is configured to obtain a performance index difference d, where the performance index difference d is a difference between performance indexes of any two processors with service interaction;
and the control module is used for controlling the processor with high performance index to execute at least one function of the processor with low performance index according to the level priority in the network model in the two processors corresponding to the service interaction when the performance index difference D is greater than or equal to the threshold D, and stopping executing the corresponding function by the processor with low performance index.
Preferably, the first obtaining module comprises an executing unit, a recording unit, a obtaining unit and a storing unit;
the storage unit is used for storing a test program and a performance index table;
the execution unit is used for controlling the processor to execute the test program once every time period T;
the recording unit is used for recording the execution time of the test program executed by the processor;
the obtaining unit is configured to obtain the performance index of the processor from the performance index table according to the execution time.
Preferably, the performance index table includes a plurality of performance index values, and any one of the performance index values corresponds to an execution time range.
Preferably, the second acquiring module comprises a judging unit and a calculating unit;
the judging unit is used for judging whether service interaction exists between any two processors;
and the calculating unit is used for calculating the performance index difference of the two processors when service interaction exists between the two processors, and calculating an absolute value to obtain the performance index difference d.
Preferably, the control module comprises a judging subunit, an acquiring subunit, a controlling subunit and a circulation judging unit;
the judging subunit is configured to judge whether the performance index difference D is greater than or equal to a threshold D;
the obtaining subunit is configured to obtain, when the performance indicator difference D is greater than or equal to a threshold D, a hierarchical priority relationship in the processor with a low performance indicator;
the control subunit is configured to close a function corresponding to the highest level priority of the processor with a low performance index, and simultaneously open a corresponding function in the processor with a high performance index;
the loop judgment unit is configured to obtain a performance index difference D between the processor with a low performance index and the processor with a high performance index, and return to the obtaining subunit when the performance index difference D is greater than or equal to a threshold D.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the data processing and transmission are carried out by adopting the cooperative work of the multi-level processors, namely, a protocol layer for dynamically distributing communication among the multi-level processors can effectively relieve the problem of the reduction of the overall communication quality caused by the performance reduction of a single processor in the nodes of the multi-level processor architecture.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic diagram of a default communication hierarchy in a two-stage processor architecture node according to the present invention;
FIG. 2 is a communication hierarchy diagram of the upper processor performance degradation case of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example 1
The embodiment provides a DCS dynamic layered communication method based on a multi-stage processor, which comprises the following steps:
acquiring performance indexes of a plurality of processors in a multi-stage processor;
the method for acquiring the performance index of the single processor comprises the following steps: and periodically enabling the processor to execute a same test program, recording the time for completing the program execution, and acquiring the performance index of the processor from the performance index table according to the execution time. Since the time for the processor to execute the test program is affected by the resource usage rate, power consumption, temperature, and the like of the processor, the processing performance of the pre-processor can be reflected by the execution time.
The performance index table described in this embodiment includes a plurality of performance index values, and any one of the performance index values corresponds to an execution time range. For example, a performance index value is 90, the corresponding execution time range is 0.01s-0.1s, and when the execution time of a processor falls within the range of 0.01s-0.1s, the performance index value of the processor is 90.
Acquiring a performance index difference d, wherein the performance index difference d is the difference between the performance indexes of any two processors with service interaction;
specifically, the method comprises the following steps:
judging whether any two processors have service interaction or not;
and when the two processors have service interaction, calculating the performance index difference of the two processors, and solving the absolute value to obtain the performance index difference d.
The principle of the scheme is as follows:
when the processing performance of the processor 1 is reduced and the processor 2 still has more processor resources available, the processor 2 instead processes some data in the processor 1 or instead implements some functions of the processor 1, so that the processor 1 can release more resources to other tasks, since the processor 2 instead processes some data or functions and the processing result may be used as an input of other processing parts of the processor 1, the processor 2 needs to feed back the processing result to the processor 1 after processing the corresponding data or function, so that there must be business interaction between the processor 1 and the processor 2, otherwise, the processor 2 cannot feed back the processing result to the processor 1.
When the performance index difference D is greater than or equal to the threshold value D, the processor with high performance index executes at least one function of the processor with low performance index according to the level priority in the network model in the two processors with corresponding service interaction, and the processor with low performance index stops executing the corresponding function;
specifically, the method comprises the following steps:
step 1: acquiring a hierarchy priority relation in a processor with low performance index;
in this embodiment, the hierarchical priority relationship in the processor with low performance index refers to: the processor with low performance index has the priority relation of the used layers, for example, the processor with low performance index has a transmission layer, a network layer, a link layer and a physical layer at the same time, but only uses the network layer and the link layer, if the priority of the link layer is higher than that of the network layer, the link layer is processed preferentially; as a preferred implementation, the priorities of the embodiment are distributed from high to low to a physical layer, a data link layer, a network layer, a transport layer, a session layer, a presentation layer and an application layer.
Step 2: closing the function corresponding to the highest level priority of the processor with low performance index, and simultaneously opening the corresponding function in the processor with high performance index; therefore, the processor with high performance index can be replaced by the processor with low performance index to execute partial functions of the processor;
and step 3: acquiring a performance index difference d of a processor with low performance index and a processor with high performance index;
and 4, step 4: and when the performance index difference D is larger than or equal to the threshold value D, repeating the steps 1-3.
In this embodiment, when determining whether the processor 2 needs to execute a part of the functions of the processor 1 instead, the performance of the single processor is not compared with the threshold value alone, and the switching is performed when the performance is greater than the threshold value. But by comparing the difference in performance of the two processors to a threshold and switching when greater than the threshold. Because in the specific use process, the performance indexes of the processor 1 and the processor 2 both exceed the threshold, and the processor 1 exceeds the threshold more and the processor 2 exceeds the threshold less, if a method of comparing the performance of a single processor with the threshold and switching when the performance of the single processor is greater than the threshold is adopted, the processor 1 and the processor 2 cannot be switched, and because the processing performance of the processor 1 is extremely low at this time, the interactive communication efficiency of the whole node is seriously reduced; if the technical solution provided by the present application is adopted, although the performance indexes of the two processors exceed the threshold, the performance index difference D of the two processors may be greater than the threshold D, and therefore, switching between the processors may be performed, so as to reduce the load of the processor 1 and improve the processing efficiency of the processor 1.
Example 2
The embodiment provides a DCS (distributed control system) dynamic layered communication system based on a multi-level processor, which comprises a first acquisition module, a second acquisition module and a control module;
the system comprises a first acquisition module, a second acquisition module and a third acquisition module, wherein the first acquisition module is used for acquiring the performance indexes of a plurality of processors in the multi-stage processor;
specifically, the first obtaining module in this embodiment includes an executing unit, a recording unit, an obtaining unit, and a storing unit;
the storage unit is used for storing the test program and the performance index table;
the execution unit is used for controlling the processor to execute the test program once every time period T;
the recording unit is used for recording the execution time of the processor for executing the test program;
the acquisition unit is used for acquiring the performance index of the processor from the performance index table according to the execution time;
the performance index table comprises a plurality of performance index values, and any one performance index value corresponds to an execution time range.
Since the time for the processor to execute the test program is affected by the resource usage rate, power consumption, temperature, and the like of the processor, the processing performance of the pre-processor can be reflected by the execution time. In addition, the performance index table described in this embodiment includes a plurality of performance index values, and any one of the performance index values corresponds to one execution time range. For example, a performance index value is 90, the corresponding execution time range is 0.01s-0.1s, and when the execution time of a processor falls within the range of 0.01s-0.1s, the performance index value of the processor is 90.
The second obtaining module is used for obtaining a performance index difference value d, wherein the performance index difference value d is the difference between the performance indexes of any two processors with service interaction;
specifically, the second obtaining module in this embodiment includes a determining unit and a calculating unit;
the judging unit is used for judging whether any two processors have service interaction or not;
and the computing unit is used for computing the performance index difference of the two processors when service interaction exists between the two processors, and solving the absolute value to obtain the performance index difference d.
The principle of the scheme is as follows:
when the processing performance of the processor 1 is reduced and the processor 2 still has more processor resources available, the processor 2 instead processes some data in the processor 1 or instead implements some functions of the processor 1, so that the processor 1 can release more resources to other tasks, since the processor 2 instead processes some data or functions and the processing result may be used as an input of other processing parts of the processor 1, the processor 2 needs to feed back the processing result to the processor 1 after processing the corresponding data or function, so that there must be business interaction between the processor 1 and the processor 2, otherwise, the processor 2 cannot feed back the processing result to the processor 1.
And the control module is used for controlling the processor with high performance index to execute at least one function of the processor with low performance index according to the hierarchical priority in the network model in the two processors corresponding to the service interaction when the performance index difference D is greater than or equal to the threshold D, and the processor with low performance index stops executing the corresponding function.
Specifically, the control module in this embodiment includes a judgment subunit, an acquisition subunit, a control subunit, and a loop judgment unit;
a judging subunit, configured to judge whether the performance index difference D is greater than or equal to a threshold D;
an obtaining subunit, configured to obtain a hierarchical priority relationship in a processor with a low performance index when the performance index difference D is greater than or equal to the threshold D;
the control subunit is used for closing the function corresponding to the highest level priority of the processor with low performance index and simultaneously starting the corresponding function in the processor with high performance index;
and the circulation judging unit is used for acquiring the performance index difference D of the processor with low performance index and the processor with high performance index, and returning to the acquiring subunit when the performance index difference D is greater than or equal to the threshold D.
In this embodiment, when determining whether the processor 2 needs to execute a part of the functions of the processor 1 instead, the performance of the single processor is not compared with the threshold value alone, and the switching is performed when the performance is greater than the threshold value. But by comparing the difference in performance of the two processors to a threshold and switching when greater than the threshold. Because in the specific use process, the performance indexes of the processor 1 and the processor 2 both exceed the threshold, and the processor 1 exceeds the threshold more and the processor 2 exceeds the threshold less, if a method of comparing the performance of a single processor with the threshold and switching when the performance of the single processor is greater than the threshold is adopted, the processor 1 and the processor 2 cannot be switched, and because the processing performance of the processor 1 is extremely low at this time, the interactive communication efficiency of the whole node is seriously reduced; if the technical solution provided by the present application is adopted, although the performance indexes of the two processors exceed the threshold, the performance index difference D of the two processors may be greater than the threshold D, and therefore, switching between the processors may be performed, so as to reduce the load of the processor 1 and improve the processing efficiency of the processor 1.
For ease of understanding, the present solution is further described below:
in the general communication protocol hierarchy, there are a physical layer, a data link layer, a check layer and an application layer from bottom to top. The node card design is implemented by using a two-stage processor architecture, the lower-stage processor defaults to run a data link layer protocol function, and the upper-stage processor defaults to run a check layer and an application layer protocol function, as shown in fig. 1.
In the using process, a performance index difference d between the upper layer processor and the lower layer processor is calculated and compared with a threshold, when the processing performance of the upper layer processor is found to be reduced and the lower layer processor still has more processor resources to use, because the hierarchical priority of the check layer is greater than that of the application layer, the lower layer processor immediately starts the check layer function module and simultaneously informs the upper layer processor to stop the check layer function, so that the upper layer processor can release more resources to other tasks, and the situation that the processing performance of the upper layer processor is reduced due to the increase of burst tasks, and the application layer and the check layer function are affected and the communication quality is further reduced is avoided, as shown in fig. 2. The performance index difference d and the threshold value are continuously monitored, and when the performance index difference d is smaller than the threshold value, the original state, that is, the state shown in fig. 1, is recovered.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. The DCS system dynamic layered communication method based on the multi-level processor is characterized by comprising the following steps:
acquiring performance indexes of a plurality of processors in a multi-stage processor;
acquiring a performance index difference d, wherein the performance index difference d is the difference between the performance indexes of any two processors with service interaction;
when the performance index difference D is greater than or equal to the threshold value D, the processor with high performance index executes at least one function of the processor with low performance index according to the level priority in the network model in the two processors with corresponding service interaction, and the processor with low performance index stops executing the corresponding function;
the processor with high performance index executes at least one function of the processor with low performance index according to the hierarchy priority in the network model, and the method comprises the following steps:
step 1: acquiring the hierarchy priority relation in the processor with low performance index;
step 2: closing the function corresponding to the highest level priority of the processor with low performance index, and simultaneously opening the corresponding function in the processor with high performance index;
and step 3: acquiring a performance index difference d of the processor with low performance index and the processor with high performance index;
and 4, step 4: and when the performance index difference D is larger than or equal to the threshold value D, repeating the steps 1-3.
2. The method of claim 1, wherein obtaining the performance indicator of the processor comprises:
the processor executes the test program once every time period T;
recording the execution time of the processor after the test program is executed;
and acquiring the performance index of the processor from a performance index table according to the execution time.
3. The method of claim 2, wherein the performance indicator table comprises a plurality of performance indicator values, and any one of the performance indicator values corresponds to an execution time range.
4. The method of claim 1, wherein obtaining the performance indicator difference d comprises:
judging whether any two processors have service interaction;
and when service interaction exists between the two processors, calculating the performance index difference of the two processors, and solving an absolute value to obtain the performance index difference d.
5. The DCS dynamic hierarchical communication system based on the multi-level processor is characterized by comprising a first acquisition module, a second acquisition module and a control module;
the first obtaining module is used for obtaining the performance indexes of a plurality of processors in the multi-stage processor;
the second obtaining module is configured to obtain a performance index difference d, where the performance index difference d is a difference between performance indexes of any two processors with service interaction;
the control module is used for controlling the processor with high performance index to execute at least one function of the processor with low performance index according to the level priority in the network model in the two processors corresponding to the service interaction when the performance index difference D is greater than or equal to the threshold value D, and the processor with low performance index stops executing the corresponding function;
the control module comprises a judging subunit, an acquiring subunit, a control subunit and a circulating judging unit;
the judging subunit is configured to judge whether the performance index difference D is greater than or equal to a threshold D;
the obtaining subunit is configured to obtain, when the performance indicator difference D is greater than or equal to a threshold D, a hierarchical priority relationship in the processor with a low performance indicator;
the control subunit is configured to close a function corresponding to the highest level priority of the processor with a low performance index, and simultaneously open a corresponding function in the processor with a high performance index;
the loop judgment unit is configured to obtain a performance index difference D between the processor with a low performance index and the processor with a high performance index, and return to the obtaining subunit when the performance index difference D is greater than or equal to a threshold D.
6. The multi-processor based DCS system dynamic hierarchical communication system according to claim 5, wherein said first obtaining module comprises an executing unit, a recording unit, an obtaining unit and a storing unit;
the storage unit is used for storing a test program and a performance index table;
the execution unit is used for controlling the processor to execute the test program once every time period T;
the recording unit is used for recording the execution time of the test program executed by the processor;
the obtaining unit is configured to obtain the performance index of the processor from the performance index table according to the execution time.
7. The multi-processor based DCS system dynamic hierarchical communication system of claim 6, wherein said performance index table comprises a plurality of performance index values, and any one performance index value corresponds to an execution time range.
8. The multi-processor based DCS system dynamic hierarchical communication system according to claim 5, wherein said second obtaining module comprises a judging unit and a calculating unit;
the judging unit is used for judging whether service interaction exists between any two processors;
and the calculating unit is used for calculating the performance index difference of the two processors when service interaction exists between the two processors, and calculating an absolute value to obtain the performance index difference d.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111104165.XA CN113568390B (en) | 2021-09-22 | 2021-09-22 | DCS (distributed control system) dynamic layered communication method and system based on multi-level processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111104165.XA CN113568390B (en) | 2021-09-22 | 2021-09-22 | DCS (distributed control system) dynamic layered communication method and system based on multi-level processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113568390A CN113568390A (en) | 2021-10-29 |
| CN113568390B true CN113568390B (en) | 2021-12-14 |
Family
ID=78173877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111104165.XA Active CN113568390B (en) | 2021-09-22 | 2021-09-22 | DCS (distributed control system) dynamic layered communication method and system based on multi-level processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113568390B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101101576A (en) * | 2006-07-06 | 2008-01-09 | 李涛 | Vehicle mounted multifunctional information processor |
| CN105867883A (en) * | 2011-03-11 | 2016-08-17 | 英特尔公司 | Dynamic core selection for heterogeneous multi-core systems |
| CN106155876A (en) * | 2016-07-26 | 2016-11-23 | 北京蓝海讯通科技股份有限公司 | A kind of canary analyzes method, application and computing device |
| CN106255228A (en) * | 2016-04-27 | 2016-12-21 | 北京智谷睿拓技术服务有限公司 | A kind of method, terminal unit and node device setting up network connection |
| CN106776250A (en) * | 2016-11-29 | 2017-05-31 | 中国电子产品可靠性与环境试验研究所 | Individual event alternating-current parameter altitude touch method of evaluating performance and the device of FPGA device |
| CN108170525A (en) * | 2016-12-07 | 2018-06-15 | 晨星半导体股份有限公司 | The device and method of the task load configuration of dynamic adjustment multi-core processor |
| CN110398921A (en) * | 2019-07-24 | 2019-11-01 | 理工雷科电子(西安)有限公司 | A kind of multitask dynamic restructuring processing system and method based on FPGA control |
| CN112333147A (en) * | 2020-09-30 | 2021-02-05 | 中国核动力研究设计院 | Nuclear power plant DCS platform network operation situation sensing method and system |
| CN112667450A (en) * | 2021-01-07 | 2021-04-16 | 浙江大学 | Dynamically configurable fault-tolerant system with multi-core processor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1324420C (en) * | 2001-03-01 | 2007-07-04 | 费舍-柔斯芒特系统股份有限公司 | Data sharing in process plant |
| CN104407996B (en) * | 2014-11-05 | 2017-06-30 | 广西科技大学鹿山学院 | The unequal dual port RAM read-write of data-bus width and arbitration controller |
| US11036146B2 (en) * | 2015-10-19 | 2021-06-15 | Asml Netherlands B. V. | Method and apparatus to reduce effects of nonlinear behavior |
| US10372148B2 (en) * | 2016-11-16 | 2019-08-06 | University Of Tennessee Research Foundation | Power system disturbance location determination based on rate of change of frequency |
-
2021
- 2021-09-22 CN CN202111104165.XA patent/CN113568390B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101101576A (en) * | 2006-07-06 | 2008-01-09 | 李涛 | Vehicle mounted multifunctional information processor |
| CN105867883A (en) * | 2011-03-11 | 2016-08-17 | 英特尔公司 | Dynamic core selection for heterogeneous multi-core systems |
| CN109960398A (en) * | 2011-03-11 | 2019-07-02 | 英特尔公司 | The dynamic core selection of system is felt concerned about for heterogeneous polynuclear |
| CN106255228A (en) * | 2016-04-27 | 2016-12-21 | 北京智谷睿拓技术服务有限公司 | A kind of method, terminal unit and node device setting up network connection |
| CN106155876A (en) * | 2016-07-26 | 2016-11-23 | 北京蓝海讯通科技股份有限公司 | A kind of canary analyzes method, application and computing device |
| CN106776250A (en) * | 2016-11-29 | 2017-05-31 | 中国电子产品可靠性与环境试验研究所 | Individual event alternating-current parameter altitude touch method of evaluating performance and the device of FPGA device |
| CN108170525A (en) * | 2016-12-07 | 2018-06-15 | 晨星半导体股份有限公司 | The device and method of the task load configuration of dynamic adjustment multi-core processor |
| CN110398921A (en) * | 2019-07-24 | 2019-11-01 | 理工雷科电子(西安)有限公司 | A kind of multitask dynamic restructuring processing system and method based on FPGA control |
| CN112333147A (en) * | 2020-09-30 | 2021-02-05 | 中国核动力研究设计院 | Nuclear power plant DCS platform network operation situation sensing method and system |
| CN112667450A (en) * | 2021-01-07 | 2021-04-16 | 浙江大学 | Dynamically configurable fault-tolerant system with multi-core processor |
Non-Patent Citations (1)
| Title |
|---|
| 多核处理器核间互连的新型互连网络;乔保军, 石峰, 计卫星.;《北京理工大学学报》;20071231;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113568390A (en) | 2021-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102402395B (en) | Quorum disk-based non-interrupted operation method for high availability system | |
| KR101298558B1 (en) | Method and system for switching main/standby boards | |
| CN111209110B (en) | Task scheduling management method, system and storage medium for realizing load balancing | |
| US20100186019A1 (en) | Dynamic resource adjustment for a distributed process on a multi-node computer system | |
| US8675805B2 (en) | Automated periodic surveillance testing method and apparatus in digital reactor protection system | |
| CN112068957B (en) | Resource allocation method, device, computer equipment and storage medium | |
| CN101021742A (en) | Method and system for throttle management for blade system | |
| CN106293893A (en) | job scheduling method, device and distributed system | |
| CN104780220A (en) | Intelligent monitoring system and method for large distributed system oriented to security futures industry | |
| CN116755939B (en) | Intelligent data backup task planning method and system based on system resources | |
| CN110399034A (en) | A kind of power consumption optimization method and terminal of SoC system | |
| US20230409391A1 (en) | Thread priority adjusting method, terminal, and computer-readable storage medium | |
| CN113568390B (en) | DCS (distributed control system) dynamic layered communication method and system based on multi-level processor | |
| CN113918383A (en) | Core board resetting method, device, equipment, storage medium and program product | |
| CN110661652B (en) | Internet equipment connection and data forwarding processing method | |
| CN114237990B (en) | Method and device for switching square redundancy based on FPGA chip | |
| CN112083646A (en) | Redundancy control method, device and control system | |
| CN104199768A (en) | Multi-core processor setting method and device | |
| CN116302580A (en) | Method and device for scheduling calculation force resources of nano relay | |
| CN108595367B (en) | Server system based on computer cluster in local area network | |
| CN107678853A (en) | The dispatching method and device of graphics processing tasks | |
| CN113190183B (en) | Storage cluster device and equipment mounting method | |
| CN108279973B (en) | Information statistical method and device and electronic equipment | |
| CN115391019B (en) | Data acquisition method and device, readable storage medium and chip | |
| CN112799809B (en) | Cache coloring-based hybrid critical real-time system for resource sharing and isolation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |