CN113556125B - Method, system, electronic equipment and medium for improving AD conversion efficiency - Google Patents
Method, system, electronic equipment and medium for improving AD conversion efficiency Download PDFInfo
- Publication number
- CN113556125B CN113556125B CN202110721305.1A CN202110721305A CN113556125B CN 113556125 B CN113556125 B CN 113556125B CN 202110721305 A CN202110721305 A CN 202110721305A CN 113556125 B CN113556125 B CN 113556125B
- Authority
- CN
- China
- Prior art keywords
- conversion
- channels
- processor
- interval time
- improving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 187
- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000012545 processing Methods 0.000 claims abstract description 17
- 238000004590 computer program Methods 0.000 claims description 9
- 238000013480 data collection Methods 0.000 claims 1
- 229920005994 diacetyl cellulose Polymers 0.000 description 12
- 238000004891 communication Methods 0.000 description 9
- 230000008901 benefit Effects 0.000 description 6
- 238000012544 monitoring process Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000000802 evaporation-induced self-assembly Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
Abstract
The application discloses a method, a system, electronic equipment and a medium for improving AD conversion efficiency, wherein the document information summarizing method comprises the following steps: a data initialization step: respectively initializing AD conversion chips by a processor; AD conversion starting step: the processor starts AD conversion of a plurality of channels according to AD conversion preset interval time; the data acquisition step, namely acquiring AD conversion results of a plurality of channels after the processor monitors the AD conversion completion marks of the channels; and a data processing step: the processor controls the AD conversion interval time of the channels within the AD conversion preset interval time according to the AD conversion result. The invention uses the AD of the multiple channels to connect with the single-channel analog data through the analog-to-digital conversion module, and uses the method for increasing the AD conversion channels and improving the conversion speed through program control on the premise of not reducing the conversion precision.
Description
Technical Field
The application relates to the technical field of analog-to-digital conversion of electronic scales, in particular to a method, a system, electronic equipment and a medium for improving AD conversion efficiency.
Background
Many electronic scales in the market all use an analog-to-digital conversion module, and the analog-to-digital conversion module uses a single AD channel to connect single-channel analog data, so that the AD conversion efficiency in the mode depends on the conversion efficiency of an AD chip, and the speed is required to be improved for the same AD chip, and the conversion precision can be only reduced. Therefore, the prior art cannot improve the AD conversion efficiency without reducing the AD conversion accuracy.
Disclosure of Invention
The embodiment of the application provides a method, a system, electronic equipment and a medium for improving AD conversion efficiency, so that the problems that AD conversion accuracy is reduced in the AD conversion process to improve the AD conversion efficiency and the like are solved at least through the method, the system, the electronic equipment and the medium.
The invention provides a method for improving AD conversion efficiency, which comprises the following steps:
a data initialization step: respectively initializing AD conversion chips by a processor;
AD conversion starting step: the processor starts AD conversion of a plurality of channels according to AD conversion preset interval time;
the data acquisition step, namely acquiring AD conversion results of a plurality of channels after the processor monitors the AD conversion completion marks of the channels;
and a data processing step: the processor controls the AD conversion interval time of the channels within the AD conversion preset interval time according to the AD conversion result.
In the above method for improving AD conversion efficiency, the data initializing step includes the processor initializing AD conversion chips of the plurality of channels, respectively.
In the method for improving AD conversion efficiency, the data collecting step includes that the processor collects the AD conversion results of the channels according to the time sequence of the preset interval time after monitoring the AD conversion completion flags of the channels.
In the above method for improving AD conversion efficiency, the data processing step includes that after the AD conversion result is transferred to a buffer queue of the processor, the processor controls the AD conversion intervals of the channels within the AD conversion preset interval time through software according to the AD conversion result.
The invention also provides a system for improving the AD conversion efficiency, which is suitable for the method for improving the AD conversion efficiency, and comprises the following steps:
a data initializing unit: respectively initializing AD conversion chips by a processor;
AD conversion starting unit: the processor starts AD conversion of a plurality of channels according to AD conversion preset interval time;
the data acquisition unit acquires AD conversion results of a plurality of channels after the processor monitors AD conversion completion marks of the channels;
a data processing unit: the processor controls the AD conversion interval time of the channels within the AD conversion preset interval time according to the AD conversion result.
In the system for improving AD conversion efficiency, the processor in the data initializing unit initializes the AD conversion chips of the plurality of channels, respectively.
In the system for improving the AD conversion efficiency, the processor monitors the AD conversion completion flags of the plurality of channels, and then acquires the AD conversion results of the plurality of channels through the data acquisition unit according to the time sequence of the preset interval time.
In the system for improving the AD conversion efficiency, after the AD conversion result is transferred to the buffer queue of the processor, the processor controls the AD conversion intervals of the plurality of channels within the AD conversion preset interval time by software in the data processing unit according to the AD conversion result.
The invention also provides an electronic device comprising a memory, a processor and a computer program stored in the memory and operable on the processor, wherein the processor implements the method for improving the AD conversion efficiency according to any one of the above when executing the computer program.
The invention also provides an electronic device readable storage medium, on which computer program instructions are stored, which when executed by the processor implement the method for improving AD conversion efficiency according to any one of the above.
Compared with the related art, the method, the system, the electronic equipment and the medium for improving the AD conversion efficiency provided by the invention have the advantages that the digital conversion module uses the AD of multiple channels to connect with single-channel analog data, the AD conversion channels are increased on the premise of not reducing the conversion precision, and the conversion speed can be improved through program control.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 is a flowchart of a method of improving AD conversion efficiency according to an embodiment of the present application;
FIG. 2 is a hardware framework diagram according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a document information summarization system of the present invention;
fig. 4 is a frame diagram of an electronic device according to an embodiment of the present application.
Wherein, the reference numerals are as follows:
a data initializing unit: 51;
AD conversion starting unit: 52;
a data acquisition unit: 53;
a data processing unit: 54;
80 parts of a bus;
a processor: 81;
a memory: 82;
communication interface: 83.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described and illustrated below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden on the person of ordinary skill in the art based on the embodiments provided herein, are intended to be within the scope of the present application.
It is apparent that the drawings in the following description are only some examples or embodiments of the present application, and it is possible for those of ordinary skill in the art to apply the present application to other similar situations according to these drawings without inventive effort. Moreover, it should be appreciated that while such a development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as having the benefit of this disclosure.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by those of ordinary skill in the art that the embodiments described herein can be combined with other embodiments without conflict.
Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. Reference to "a," "an," "the," and similar terms herein do not denote a limitation of quantity, but rather denote the singular or plural. The terms "comprising," "including," "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to only those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein refers to two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The terms "first," "second," "third," and the like, as used herein, are merely distinguishing between similar objects and not representing a particular ordering of objects.
In electronics, a digital-to-analog converter (DAC, D/A, D2A, or D-to-A) is a system that converts digital signals to analog signals. Analog-to-digital converters (ADCs) perform the opposite function. There are several DAC architectures; the suitability of a DAC for a particular application is determined by a quality factor, including resolution, maximum sampling frequency, etc. Digital-to-analog conversion may distort the signal and therefore a DAC with little error should be specified in a particular application. DACs are commonly used in music players to convert digital data streams into analog audio signals. They are also used in televisions and cell phones to convert digital video data into analog video signals that are connected to a screen driver to display monochrome or color images. Both applications require trade-offs in frequency and resolution in using a DAC. The audio DAC is of a low frequency, high resolution type, while the video DAC is of a high frequency, low to medium resolution type. Due to complexity and the need for precisely matched elements, all DACs are implemented with Integrated Circuits (ICs), except for the most specialized DACs. Discrete DACs are typically very high speed, low resolution, power hungry devices such as those used in military radar systems. Ultra-high speed test equipment, particularly sampling oscilloscopes, may also use a discrete DAC.
HX711 is a 24-bit a/D converter chip designed specifically for high-precision electronic scales. Compared with other chips of the same type, the chip integrates peripheral circuits required by other chips of the same type, such as a stabilized voltage supply, an on-chip clock oscillator and the like, and has the advantages of high integration level, high response speed, strong anti-interference performance and the like. The cost of the whole electronic scale is reduced, and the performance and reliability of the whole electronic scale are improved. The interface and programming of the chip and the back-end MCU chip are very simple, all control signals are driven by pins, and registers in the chip do not need to be programmed.
The input selector switch can select the channel A or the channel B at will and is connected with the low-noise programmable amplifier inside the input selector switch. The programmable gain of channel A is 128 or 64, and the corresponding full scale differential input signal amplitude is 20mV or 40mV, respectively. Channel B is then a fixed 64 gain for system parameter detection. The regulated power supply provided in the chip can directly provide power for the external sensor and the A/D converter in the chip, and no additional analog power supply is needed on the system board. The clock oscillator in the chip does not need any external device. The power-on automatic reset function simplifies the initialization process of the power-on.
According to the invention, the analog-to-digital conversion module uses the multi-channel AD to connect with the single-channel analog data, and the AD conversion efficiency is improved by using the cost to exchange time on the premise of not reducing the conversion precision.
The invention will now be described with reference to specific examples.
Example 1
The present embodiment provides a method of improving AD conversion efficiency. Referring to fig. 1 to 2, fig. 1 is a flowchart of a method for improving AD conversion efficiency according to an embodiment of the present application; fig. 2 is a hardware frame diagram according to an embodiment of the present application, and as shown in fig. 1 to 2, a method for improving AD conversion efficiency includes the steps of:
data initialization step S1: respectively initializing AD conversion chips by a processor;
AD conversion start step S2: the processor starts AD conversion of a plurality of channels according to AD conversion preset interval time;
step S3 of data acquisition, namely acquiring AD conversion results of a plurality of channels after the processor monitors AD conversion completion marks of the channels;
data processing step S4: the processor controls the AD conversion interval time of the channels within the AD conversion preset interval time according to the AD conversion result.
In an embodiment, the data initializing step S1 includes the processor initializing AD conversion chips of a plurality of the channels, respectively.
In a specific embodiment, as shown in fig. 2, the processor (HT 32F 59041) initializes the AD conversion chip of the SESER1 channel, the AD conversion chip of the SESER2 channel, respectively.
In an embodiment, the data acquisition step S3 includes the processor monitoring the AD conversion completion flags of the plurality of channels, and acquiring the AD conversion results of the plurality of channels according to the time sequence of the preset interval time.
In a particular embodiment, the processor (HT 32F 59041) separately initiates AD conversion of the SESESER 1 channels, and the interval (T/N) restarts AD conversion of the SESER2 channels. For example, in the case where the conversion accuracy is unchanged, the AD chip conversion time (i.e., from the start of conversion to the completion of chip conversion) is substantially constant, for example, 80ms (T) conversion is completed once, thus enabling the AD conversion of the SESER1 channel, and 40ms (T/N) intervals enable the AD conversion of the SESER2 channel.
After the processor (HT 32F 59041) starts all conversion channels at intervals, the processor (HT 32F 59041) listens for a conversion completion flag, and then sequentially reads the AD conversion result of the SESER1 channel and the AD conversion result of the SESER2 channel at intervals of an interval time (T/N), respectively. For example, when the processor monitors the channel 1 conversion completion flag, the processor starts to collect the data of the channel 1 and transfers the data to a queue to be processed. When the processor monitors the channel 2 conversion completion flag, the data of the channel 2 is collected and transferred to a queue to be processed, wherein the interval is exactly 40ms (T/N) theoretically.
In an embodiment, the step S4 of data processing includes that after the AD conversion result is transferred to a buffer queue of the processor, the processor controls the AD conversion intervals of the channels within the AD conversion preset interval time through software according to the AD conversion result.
In a specific embodiment, when the switching process has a small error, and the time interval for completing the switching of each channel is not (T/N), the switching start time point is controlled by software, so that the switching is always distributed at the (T/N) time interval, that is, the data processing step S4 is used for processing the channel with the time interval not being 40ms (T/N), so as to ensure that the switched channel is distributed evenly in one switching period. The method for improving the AD conversion efficiency can also use multiple independent AD channels built in the singlechip.
The hardware control principle is that the sensor acquires analog data, the analog data are converted into digital data through HX711, the digital data are transmitted to the HT32F59041 processor, and the digital data are transmitted to the display device for display through 485 after being processed by the HT32F59041 processor.
Example two
Referring to fig. 3, fig. 3 is a schematic structural diagram of a document information summarizing system according to the present invention. As shown in fig. 3, the system for improving AD conversion efficiency according to the present invention is applicable to the above method for improving AD conversion efficiency, and includes:
a data initializing unit: respectively initializing AD conversion chips by a processor;
AD conversion starting unit: the processor starts AD conversion of a plurality of channels according to AD conversion preset interval time;
the data acquisition unit acquires AD conversion results of a plurality of channels after the processor monitors AD conversion completion marks of the channels;
a data processing unit: the processor controls the AD conversion interval time of the channels within the AD conversion preset interval time according to the AD conversion result.
In an embodiment, the processor in the data initializing unit initializes the AD conversion chips of the plurality of channels, respectively.
In an embodiment, after the processor monitors the AD conversion completion flags of the plurality of channels, the AD conversion results of the plurality of channels are collected by the data collecting unit according to the time sequence of the preset interval time.
In an embodiment, after the AD conversion result is transferred to a buffer queue of the processor, the processor controls the AD conversion interval time of the plurality of channels within the AD conversion preset interval time by software in the data processing unit according to the AD conversion result.
Example III
Referring to fig. 4, a specific implementation of an electronic device is disclosed in this embodiment. The electronic device may include a processor 81 and a memory 82 storing computer program instructions.
In particular, the processor 81 may include a Central Processing Unit (CPU), or an application specific integrated circuit (Application Specific Integrated Circuit, abbreviated as ASIC), or may be configured to implement one or more integrated circuits of embodiments of the present application.
Memory 82 may include, among other things, mass storage for data or instructions. By way of example, and not limitation, memory 82 may comprise a Hard Disk Drive (HDD), floppy Disk Drive, solid state Drive (Solid State Drive, SSD), flash memory, optical Disk, magneto-optical Disk, tape, or universal serial bus (Universal Serial Bus, USB) Drive, or a combination of two or more of the foregoing. The memory 82 may include removable or non-removable (or fixed) media, where appropriate. The memory 82 may be internal or external to the abnormal data monitoring apparatus, where appropriate. In a particular embodiment, the memory 82 is a Non-Volatile (Non-Volatile) memory. In a particular embodiment, the Memory 82 includes Read-Only Memory (ROM) and random access Memory (Random Access Memory, RAM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (Programmable Read-Only Memory, abbreviated PROM), an erasable PROM (Erasable Programmable Read-Only Memory, abbreviated FPROM), an electrically erasable PROM (Electrically Erasable Programmable Read-Only Memory, abbreviated EFPROM), an electrically rewritable ROM (Electrically Alterable Read-Only Memory, abbreviated EAROM), or a FLASH Memory (FLASH), or a combination of two or more of these. The RAM may be Static Random-Access Memory (SRAM) or dynamic Random-Access Memory (Dynamic Random Access Memory DRAM), where the DRAM may be a fast page mode dynamic Random-Access Memory (Fast Page Mode Dynamic Random Access Memory FPMDRAM), extended data output dynamic Random-Access Memory (Extended Date Out Dynamic Random Access Memory EDODRAM), synchronous dynamic Random-Access Memory (Synchronous Dynamic Random-Access Memory SDRAM), or the like, as appropriate.
Memory 82 may be used to store or cache various data files that need to be processed and/or communicated, as well as possible computer program instructions for execution by processor 81.
The processor 81 implements any of the methods of improving AD conversion efficiency in the above-described embodiments by reading and executing the computer program instructions stored in the memory 82.
In some of these embodiments, the electronic device may also include a communication interface 83 and a bus 80. As shown in fig. 4, the processor 81, the memory 82, and the communication interface 83 are connected to each other through the bus 80 and perform communication with each other.
The communication interface 83 is used to implement communications between various modules, devices, units, and/or units in embodiments of the present application. Communication port 83 may also enable communication with other components such as: and the external equipment, the image/abnormal data monitoring equipment, the database, the external storage, the image/abnormal data monitoring workstation and the like are used for data communication.
Bus 80 includes hardware, software, or both that couple components of the electronic device to one another. Bus 80 includes, but is not limited to, at least one of: data Bus (Data Bus), address Bus (Address Bus), control Bus (Control Bus), expansion Bus (Expansion Bus), local Bus (Local Bus). By way of example, and not limitation, bus 80 may include a graphics acceleration interface (Accelerated Graphics Port), abbreviated AGP, or other graphics Bus, an enhanced industry standard architecture (Extended Industry Standard Architecture, abbreviated EISA) Bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an industry standard architecture (Industry Standard Architecture, ISA) Bus, a wireless bandwidth (InfiniBand) interconnect, a Low Pin Count (LPC) Bus, a memory Bus, a micro channel architecture (Micro Channel Architecture, abbreviated MCa) Bus, a peripheral component interconnect (Peripheral Component Interconnect, abbreviated PCI) Bus, a PCI-Express (PCI-X) Bus, a serial advanced technology attachment (Serial Advanced Technology Attachment, abbreviated SATA) Bus, a video electronics standards association local (Video Electronics Standards Association Local Bus, abbreviated VLB) Bus, or other suitable Bus, or a combination of two or more of the foregoing. Bus 80 may include one or more buses, where appropriate. Although embodiments of the present application describe and illustrate a particular bus, the present application contemplates any suitable bus or interconnect.
The electronic device may be connected to an abnormal data monitoring system to implement the method described in connection with fig. 1-2.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
In summary, the analog-to-digital conversion module uses the multi-channel AD to connect with the single-channel analog data, and the method for increasing the AD conversion channels is used on the premise of not reducing the conversion precision, and N pieces of high-precision original data to be processed can be acquired in one AD conversion period (T) through program control, so that the conversion time of each channel is approximately changed into (T/N), namely the AD conversion speed is improved by N times. The invention solves the problems of improving the AD conversion efficiency by reducing the AD conversion precision in the AD conversion process.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. The scope of the present application is therefore intended to be covered by the appended claims.
Claims (8)
1. A method of improving AD conversion efficiency, comprising:
a data initialization step: respectively initializing AD conversion chips by a processor;
AD conversion starting step: the processor starts AD conversion of a plurality of channels according to AD conversion preset interval time;
the data acquisition step, namely acquiring AD conversion results of a plurality of channels after the processor monitors the AD conversion completion marks of the channels;
and a data processing step: the processor controls the AD conversion interval time of the channels to be within the AD conversion preset interval time according to the AD conversion result;
the data acquisition step includes that after the processor monitors the AD conversion completion marks of the channels, the AD conversion results of the channels are acquired according to the time sequence of the preset interval time.
2. The method for improving AD conversion efficiency according to claim 1, wherein the data initializing step includes the processor initializing AD conversion chips of a plurality of the channels, respectively.
3. The method according to claim 1, wherein the data processing step includes, after the AD conversion result is transferred to a buffer queue of the processor, controlling the AD conversion intervals of the plurality of channels within the AD conversion preset interval time by software according to the AD conversion result.
4. A system for improving AD conversion efficiency, characterized by being applied to the method for improving AD conversion efficiency according to any one of claims 1 to 3, comprising:
a data initializing unit: respectively initializing AD conversion chips by a processor;
AD conversion starting unit: the processor starts AD conversion of a plurality of channels according to AD conversion preset interval time;
the data acquisition unit acquires AD conversion results of a plurality of channels after the processor monitors AD conversion completion marks of the channels;
a data processing unit: the processor controls the AD conversion interval time of the channels to be within the AD conversion preset interval time according to the AD conversion result;
after the processor monitors the AD conversion completion marks of the channels, the AD conversion results of the channels are collected through the data collection unit according to the time sequence of the preset interval time.
5. The system for improving AD conversion efficiency according to claim 4, wherein the processor in the data initializing unit initializes AD conversion chips of the plurality of channels, respectively.
6. The system according to claim 5, wherein the processor controls the AD conversion intervals of the plurality of channels within the AD conversion preset interval time by software in the data processing unit according to the AD conversion result after transferring the AD conversion result to the buffer queue of the processor.
7. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of improving AD conversion efficiency according to any one of claims 1 to 3 when executing the computer program.
8. An electronic device readable storage medium having stored thereon computer program instructions which, when executed by the processor, implement the method of improving AD conversion efficiency of any one of claims 1 to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110721305.1A CN113556125B (en) | 2021-06-28 | 2021-06-28 | Method, system, electronic equipment and medium for improving AD conversion efficiency |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110721305.1A CN113556125B (en) | 2021-06-28 | 2021-06-28 | Method, system, electronic equipment and medium for improving AD conversion efficiency |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113556125A CN113556125A (en) | 2021-10-26 |
| CN113556125B true CN113556125B (en) | 2024-02-06 |
Family
ID=78131024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110721305.1A Active CN113556125B (en) | 2021-06-28 | 2021-06-28 | Method, system, electronic equipment and medium for improving AD conversion efficiency |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113556125B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1564080A (en) * | 2004-04-14 | 2005-01-12 | 西安交通大学 | Digital optical fiber array high speed pick-up device having self-focusing lens |
| CN101018056A (en) * | 2007-02-16 | 2007-08-15 | 中国科学院武汉物理与数学研究所 | Rb atom frequency standard digital servo device |
| CN102269981A (en) * | 2011-03-14 | 2011-12-07 | 南大傲拓科技江苏有限公司 | Analogue quantity acquiring method and device in industrial control |
| CN104950770A (en) * | 2015-06-24 | 2015-09-30 | 中国船舶重工集团公司第七二六研究所 | Controllable high-speed multi-channel signal acquisition control circuit system and control method thereof |
| CN108681269A (en) * | 2018-04-09 | 2018-10-19 | 湖北三江航天万峰科技发展有限公司 | A kind of data collecting system of multichannel isolation |
| US10509104B1 (en) * | 2018-08-13 | 2019-12-17 | Analog Devices Global Unlimited Company | Apparatus and methods for synchronization of radar chips |
| CN111256862A (en) * | 2020-03-31 | 2020-06-09 | 西安微电子技术研究所 | High-precision self-calibration intelligent temperature acquisition and control circuit |
| CN111327319A (en) * | 2020-02-25 | 2020-06-23 | 北京物资学院 | Multichannel analog signal sampling method and device |
| CN112217537A (en) * | 2020-09-22 | 2021-01-12 | 珠海格力电器股份有限公司 | Multichannel signal transceiving system, multichannel signal transceiving method, electronic device, and storage medium |
| CN112560639A (en) * | 2020-12-11 | 2021-03-26 | 上海明略人工智能(集团)有限公司 | Face key point number conversion method, system, electronic equipment and storage medium |
-
2021
- 2021-06-28 CN CN202110721305.1A patent/CN113556125B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1564080A (en) * | 2004-04-14 | 2005-01-12 | 西安交通大学 | Digital optical fiber array high speed pick-up device having self-focusing lens |
| CN101018056A (en) * | 2007-02-16 | 2007-08-15 | 中国科学院武汉物理与数学研究所 | Rb atom frequency standard digital servo device |
| CN102269981A (en) * | 2011-03-14 | 2011-12-07 | 南大傲拓科技江苏有限公司 | Analogue quantity acquiring method and device in industrial control |
| CN104950770A (en) * | 2015-06-24 | 2015-09-30 | 中国船舶重工集团公司第七二六研究所 | Controllable high-speed multi-channel signal acquisition control circuit system and control method thereof |
| CN108681269A (en) * | 2018-04-09 | 2018-10-19 | 湖北三江航天万峰科技发展有限公司 | A kind of data collecting system of multichannel isolation |
| US10509104B1 (en) * | 2018-08-13 | 2019-12-17 | Analog Devices Global Unlimited Company | Apparatus and methods for synchronization of radar chips |
| CN111327319A (en) * | 2020-02-25 | 2020-06-23 | 北京物资学院 | Multichannel analog signal sampling method and device |
| CN111256862A (en) * | 2020-03-31 | 2020-06-09 | 西安微电子技术研究所 | High-precision self-calibration intelligent temperature acquisition and control circuit |
| CN112217537A (en) * | 2020-09-22 | 2021-01-12 | 珠海格力电器股份有限公司 | Multichannel signal transceiving system, multichannel signal transceiving method, electronic device, and storage medium |
| CN112560639A (en) * | 2020-12-11 | 2021-03-26 | 上海明略人工智能(集团)有限公司 | Face key point number conversion method, system, electronic equipment and storage medium |
Non-Patent Citations (1)
| Title |
|---|
| 基于AD5412菊花链的数模转换设计;樊妮娜;夏路易;;机械工程与自动化(第03期);150-156 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113556125A (en) | 2021-10-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101278481B (en) | Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance | |
| Loose et al. | The ACADIA ASIC: detector control and digitization for the Wide-Field Infrared Survey Telescope (WFIRST) | |
| US20130093910A1 (en) | Image sensor and image processing apparatus including the same | |
| CN113556125B (en) | Method, system, electronic equipment and medium for improving AD conversion efficiency | |
| US20120280696A1 (en) | Test chip and chip test system using the same | |
| US7477173B2 (en) | Combined AD/DA converting apparatus | |
| CN112782569B (en) | Threshold value testing device and method for digital chip pin logic level | |
| CN111863114B (en) | Chip sampling quasi-position determining method and device | |
| US8946616B2 (en) | Analog-to-digital converter using variable counting interval and image sensor including same | |
| US10326465B1 (en) | Analog to digital converter device and method for generating testing signal | |
| EP1783505B1 (en) | Compressed logic sample storage | |
| CN116165955A (en) | Extensible multichannel high-precision satellite load remote sensing data acquisition system | |
| CN115763217A (en) | Mass axis correction method and device of quadrupole mass spectrometer | |
| CN110673802B (en) | Data storage method and device, chip, electronic equipment and board card | |
| CN108449558B (en) | DSP-based CCD circuit driving method | |
| JPH11150880A (en) | Voltage-detecting device of assembled battery | |
| CN108267681B (en) | Module test system of programmable circuit | |
| US6725172B2 (en) | Systems and methods for tagging measurement values | |
| CN117420342B (en) | Multichannel acquisition method, device, system, FPGA and sampling oscilloscope | |
| KR20190056326A (en) | Frameless random-access image sensing | |
| US7126858B1 (en) | Apparatus for emulating asynchronous clear in memory structure and method for implementing the same | |
| CN113885968B (en) | Adaptive digital-analog mixed starting mode setting system and method | |
| CN216134526U (en) | High-speed data acquisition device of infrared camera front end | |
| US8099659B2 (en) | Logic tester and method for simultaneously measuring delay periods of multiple tested devices | |
| CN115425957B (en) | Multi-channel switch array control circuit and automatic detection system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |