CN113555471B - Infrared sensor chip based on semiconductor CMOS process and preparation method thereof - Google Patents
Infrared sensor chip based on semiconductor CMOS process and preparation method thereof Download PDFInfo
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Abstract
The embodiment of the application provides an infrared sensor chip based on a semiconductor CMOS process and a preparation method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem that when a sacrificial layer is removed in the related technology, a micro-bridge structure and a beam structure are easily damaged; forming a beam structure and a micro-bridge structure; forming a second sacrificial layer covering the beam structure and the microbridge structure; and removing the first sacrificial layer and the second sacrificial layer. The second sacrificial layer that this application embodiment covered beam structure and microbridge structure through formation utilizes the second sacrificial layer to protect beam structure and microbridge structure's side, prevents to cause the damage to beam structure and microbridge structure when getting rid of first sacrificial layer, improves infrared sensor chip's performance.
Description
Technical Field
The embodiment of the application relates to the technical field of semiconductors, in particular to an infrared sensor chip based on a semiconductor CMOS (complementary metal oxide semiconductor) process and a preparation method thereof.
Background
An infrared sensor chip based on semiconductor CMOS technology is a heat sensor, and the principle is that a microstructure is used for absorbing infrared rays radiated by an external object and generating changes of signals such as resistance, voltage and the like, and a reading circuit is used for amplifying the signals to obtain detection of the intensity of infrared signals radiated by the external object.
In the related art, an infrared sensor chip based on a semiconductor CMOS process generally includes an Integrated Circuit (IC), a microbridge structure and a beam structure, where the IC is an infrared signal processing Circuit, the microbridge structure is an infrared sensing device, the microbridge structure generally includes a bridge and a microbridge deck, the bridge is used for supporting, the microbridge deck is used for sensing an infrared signal, and the beam structure is used for electrically connecting the microbridge deck and the Integrated Circuit.
When the microbridge structure and the beam structure are manufactured, a sacrificial layer is usually formed on a substrate, then the microbridge structure and the beam structure are formed, and finally the sacrificial layer is removed by using etching gas, so that the microbridge structure and the beam structure are in a suspended state.
However, in the process of removing the sacrificial layer, because gaps are formed between the micro-bridge structure and the beam structure and in the beam structure, when etching gas is introduced to the surface of the sacrificial layer, the etching gas can etch the top surfaces and the side surfaces of the micro-bridge structure and the beam structure, so that the electrode layers of the micro-bridge structure and the beam structure are damaged, and the performance of the infrared sensor chip is reduced.
Disclosure of Invention
In view of the above problems, embodiments of the present application provide an infrared sensor chip based on a semiconductor CMOS process and a method for manufacturing the same, so as to solve the technical problem that a micro-bridge structure and a beam structure are easily damaged by removing a sacrificial layer in the related art.
In order to achieve the above object, the embodiments of the present application provide the following technical solutions:
in a first aspect, an embodiment of the present application provides a method for manufacturing an infrared sensor chip based on a semiconductor CMOS process, which includes the following steps:
providing a substrate, wherein the substrate is provided with a first sacrificial layer;
forming a beam structure and a microbridge structure, wherein the microbridge structure comprises a bridge deck and a bridge beam connected with the bridge deck, the bridge beam is positioned in the first sacrificial layer and is electrically connected with the circuit in the substrate, the bridge deck is arranged on the first sacrificial layer and is connected with the beam structure, and a gap is arranged in the beam structure;
forming a second sacrificial layer covering the beam structure and the microbridge structure;
and removing the first sacrificial layer and the second sacrificial layer.
The method for manufacturing the infrared sensor chip based on the semiconductor CMOS process, wherein the step of removing the first sacrificial layer and the second sacrificial layer includes:
patterning the second sacrificial layer to form an etching hole in the second sacrificial layer;
and etching gas is introduced into the etching holes to remove the first sacrificial layer and the second sacrificial layer.
The method for manufacturing the infrared sensor chip based on the semiconductor CMOS process comprises the step of etching the beam structure, wherein the distance between the inner wall of the etching hole and the beam structure close to the etching hole is larger than 0.05 um.
The method for manufacturing the infrared sensor chip based on the semiconductor CMOS process, wherein the step of patterning the second sacrificial layer includes:
forming a first mask layer on the second sacrificial layer;
patterning the first mask layer to form a first opening in the first mask layer, wherein the first opening exposes the micro-bridge structure;
removing a part of the thickness of the second sacrificial layer exposed in the first opening to form a first groove in the second sacrificial layer;
removing the first mask layer;
forming a second mask layer in the first groove, wherein the second mask layer extends out of the first groove and covers the second sacrificial layer;
patterning the second mask layer to form at least three second openings in the second mask layer, wherein the three second openings respectively expose the gap, the area between the beam structure and the micro-bridge structure and the part of the area surrounded by the bridge;
and removing the second sacrificial layer exposed in the second opening to form etching holes in the second sacrificial layer, wherein the etching holes correspond to the second openings one by one.
The method for manufacturing the infrared sensor chip based on the semiconductor CMOS process is as described above, wherein the depth of the first groove occupies the thickness 1/3-1/2 of the second sacrificial layer.
The method for manufacturing an infrared sensor chip based on a semiconductor CMOS process as described above, wherein after the step of removing the second sacrificial layer exposed in the second opening, and before the step of removing the first sacrificial layer, the method further comprises:
and removing the second mask layer.
The method for manufacturing the infrared sensor chip based on the semiconductor CMOS process, wherein the step of providing the substrate with the first sacrificial layer thereon comprises:
forming a dielectric layer on the substrate;
patterning the dielectric layer to form a plurality of through holes in the dielectric layer;
and forming an interconnection structure in each through hole.
The method for manufacturing the infrared sensor chip based on the semiconductor CMOS process includes the steps of:
forming a plurality of connection holes in the first sacrificial layer, each of the connection holes exposing one of the interconnect structures;
forming a first initial protection layer on the side wall of the connecting hole, wherein the first initial protection layer extends out of the connecting hole and covers the first sacrificial layer;
forming an infrared absorption layer on the first initial protection layer, wherein the infrared absorption layer covers part of the first initial protection layer, and a middle hole is formed in the connecting hole by the infrared absorption layer;
forming an initial electrode layer covering the bottom wall of the middle hole, the infrared absorption layer and the first initial protection layer;
removing part of the initial electrode layer, wherein the remained initial electrode layer forms an electrode layer;
forming a second initial protection layer on the electrode layer, wherein the second initial protection layer also covers the exposed first initial protection layer and the exposed infrared absorption layer;
the first initial protection layer and the second initial protection layer are arranged on the first sacrificial layer in a graphical mode, the first initial protection layer which is reserved forms a first protection layer, the second initial protection layer which is reserved forms a second protection layer, the first protection layer, the electrode layer and the second protection layer which are arranged in the first area in a stacked mode form a beam structure, and the first protection layer, the infrared absorption layer, the electrode layer and the second protection layer which are arranged in the second area in a stacked mode form a micro-bridge structure.
The preparation method of the infrared sensor chip based on the semiconductor CMOS process includes that the first protective layer and the second protective layer are made of silicon oxide or silicon nitride.
The preparation method of the infrared sensor chip based on the semiconductor CMOS process includes that the first sacrificial layer and the second sacrificial layer are made of one of amorphous silicon, polyimide or polysilicon.
A second aspect of the embodiments of the present application provides an infrared sensor chip based on a semiconductor CMOS process, which is manufactured by the above-mentioned method for manufacturing an infrared sensor chip based on a semiconductor CMOS process, and includes a substrate;
a first sacrificial layer disposed on the substrate;
a beam structure disposed within the first sacrificial layer and having a gap therein;
the micro-bridge structure comprises a bridge deck and a bridge beam connected with the bridge deck, wherein the bridge deck is arranged on the first sacrificial layer, and the bridge beam is positioned in the first sacrificial layer and is electrically connected with the circuit in the substrate;
and the second sacrificial layer covers the beam structure and the micro-bridge structure, and at least three etching holes are formed in the second sacrificial layer, wherein the two etching holes penetrate through the first sacrificial layer and respectively expose the gap and the region between the beam structure and the micro-bridge structure, and the other etching hole extends into the first sacrificial layer and exposes the part of the region surrounded by the bridge.
The infrared sensor chip based on the semiconductor CMOS process as described above, wherein a space is provided between a bottom of the hole exposing the etching hole of the portion of the region surrounded by the bridge and the upper surface of the bridge.
In the infrared sensor chip based on the semiconductor CMOS process and the preparation method thereof provided by the embodiment of the application, the second sacrificial layer covering the beam structure and the microbridge structure is formed, and the second sacrificial layer is used for protecting the side surfaces of the beam structure and the microbridge structure, so that the beam structure and the microbridge structure are prevented from being damaged when the first sacrificial layer is removed, and the performance of the infrared sensor chip is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a process flow diagram of a method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a dielectric layer formed in a method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram illustrating a structure of an interconnection structure formed in a method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram illustrating formation of a first sacrificial layer and a connection hole in a method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram illustrating a first initial protection layer and an infrared absorption layer formed in a method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram illustrating an initial electrode layer formed in a method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of an electrode layer formed in the method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to the embodiment of the present application;
fig. 8 is a schematic structural diagram illustrating a second initial protection layer formed in a method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram illustrating a beam structure and a microbridge structure formed in a method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to an embodiment of the present disclosure;
fig. 10 is a schematic structural diagram illustrating a second sacrificial layer formed in a method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to an embodiment of the present disclosure;
fig. 11 is a schematic structural diagram of a first mask layer formed in the method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to the embodiment of the present application;
fig. 12 is a schematic structural diagram illustrating a first groove formed in a method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to an embodiment of the present disclosure;
fig. 13 is a schematic structural diagram illustrating a second mask layer formed in the method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to the embodiment of the present application;
fig. 14 is a schematic structural diagram illustrating formation of a second opening in a method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to an embodiment of the present disclosure;
fig. 15 is a schematic structural diagram illustrating etching holes formed in a method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to an embodiment of the present disclosure;
fig. 16 is a schematic structural diagram illustrating a method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to an embodiment of the present disclosure, in which the first sacrificial layer and the second sacrificial layer are removed;
fig. 17 is a schematic diagram of an infrared sensor chip based on a semiconductor CMOS process according to an embodiment of the present application.
Description of reference numerals:
10: a substrate; 20: a dielectric layer; 21: a through hole; 22: an interconnect structure; 30: a first sacrificial layer; 31: connecting holes; 32: a middle hole; 41: a first initial protective layer; 42: an infrared absorbing layer; 43: an initial electrode layer; 44: an electrode layer; 45: a second initial protective layer; 46: a first protective layer; 47: a second protective layer; 40: a beam structure; 48: a gap; 50: a microbridge structure; 51: a bridge; 52: a bridge deck; 60: a second sacrificial layer; 61: etching the hole; 62: a first groove; 70: a first mask layer; 71: a first opening; 80: a second mask layer; 81: a second opening; 90: electrically connecting the posts.
Detailed Description
The embodiment of the application provides a preparation method of an infrared sensor chip based on a semiconductor CMOS process, wherein a second sacrificial layer 60 covering a beam structure 40 and a micro-bridge structure 50 is formed on a first sacrificial layer 30, when the first sacrificial layer 30 is removed, the second sacrificial layer 60 can be removed synchronously, and in the process, the second sacrificial layer 60 can protect the top surfaces of the micro-bridge structure 50 and the beam structure 40, so that the damage to the micro-bridge structure 50 and the beam structure 40 is reduced, and the performance of the infrared sensor chip is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present application more comprehensible, embodiments of the present application are described in detail below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The infrared sensor chip based on the semiconductor CMOS process and the method for manufacturing the same will be described in detail with reference to fig. 1 to 17.
The embodiment of the application provides a preparation method of an infrared sensor chip based on a semiconductor CMOS process, which comprises the following steps:
step S100: a substrate 10 is provided, the substrate 10 having a first sacrificial layer 30 thereon.
Illustratively, the substrate 10 serves as a supporting member of an infrared sensor chip based on a semiconductor CMOS process for supporting other components provided thereon, wherein the substrate 10 may be made of a semiconductor material, which may be one or more of silicon, germanium, a silicon germanium compound, and a silicon carbon compound.
In the present embodiment, the first sacrificial layer 30 may be formed directly on the substrate 10, or the interconnect layer may be formed first, and then the first sacrificial layer 30 is formed.
Illustratively, the dielectric layer 20 may be formed on the substrate 10 by a deposition process, for example, the dielectric layer 20 may be formed on the substrate 10 by a chemical vapor deposition process or a physical vapor deposition process, wherein the material of the dielectric layer 20 may include silicon oxide.
Then, the dielectric layer 20 is patterned to form a plurality of through holes 21 in the dielectric layer 20, and the plurality of through holes 21 may be spaced along a first direction, wherein the first direction is an X direction in fig. 2.
Thereafter, a deposition process may be utilized to deposit a conductive material within each via 21, the conductive material within each via 21 forming an interconnect structure 22, the interconnect structure 22 being utilized to effect an electrical connection between a subsequently formed microbridge structure 50 and an integrated circuit within the substrate 10, wherein the conductive material comprises copper or tungsten.
Finally, a first sacrificial layer 30 is formed by a deposition process, wherein the first sacrificial layer 30 covers the dielectric layer 20 and the interconnection structure 22.
Step S200: the beam structure 40 and the micro-bridge structure 50 are formed, the micro-bridge structure 50 includes a bridge deck 52 and a bridge 51 connected to the bridge deck 52, wherein the bridge 51 is located in the first sacrificial layer 30 and is electrically connected to the circuit in the base 10, the bridge deck 52 is disposed on the first sacrificial layer 30 and is connected to the beam structure 40, and a gap is provided in the beam structure 40.
Illustratively, a plurality of connection holes 31 may be formed in the first sacrificial layer 30, each connection hole 31 exposing one interconnect structure 22.
Specifically, a photoresist layer with a certain thickness may be formed on the first sacrificial layer 30 by a coating method, and then the photoresist layer is patterned by exposure, development or etching, so that an opening is formed in the photoresist layer, and the projection of the opening on the dielectric layer 20 covers at least a portion of the interconnect structure 22.
Then, the first sacrificial layer 30 exposed in the opening is removed using an etching liquid or an etching gas to form a connection hole 31 in the first sacrificial layer 30.
A first preliminary protective layer 41 is formed on the sidewall of the connection hole 31, and the first preliminary protective layer 41 extends outside the connection hole 31 and covers the first sacrificial layer 30.
After the first initial protection layer 41 is formed, the infrared absorption layer 42 is formed on the first initial protection layer 41, the infrared absorption layer 42 covers part of the first initial protection layer 41, and the infrared absorption layer 42 forms the middle hole 32 in the connection hole 31, wherein the infrared absorption layer 42 covers part of the first initial protection layer 41, it can be understood that the length of the infrared absorption layer 42 outside the connection hole 31 is smaller than the length of the first initial protection layer 41, taking the orientation shown in fig. 5 as an example, the left end part of the infrared absorption layer 42 is not aligned with the left end part of the first initial protection layer 41, and the right end part of the infrared absorption layer 42 is not aligned with the right end part of the first initial protection layer 41.
The infrared absorption layer 42 is made of silicon or silicon nitride.
And then, forming an initial electrode layer 43 by utilizing an atomic layer deposition process, wherein the initial electrode layer 43 covers the bottom wall of the middle hole 32, the infrared absorption layer 42 and the first initial protection layer 41, and the material of the initial electrode layer 43 comprises metallic titanium.
Then, the initial electrode layer 43 is patterned, a portion of the initial electrode layer 43 is removed, and the remaining initial electrode layer 43 forms an electrode layer 44, wherein a portion of the electrode layer 44 serves as a conductive portion of the micro-bridge structure 50, and another portion of the electrode layer 44 serves as a conductive portion of the beam structure 40, for example, in the orientation shown in fig. 7, from left to right, the electrode layer 44 in the first circle serves as a conductive portion of the micro-bridge structure 50, and the electrode layer 44 in the second circle serves as a conductive portion of the beam structure 40.
A second preliminary protective layer 45 is formed on the electrode layer 44, and the second preliminary protective layer 45 also covers the exposed first preliminary protective layer 41 and the infrared absorption layer 42.
After the second initial protection layer 45 is formed, the first initial protection layer 41 and the second initial protection layer 45 on the first sacrificial layer 30 are patterned, the remaining first initial protection layer 41 constitutes a first protection layer 46, the remaining second initial protection layer 45 constitutes a second protection layer 47, wherein the first protective layer 46, the electrode layer 44 and the second protective layer 47 sequentially stacked in the first region form a beam structure 40, the first protective layer 46, the infrared absorption layer 42, the electrode layer 44 and the second protective layer 47 sequentially stacked in the second region form a micro-bridge structure 50, and a portion located in the first sacrificial layer 30 constitutes a bridge 51 of the micro-bridge structure 50, a portion located on the first sacrificial layer 30 constitutes a deck 52 of the micro-bridge structure 50, the deck 52 is connected to the beam structure 40, so that the infrared signals formed on the deck 52 are transmitted through the beam structure 40 to the integrated circuits located in the base 10.
The first area is area a in fig. 9, and the second area is area B in fig. 9.
Step S300: a second sacrificial layer 60 is formed overlying the beam structure 40 and the microbridge structure 50.
A second sacrificial layer 60 is formed by a deposition process, and the second sacrificial layer 60 covers the beam structure 40 and the microbridge structure 50, wherein the material of the second sacrificial layer 60 may be the same as that of the first sacrificial layer 30, and both include one of amorphous silicon, polyimide, or polysilicon.
Step S400: the first sacrificial layer 30 and the second sacrificial layer 60 are removed.
Illustratively, the second sacrificial layer 60 is patterned to form etch holes 61 in the second sacrificial layer 60.
Specifically, the first mask layer 70 is formed on the second sacrificial layer 60, and a photoresist layer may be formed on the second sacrificial layer 60 to a certain thickness, for example, by coating.
The first mask layer 70 is patterned to form a first opening 71 in the first mask layer 70, and the first opening 71 exposes the micro-bridge structure 50, that is, a projection area of the first opening 71 on the substrate 10 coincides with a projection of the micro-bridge structure 50 on the substrate 10.
Specifically, the photoresist layer is patterned by exposure, development, or etching, so that the first opening 71 is formed in the photoresist layer.
After the first opening 71 is formed, a portion of the thickness of the second sacrificial layer 60 exposed in the first opening 71 may be removed using an etching liquid or an etching gas to form a first groove 62 in the second sacrificial layer 60.
In the embodiment, the second sacrificial layer 60 with a partial thickness above the micro-bridge structure 50 is removed to thin a partial region of the second sacrificial layer 60, because the beam structure 40 has a smaller size, and in the subsequent etching process, the second sacrificial layer 60 above the beam structure 40 is etched faster, so that in the embodiment, the beam structure 40 can be prevented from being over-etched by reducing the thickness of the second sacrificial layer 60 above the micro-bridge structure 50, and the performance of the infrared sensor chip is ensured.
If the ratio of the depth of the first groove 62 to the thickness of the second sacrificial layer 60 is less than 1/3, the depth of the first groove 62 will be too small, and the beam structure 40 will be over-etched in the subsequent etching process, and if the ratio of the depth of the first groove 62 to the thickness of the second sacrificial layer 60 is greater than 1/2, the depth of the first groove 62 will be too small, and the micro-bridge structure 50 will be over-etched in the subsequent etching process, so that the depth of the first groove 62 is as large as 1/3-1/2 of the thickness of the second sacrificial layer 60 in this embodiment, which can prevent the over-etching of the beam structure 40 and the micro-bridge structure 50, and further improve the performance of the infrared sensor chip.
After the first recess 62 is formed, the first masking layer 70 may be removed using a cleaning solution.
A second masking layer 80 is formed in the first recess 62, and the second masking layer 80 extends to the outside of the first recess 62 and covers the second sacrificial layer 60.
The second mask layer 80 is patterned to form at least three second openings 81 in the second mask layer 80, and the three second openings 81 expose portions of the gap 48, the region between the beam structure 40 and the microbridge structure 50, and the region surrounded by the bridge 51, respectively.
Taking the orientation shown in fig. 14 as an example, from right to left, the first second opening 81 exposes the gap 48 in the beam structure 40, the second opening 81 exposes the region between the beam structure 40 and the microbridge structure 50, and the third second opening 81 exposes a portion of the region surrounded by the bridge beam 51, that is, the dimension of the third second opening 81 in the first direction is smaller than the dimension of the region surrounded by the second protective layer 47 in the connection hole 31.
The second sacrificial layer 60 exposed in the second openings 81 is removed to form etch holes 61 in the second sacrificial layer 60, the etch holes 61 corresponding to the second openings 81 one to one.
Finally, an etching gas is passed into the etching holes 61 to remove the first sacrificial layer 30 and the second sacrificial layer 60.
In some embodiments, the distance between the inner wall of the via 61 and the beam structure 40 near the via 61 is greater than 0.05um, i.e., the via 61 does not expose the sides of the beam structure 40 and the micro-bridge structure 50.
When the etching gas is introduced into the etching hole 61, the second sacrificial layer 60 protects the top surfaces of the micro-bridge structure 50 and the beam structure 40, prevents the etching from reaching the second protective layer 47 on the top surfaces of the micro-bridge structure 50 and the beam structure 40, and reduces damage to the second protective layer 47.
In addition, since the beam structure 40 has a smaller size, when the etching gas is introduced into the etching hole 61, the etching gas can laterally etch the side surface of the beam structure 40, and therefore, in this embodiment, the second sacrificial layer 60 is used to wrap the beam structure 40 and the microbridge structure 50, so as to prevent the etching gas from laterally over-etching the beam structure 40, and ensure the performance of the beam structure 40.
The infrared sensor chip based on the semiconductor CMOS process provided by the embodiment of the application comprises a substrate 10, a first sacrificial layer 30, a beam structure 40, a micro-bridge structure 50 and a second sacrificial layer 60.
The first sacrificial layer 30 is disposed on the substrate 10, wherein the first sacrificial layer 30 may be in direct contact with the substrate 10 or may be in contact with the substrate 10 through the interconnect structure 22.
The beam structure 40 is disposed on the first sacrificial layer 30 with a gap 48 within the beam structure 40.
The beam structure 40 is used to electrically connect the micro-bridge structure 50 to the integrated circuit in the substrate 10, for example, as shown in fig. 17, one end of the beam structure 40 is connected to the micro-bridge structure 50, and the other end of the beam structure 40 can be connected to the substrate 10 through an electrical connection pillar 90, wherein the beam structure 40 includes a first protection layer 46, an electrode layer 44 and a second protection layer 47 which are stacked.
The micro-bridge structure 50 includes a bridge deck 52 and a bridge deck 51 connected to the bridge deck 52, wherein the bridge deck 52 is disposed on the first sacrificial layer 30, the bridge deck 51 is located in the first sacrificial layer 30 and electrically connected to the circuit in the substrate 10, and wherein the bridge deck 52 is connected to the beam structure 40.
The second sacrificial layer 60 covers the beam structure 40 and the microbridge structure 50, that is, the second sacrificial layer 60 covers the beam structure 40 and the microbridge structure 50 to protect the beam structure 40 and the microbridge structure 50, and the second sacrificial layer 60 has at least three etching holes 61 therein, wherein two etching holes 61 penetrate through the first sacrificial layer 30 to expose the gap 48, the region between the beam structure 40 and the microbridge structure 50, respectively, and another etching hole 61 extends into the first sacrificial layer 30 to expose a portion of the region surrounded by the bridge 51.
Taking the orientation shown in fig. 15 as an example, from right to left, the first via 61 exposes the gap 48 of the beam structure 40, the second via 61 exposes the region between the beam structure 40 and the microbridge structure 50, and the third via 61 exposes a portion of the region surrounded by the bridge 51.
In this embodiment, when the etching gas is introduced into the etching hole 61, the second sacrificial layer 60 protects the top surfaces of the micro-bridge structure 50 and the beam structure 40, so as to prevent the etching gas from reaching the second protective layer 47 on the top surfaces of the micro-bridge structure 50 and the beam structure 40, thereby reducing the damage to the second protective layer 47.
In some embodiments, a space is formed between the bottom of the etching hole 61 exposing the part of the area surrounded by the bridge 51 and the upper surface of the bridge 51, and the second sacrificial layer 60 is used to protect the upper surface of the bridge 51, so that the etching gas can be prevented from laterally over-etching the upper surface of the bridge 51, and the performance of the micro-bridge structure 50 is ensured.
The embodiments or implementation modes in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
It should be noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (9)
1. A preparation method of an infrared sensor chip based on a semiconductor CMOS process is characterized by comprising the following steps:
providing a substrate, wherein the substrate is provided with a first sacrificial layer;
forming a beam structure and a microbridge structure, wherein the microbridge structure comprises a bridge deck and a bridge beam connected with the bridge deck, the bridge beam is positioned in the first sacrificial layer and is electrically connected with the circuit in the substrate, the bridge deck is arranged on the first sacrificial layer and is connected with the beam structure, and a gap is arranged in the beam structure;
forming a second sacrificial layer covering the beam structure and the microbridge structure;
removing the first sacrificial layer and the second sacrificial layer;
wherein the step of removing the first sacrificial layer and the second sacrificial layer comprises:
patterning the second sacrificial layer to form an etching hole in the second sacrificial layer;
etching gas is led into the etching hole to remove the first sacrificial layer and the second sacrificial layer;
wherein, in the step of patterning the second sacrificial layer, the step of patterning the second sacrificial layer comprises:
forming a first mask layer on the second sacrificial layer;
patterning the first mask layer to form a first opening in the first mask layer, wherein the first opening exposes the micro-bridge structure;
removing a part of the thickness of the second sacrificial layer exposed in the first opening to form a first groove in the second sacrificial layer;
removing the first mask layer;
forming a second mask layer in the first groove, wherein the second mask layer extends out of the first groove and covers the second sacrificial layer;
patterning the second mask layer to form at least three second openings in the second mask layer, wherein the three second openings respectively expose the gap, the area between the beam structure and the micro-bridge structure and the part of the area surrounded by the bridge;
and removing the second sacrificial layer exposed in the second opening to form etching holes in the second sacrificial layer, wherein the etching holes correspond to the second openings one by one, and the side surfaces of the micro-bridge structure and the beam structure are not exposed by the etching holes.
2. The method of claim 1, wherein a distance between an inner wall of the via and the beam structure near the via is greater than 0.05 um.
3. The method of claim 1, wherein the depth of the first recess is 1/3-1/2 of the thickness of the second sacrificial layer.
4. The method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to any one of claims 1 to 3, wherein after the step of removing the second sacrificial layer exposed in the second opening, before the step of removing the first sacrificial layer and the second sacrificial layer, the method for manufacturing further comprises:
and removing the second mask layer.
5. The method for preparing an infrared sensor chip based on a semiconductor CMOS process according to any one of claims 1-3, wherein the step of providing a substrate with a first sacrificial layer thereon comprises:
forming a dielectric layer on the substrate;
patterning the dielectric layer to form a plurality of through holes in the dielectric layer;
and forming an interconnection structure in each through hole.
6. The method of claim 5, wherein the step of forming the beam structure and the microbridge structure comprises:
forming a plurality of connection holes in the first sacrificial layer, each of the connection holes exposing one of the interconnect structures;
forming a first initial protection layer on the side wall of the connecting hole, wherein the first initial protection layer extends out of the connecting hole and covers the first sacrificial layer;
forming an infrared absorption layer on the first initial protection layer, wherein the infrared absorption layer covers part of the first initial protection layer, and a middle hole is formed in the connecting hole by the infrared absorption layer;
forming an initial electrode layer covering the bottom wall of the middle hole, the infrared absorption layer and the first initial protection layer;
removing part of the initial electrode layer, wherein the remained initial electrode layer forms an electrode layer;
forming a second initial protection layer on the electrode layer, wherein the second initial protection layer also covers the exposed first initial protection layer and the exposed infrared absorption layer;
the first initial protection layer and the second initial protection layer are arranged on the first sacrificial layer in a graphical mode, the first initial protection layer which is reserved forms a first protection layer, the second initial protection layer which is reserved forms a second protection layer, the first protection layer, the electrode layer and the second protection layer which are arranged in the first area in a stacked mode form a beam structure, and the first protection layer, the infrared absorption layer, the electrode layer and the second protection layer which are arranged in the second area in a stacked mode form a micro-bridge structure.
7. The method of claim 6, wherein the first and second protective layers comprise silicon oxide or silicon nitride.
8. The method of claim 7, wherein the first sacrificial layer and the second sacrificial layer are made of one of amorphous silicon, polyimide or polysilicon.
9. An infrared sensor chip based on a semiconductor CMOS process, which is manufactured by the method for manufacturing an infrared sensor chip based on a semiconductor CMOS process according to any one of claims 1 to 8, comprising:
a substrate having circuitry therein;
a beam structure disposed on the substrate through an electrical connection post, and having a gap therein;
and the micro bridge structure comprises a bridge deck and a bridge beam connected with the bridge deck, and the bridge beam is connected with one end of the beam structure, which deviates from the electric connecting column, so that the micro bridge structure is electrically connected with a circuit in the substrate.
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