CN113555457B - Ge/Si substrate and preparation method thereof - Google Patents

Ge/Si substrate and preparation method thereof Download PDF

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CN113555457B
CN113555457B CN202010338509.2A CN202010338509A CN113555457B CN 113555457 B CN113555457 B CN 113555457B CN 202010338509 A CN202010338509 A CN 202010338509A CN 113555457 B CN113555457 B CN 113555457B
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芦红
魏炼
苗艺
李晨
陈延峰
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Abstract

The invention provides a Ge/Si substrate, which comprises a Si substrate, a Si buffer layer and a Ge film which are sequentially stacked, wherein the Ge film is grown on the Si buffer layer by an epitaxial method, and the hole mobility of the Ge film is more than 1000cm 2 Vs. In the Ge/Si substrate provided by the invention, the Ge film has flat surface, high monocrystal quality, complete relaxation of crystal lattice and hole carrier mobility of more than 1000cm 2 Vs up to 1300cm 2 And the V.s can greatly promote the development of Si-based Ge photon technology, and in addition, the Ge/Si substrate can replace a germanium substrate and is used for epitaxial growth of materials and subsequent device integration and processing. The invention also provides a preparation method of the Ge/Si substrate.

Description

Ge/Si substrate and preparation method thereof
Technical Field
The invention relates to a Ge/Si substrate with high mobility and a preparation method thereof, in particular to optimization of a direct epitaxial high-quality Ge growth condition on a Si substrate and regulation and control of defects in a Ge/Si interface and a film, comprising the processes of substrate treatment, buffer layer growth, ge growth temperature optimization and in-situ annealing.
Background
Silicon (Si) and germanium (Ge) are the most common semiconductor materials and are also important electronic component materials. The Ge/Si material can be used as a new material for researching silicon-based high-speed electronic devices, and is the first choice material for silicon-based long-wavelength photodetectors.
In addition, germanium is lattice matched with GaAs materials, and the Ge/Si substrate can be used as a virtual substrate of silicon-based GaAs materials, and has important application prospects in the aspects of silicon-based photoelectric integration, silicon-based high-efficiency solar cell development and the like.
But the lattice mismatch degree of germanium and silicon is more than 4%, so that the Ge/Si substrate technology is difficult to realize. From the main technical index of the Ge epitaxial layer obtained by direct epitaxy on Si substrates, the following problems exist:
1) The surface roughness of the Ge epitaxial layer is large, which is not beneficial to the growth of III-V heterostructures on the subsequent Ge buffer layer;
2) The Ge epitaxial layer has high dislocation density, and can degrade the performance of the device in the application of photoelectric devices.
Although great progress is made on the improvement of dislocation density and roughness at present, the hole mobility of the obtained Ge film is quite different from that of a Ge block, and the mobility is a key index for measuring the quality of a material, and the numerical value directly reflects the performances of the material such as purity, single crystallinity and the like. As early as 1989 Kataoka et al conducted electrical studies on Ge films epitaxially grown on Si at different temperatures, they found that the mobility of the Ge films was not more than 400cm 2 Vs, while finding that the mobility of the annealed Ge film is reduced to 100cm 2 The reason for/Vs is that annealing while improving crystal quality produces some island morphology to increase carrier concentration. In addition, zhou et al demonstrate that the hole mobility of Ge films obtained with low temperature Ge layers at higher growth temperatures (350 ℃) is higher (550 cm) 2 /Vs). Hole mobility of a Ge film epitaxially grown on Si by Chen et al is 280cm 2 Vs, when low-temperature Si is inserted in the middle 0.75 Ge 0.25 The hole mobility of the epitaxial Ge film can be improved to 450cm when the Si superlattice buffer layer is used 2 Vs. The improvement of the mobility of the Ge/Si substrate is a problem to be solved.
While germanium substrates are relatively expensive. Therefore, developing and optimizing a process for preparing a high quality Ge epitaxial layer on a silicon substrate has significant practical value.
There are three common methods for epitaxial germanium on current silicon substrates: 1. firstly, growing germanium-silicon alloy with low germanium content on a silicon wafer, and then continuously improving a layer-by-layer growth mode of the germanium content; 2. techniques utilizing selective area growth (selective area growth, SAG). The technology needs to pattern a substrate first and then carry out epitaxial lateral growth; "two-step growth", i.e., first growing a thin Ge seed layer (30-100 nm) at low temperature (300-400 ℃) to limit migration of Ge atoms and thereby prevent three-dimensional island nucleation of Ge; the thick Ge film is then grown at high temperature (600-850 ℃) to achieve higher growth rates and better Ge crystallinity. Both of the former methods are unsuitable for a wide range of applications due to cost and process complexity. The third method is a currently common method, but the mobility of the obtained Ge/Si substrate is not high, while the dislocation density and surface roughness still need to be further improved.
Disclosure of Invention
The invention aims to provide a Ge/Si substrate with high mobility and a preparation method thereof. The preparation method has the advantages of simpler preparation process and lower cost.
In order to achieve the above object, the present invention adopts the following technical scheme:
the invention provides a Ge/Si substrate, which comprises a Si substrate, a Si buffer layer and a Ge film which are sequentially stacked, wherein the Ge film is grown on the Si buffer layer by an epitaxial method, and the hole mobility of the Ge film is more than 1000cm 2 /Vs。
In some embodiments of the invention, the hole mobility of the Ge film is 1200-1300cm 2 /Vs。
In some embodiments of the present invention, the interface of the Ge film and the Si buffer layer has a periodically arranged array of 90 ° misfit dislocations.
In some embodiments of the present invention, the Ge film comprises a Ge film having an atomically flat surface topography.
In some embodiments of the invention, the Ge film includes a threading dislocation density of 10 7 /cm 2 Magnitude or less than 10 7 /cm 2 Is a Ge film of (C).
In some embodiments of the invention, the Ge film has a thickness of less than 1 micron, and further the Ge film has a thickness of 400-600nm.
In some embodiments of the invention, the thickness of the Si buffer layer is less than 100nm, further, the thickness of the Si buffer layer is 20-50nm.
The invention also provides a method of preparing the Ge/Si substrate of the invention, the method comprising:
step 1, obtaining a Si substrate with a (100) crystal face;
step 2, pretreating the Si substrate with the (100) crystal face by using a chemical reagent, and then carrying out surface treatment on the pretreated Si substrate with the (100) crystal face;
step 3, growing a layer of Si buffer layer on the Si substrate with the (100) crystal face after the surface treatment by a molecular beam epitaxy method;
step 4, directly epitaxially growing a Ge film on the Si buffer layer at a temperature of between 100 and 600 ℃;
and 5, carrying out in-situ annealing on the obtained Ge film.
In some embodiments of the invention, in step 2, the surface treatment is performed at a temperature between 500 ℃ and 600 ℃.
In some embodiments of the invention, the surface treatment is performed for a period of time ranging from 5 to 10 minutes.
In some embodiments of the invention, the growth temperature of the Si buffer layer is 400 ℃ to 700 ℃.
In some embodiments of the present invention, in step 4, the Ge film growth temperature is from 100 ℃ to 300 ℃.
In some embodiments of the invention, the growth rate of the Ge film is
Figure BDA0002467645780000031
In some embodiments of the invention, the annealing temperature is 300 ℃ to 900 ℃. In some embodiments of the invention, the annealing temperature is 500 ℃ to 700 ℃. In some embodiments of the invention, the annealing temperature is 700 ℃ to 800 ℃.
In some embodiments of the invention, the annealing time is 10-30 minutes.
Preferably, in step 2, the chemical agent used is hydrofluoric acid.
The invention epitaxially grows germanium on a silicon substrate, and provides a preparation method of a Ge/Si substrate with high mobility, which has the following advantages:
(1) The germanium film prepared by the method has flat surface, high monocrystal quality, complete relaxation of crystal lattice and hole carrier mobility of more than 1000cm 2 Vs up to 1300cm 2 The V.s is highest in the hole mobility of the Ge/Si substrate reported at present, can greatly promote the development of Si-based Ge photon technology, and can replace a germanium substrate for the epitaxial growth of related materials and the subsequent integration of materials and devices.
(2) The silicon (100) substrate processed by the method of the invention can achieve atomic level flatness.
(3) The use of low temperature growth in the method of the present invention has three advantages, firstly, many point defects are introduced into the epitaxial layer during the growth of low temperature epitaxy, and the point defects mainly consist of vacancy clusters, which tend to become nucleation sites, ensuring the smooth progress of epitaxy, and importantly, the vacancy clusters are also annihilation centers of dislocations, and play an important role in-situ annealing. Secondly, in previous studies, we found that the Ge thin film cannot be connected into one piece at higher growth temperature, that is, the coverage area of the Ge thin film is smaller at higher temperature, so that the rugged morphology tends to appear, and the partial area is not too much nucleated due to too fast migration of Ge atoms reaching the surface of the Si substrate at higher temperature. While low temperatures help to obtain a continuous film. Thirdly, for the large-mismatch heteroepitaxy, how to release the mismatch stress and ensure the epitaxy quality is a relatively large problem, and there are a large number of dislocation (mainly 60 DEG dislocation) to release the stress, and a three-dimensional island-shaped form to release the stress, wherein both forms can deteriorate the quality of the epitaxial film, and the key reasons are from the mismatched interface, namely the initial surface of Si (100), and the mode which is more prone to two-dimensional growth when Ge is epitaxially grown on the surface of Si (100) processed by us at low temperature, so that the quality of the large-mismatch heteroepitaxy is ensured. Meanwhile, conditions are provided for rearrangement of Ge atoms, and possibility is created for interface regulation and control.
(4) Germanium prepared by the method of the invention, whichThe surface is smooth, the roughness of the epitaxial germanium of the silicon (100) is 300-500pm, and the dislocation density is 10 9 cm -2 Reduced to 10 7 cm -2 。
(5) The method can directly grow the germanium virtual substrate on the silicon substrate in an epitaxial mode without growing in a layer-by-layer growth mode by gradually increasing the germanium content, so that the preparation process is simpler and the cost is lower.
(6) The method can treat most of 60 DEG dislocation in germanium, and a large number of dislocation (including 60 DEG dislocation) are annihilated at the interface by high-temperature in-situ annealing to form a periodic 90 DEG mismatching dislocation array, so that the stress is greatly released, the defect density of the germanium film is greatly reduced, and conditions are created for greatly improving the mobility.
Drawings
The invention may be better understood by reference to the following description of an embodiment of the invention, taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic structural view of a Ge/Si substrate of the present invention.
FIG. 2 is an AFM profile of a series of Ge/Si substrate surfaces that are not annealed and different annealing temperatures.
Fig. 3 shows a series of (224) space diagrams (RSM) of Ge/Si substrates corresponding to fig. 2.
FIG. 4 (a) is an XRD rocking curve (rocking curve) of a Ge film of a series of Ge/Si substrates that are not annealed and different annealing temperatures; FIG. 4 (b) shows a plan-view TEM image of a high temperature in situ annealed sample, with black circles framed out with threading dislocations.
FIG. 5 is a cross-sectional TEM view of (a) an as-grown Ge film directly epitaxially on an untreated Si (100) substrate, as obtained by the present invention; (b) A cross-sectional TEM image of a Ge film grown directly epitaxially on a Si (100) substrate with a high temperature in situ anneal process.
FIG. 6 is a graph of carrier mobility versus room temperature Hall test of Ge films of a series of Ge/Si substrates that were not annealed and different annealing temperatures.
Detailed Description
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. The illustrated example embodiments are presented for purposes of illustration only and are not intended to be limiting. Accordingly, the scope of the invention is not to be restricted by the following specific embodiments, but only by the scope of the appended claims.
The invention will now be described in further detail with reference to the drawings and to specific examples.
The invention provides a method for epitaxially growing germanium on a silicon substrate by molecular beam epitaxy and adopting in-situ annealing to treat Ge/Si interface and defects. The preparation method comprises the following steps:
first, a (100) crystal plane silicon substrate is subjected to surface treatment. And (3) transferring the silicon substrate subjected to hydrofluoric acid treatment into a cavity, keeping the substrate to rotate, and raising the temperature of a substrate heater to 500-600 ℃ for the silicon (100) substrate, and keeping the temperature for 5-10 minutes.
A 20-50nm thick silicon buffer layer is then grown on the treated silicon substrate by molecular beam epitaxy. The growth temperature of the silicon buffer layer on the silicon (100) substrate is 400-600 ℃. The purpose of the silicon buffer layer is to obtain a smoother surface and ensure the quality of the subsequent epitaxial film.
Germanium 500-600nm thick is then grown on the silicon buffer layer by molecular beam epitaxy. The growth temperature is 100-300 deg.C, and the growth rate is
Figure BDA0002467645780000051
The germanium source furnace is a thermal evaporation source furnace, and the growth rate of germanium is changed by changing the temperature of the source furnace.
And finally, carrying out in-situ annealing in the growth chamber, wherein the annealing temperature is higher than the growth temperature, the annealing temperature is 300-900 ℃, and the annealing time is 10-30min.
FIG. 1 is a prepared high mobility Ge/Si substrate, comprising a Si substrate, a Si buffer layer and a Ge film which are sequentially stacked, wherein the Ge film is grown on the Si buffer layer by an epitaxial method, the thickness of the Si buffer layer is 20-50nm, the thickness of the Ge film is 400-600nm, and the interface between the Ge film and the Si buffer layer is provided with periodically arranged 90 DEG misfit dislocation.
The hole mobility of the prepared Ge film is more than 1000cm 2 Vs up to 1300cm 2 Vs. The intrinsic germanium refers to germanium which is not artificially doped, and the carrier type is hole, so the mobility is the hole mobility of the intrinsic germanium.
FIG. 2 is an AFM topography of a series of Ge film surfaces that were not annealed and at different annealing temperatures, showing that the quality of the surface was not degraded after annealing, the Root Mean Square (RMS) roughness remained between 300 and 500pm, the RMS of the annealed samples differing by a maximum of 0.08nm from that of the unannealed samples, and the single layer (monolayer) of Ge was about 0.14nm, i.e., the distance the Ge atoms moved in the growth direction during annealing was not more than 1 monolayer overall, indicating to some extent indirectly that Ge atoms may be rearranged primarily in the direction of the interface, indicating that the interface would play a critical role.
Fig. 3 shows a (224) space map (RSM) of a series of Ge film samples corresponding to fig. 2, in-plane as well as out-of-plane lattice conditions of the Ge film can be well obtained along the [224] diffraction direction. Taking the inverted space of the unannealed sample as an example, we found that Ge (224) had a relatively pronounced broadening in the near in-plane direction, which is believed to be a "mosaic" structure caused by dislocations, the magnitude of which has a large relationship with dislocation density. When the sample is annealed in situ, it is found that this broadening is significantly reduced and becomes smaller as the annealing temperature increases. In our sample structure, because of the large mismatching heteroepitaxy, dislocation is mainly generated by mismatching, so after the annealing control interface releases mismatching stress, the related dislocations can also annihilate by mutual movement, so we observe that the broadening is smaller and smaller along with the increase of annealing temperature.
FIG. 4 (a) is an XRD rocking curve (rocking curve) of Ge films for a series of samples that were not annealed and different annealing temperatures; FIG. 4 (b) shows a plan-view TEM image of a high temperature in situ annealed sample, with black circles framed out with threading dislocations. There are two main types of defects within the epitaxial Ge film on Si: point defects and dislocations (mainly 60 ° dislocations). The previous section of the study of space inversion (RSM) mentions that the dislocation density decreases with annealing temperature, but this is only a qualitative analysis, which we need to quantitatively obtain The Dislocation Density (TDD) of Ge films. While research has long been conducted to find that the full width at half maximum (half maximum) and dislocation density (TDD) obtained by XRD rocking curve (swing curve) have a great relation with the specific calculation formula as follows:
D＝(β/3b) 2 (3.1)
where D is the dislocation density, β is the full width at half maximum (FWHM), and b is the Berth vector of the dislocation. Because of the predominantly 60 dislocation in the Ge film, the Bosch vector
Figure BDA0002467645780000061
。
From the swing cutting half width value of the Ge film tested in FIG. 4 (a), the Dislocation Density (TDD) can be calculated from the dislocation density of 6.26X10 before annealing 9 cm -2 Reduced to 7.36×10 7 cm -2 These 60 dislocation generating motions under the control of annealing eventually annihilate each other at the site of the point defect (vacancy), and the disappearance of a large number of defects (including 60 dislocation) after annealing can be observed from the sectional view of TEM as shown in fig. 5 (b). In addition to obtaining dislocation density (TDD) of Ge films by indirect calculation, the present invention also provides a plan-view of TEM, FIG. 4 (b) shows a plan-view TEM image of a high temperature in situ annealed sample, the sample size being about 6X6μm 2 The "pits" in the black boxes are threading dislocations, and The Dislocation Density (TDD) of the sample was estimated initially to be about 2X 10 7 cm -2 And the result of calculation according to XRD rocking curve was 7.62X10 7 cm -2 The dislocation density obtained by both methods is of the order of magnitude (-10) 7 cm -2 )。
Cross-sectional TEM images of direct epitaxial growth of germanium on untreated silicon (100) substrates and direct epitaxial growth of germanium on silicon (100) substrates with high temperature in situ annealing treatments are shown in fig. 5 (a) and (b), respectively. It can be seen from the comparison that there are a large number of defects (including 60 ° dislocations) in the untreated Ge interface and in the film, 60 ° dislocations being a mixed dislocation that occurs in the usual diamond-type lattice, and that it has an angle of 60 ° with the interface, and its component penetrates the surface of the film to form threading dislocations, affecting the quality of the film, which can be clearly observed under TEM. Obvious periodic arrangement of dislocation can be seen at the interface of the Ge film by adopting high-temperature in-situ annealing, the array of the periodic arrangement of the interface after the high-temperature annealing can be determined to be 90-degree mismatched dislocation by using a Bosch vector ring, the periodic interval of the 90-degree mismatched dislocation array (IMF) is 9.6nm and completely accords with the theoretical calculation result (9.57563 nm) in good correspondence with lattice mismatch of Si and Ge 4.1%, and the 90-degree mismatched dislocation formed in the Ge film releases stress caused by mismatch in an epitaxial film. Besides 90 DEG misfit dislocation, almost no defect comprising 60 DEG dislocation is observed near the Ge/Si interface, reflecting the fact that Ge atoms are rearranged from the interface after high-temperature in-situ annealing, so that 60 DEG dislocation annihilates and Ge island structures near the interface disappear. These conclusions reflect the very high feasibility of the process, which will provide a more powerful guarantee for the high performance of the related electronic devices of Ge/Si, while at the same time bringing great help to the development of silicon-based optoelectronics.
FIG. 6 is a graph showing the results of Hall electrical tests on various samples, illustrating that the silicon substrate of the present invention has a resistivity as high as 10,000 Ω cm, so that the results of the electrical tests of the present invention are all derived from germanium films. The sample was cut into 1X 1cm pieces 2 And electrodes coated with indium at four corners, the resistance was tested with a multimeter to ensure that the ohmic contact of the sample was good, then the electrode coated sample was placed on a sample holder and finally placed in a Hall system for testing by the van der waals method. It can be seen from FIG. 3 that the unannealed germanium film has a mobility of only 343cm 2 V.s, indicates that there are many electrical recombination centers and scattering centers in the film, which are mainly derived from dislocations, point defects, etc. in the film. For annealed samples, the mobility of 500 ℃ annealed germanium films is greatly improved because 500 ℃ annealing greatly reduces point defects while promoting annihilation of a large number of defects (including 60 DEG dislocations), resulting in large electrical recombination and scattering centers in the filmThe amount is reduced; the mobility of the germanium film has a saturation trend after the annealing temperature reaches 600 ℃, which indicates that the annihilation mechanism of the defect reaches the limit, the point defect in the film is reduced to the minimum, and the dislocation motion annihilation also reaches the limit; however, after the annealing reaches the high temperature of 700 ℃, the mobility of the germanium film is obviously improved again, and the phenomenon is explained by a TEM interface diagram of silicon and germanium in fig. 5, because interface atoms are rearranged to generate interface mismatch dislocation of 90 degrees, a periodic dislocation array is formed, 4% of mismatch stress between silicon and germanium lattices is released, 60-degree dislocation in the film and at the interface is almost eliminated, and the mobility of the germanium film is further improved. The research of the invention brings great help to the silicon-based photon integration which is limited by defects at present.
Although the exemplary embodiments have been described above in detail, the disclosed embodiments are exemplary only and not limiting, and those skilled in the art will readily appreciate that many other modifications, adaptations, and/or alternatives are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this disclosure. Accordingly, all such modifications, adaptations and/or alternatives are intended to be included within the scope of the present disclosure as defined in the following claims.

Claims (17)

1. A Ge/Si substrate comprising a Si substrate, a Si buffer layer and a Ge thin film sequentially stacked, the Ge thin film being grown on the Si buffer layer by an epitaxial method at a temperature of between 100 ℃ and 300 ℃, wherein the Ge thin film has a hole mobility of more than 1000cm 2 /Vs；
And the interface of the Ge film and the Si buffer layer is provided with a periodically arranged 90-degree mismatched dislocation array.
2. The Ge/Si substrate of claim 1, wherein the Ge thin film has a hole mobility of 1200-1300cm 2 /Vs。
3. The Ge/Si substrate of claim 1, wherein said Ge film comprises a Ge film having an atomically flat surface topography.
4. The Ge/Si substrate of claim 1, wherein said Ge film comprises threading dislocation density of 10 7 /cm 2 Magnitude or less than 10 7 /cm 2 Is a Ge film of (C).
5. The Ge/Si substrate of claim 1, wherein said Ge film has a thickness of less than 1 micron.
6. The Ge/Si substrate of claim 1, wherein said Ge film has a thickness of 400-600nm.
7. The Ge/Si substrate of claim 1, wherein a thickness of said Si buffer layer is less than 100nm.
8. The Ge/Si substrate of claim 1, wherein said Si buffer layer has a thickness of 20-50nm.
9. A method of preparing the Ge/Si substrate of claim 1, the method comprising:
step 1, obtaining a Si substrate with a (100) crystal face;
step 2, pretreating the Si substrate with the (100) crystal face by using a chemical reagent, and then carrying out surface treatment on the pretreated Si substrate with the (100) crystal face;
step 3, growing a layer of Si buffer layer on the Si substrate with the (100) crystal face after the surface treatment by a molecular beam epitaxy method;
step 4, directly epitaxially growing a Ge film on the Si buffer layer at a temperature of between 100 and 300 ℃;
step 5, carrying out in-situ annealing on the obtained Ge film;
and the interface of the Ge film and the Si buffer layer is provided with a periodically arranged 90-degree mismatched dislocation array.
10. The method of claim 9, wherein in step 2, the surface treatment is performed at a temperature between 500-600 ℃.
11. The method of claim 10, wherein the surface treatment is performed for a time period of 5-10 minutes.
12. The method of claim 9, wherein the Si buffer layer has a growth temperature of 400-700 ℃.
13. The method of claim 9, wherein the growth rate of the Ge film is
Figure FDA0004164104840000021
14. The method of claim 9, wherein the annealing temperature is 300 ℃ to 900 ℃.
15. The method of claim 9, wherein the annealing temperature is 500 ℃ -700 ℃.
16. The method of claim 9, wherein the annealing temperature is 700 ℃ -800 ℃.
17. The method of claim 9, wherein the annealing time is 10-30 minutes.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102315246A (en) * 2010-06-30 2012-01-11 中国科学院上海硅酸盐研究所 Relaxation SiGe virtual substrate and preparation method thereof
CN107316802A (en) * 2017-06-26 2017-11-03 南京大学 A kind of low-temperature epitaxy preparation method of high Ge content germanium-silicon thin membrane
CN109166788A (en) * 2018-08-29 2019-01-08 南京大学 A method of direct epitaxial growth Ge virtual substrate on a silicon substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102315246A (en) * 2010-06-30 2012-01-11 中国科学院上海硅酸盐研究所 Relaxation SiGe virtual substrate and preparation method thereof
CN107316802A (en) * 2017-06-26 2017-11-03 南京大学 A kind of low-temperature epitaxy preparation method of high Ge content germanium-silicon thin membrane
CN109166788A (en) * 2018-08-29 2019-01-08 南京大学 A method of direct epitaxial growth Ge virtual substrate on a silicon substrate

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