CN113555410A

CN113555410A - Display substrate and display device

Info

Publication number: CN113555410A
Application number: CN202110832637.7A
Authority: CN
Inventors: 晁晋予; 吴永凯; 史鲁斌; 谈耀宏; 孙文; 胡国仁; 李仁佑
Original assignee: BOE Technology Group Co Ltd; Mianyang BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Mianyang BOE Optoelectronics Technology Co Ltd
Priority date: 2021-07-22
Filing date: 2021-07-22
Publication date: 2021-10-26
Also published as: CN114335133A

Abstract

The invention provides a display substrate and a display device, relates to the technical field of display, and can ensure that a transistor in a sub-pixel driving circuit has good characteristics. The display substrate includes: a display area and a peripheral area surrounding the display area; the display substrate further includes: an adjustable signal output port located in the peripheral region; a plurality of sub-pixel driving circuits located in the display area; the sub-pixel driving circuit includes a first transistor including a channel region; an adjustment layer comprising a first portion and a second portion coupled, an orthographic projection of the first portion on a base of the display substrate at least partially overlapping with an orthographic projection of at least a portion of the channel region comprised by the sub-pixel drive circuit on the base; the second portion is coupled to the adjustable signal output port. The display substrate provided by the invention is used for displaying.

Description

Display substrate and display device

Technical Field

The invention relates to the technical field of display, in particular to a display substrate and a display device.

Background

With the continuous development of display technology, organic light emitting diode display panels and liquid crystal display panels are widely used in various fields.

Each sub-pixel in the display panel includes a sub-pixel driving circuit for supplying a driving signal to the light emitting element to drive the light emitting element to emit light, and the light emitting element. The sub-pixel driving circuit generally includes a driving transistor and a switching transistor, and the characteristics of these transistors directly affect the display effect of the display panel. Therefore, how to ensure that the transistors in the sub-pixel driving circuit have good characteristics is a problem to be solved in the art.

Disclosure of Invention

The invention provides a display substrate and a display device, which can ensure that a transistor in a sub-pixel driving circuit has good characteristics.

In order to achieve the above purpose, the invention provides the following technical scheme:

a first aspect of the present invention provides a display substrate comprising: a display area and a peripheral area surrounding the display area; the display substrate further includes:

an adjustable signal output port located in the peripheral region;

a plurality of sub-pixel driving circuits located in the display area; the sub-pixel driving circuit includes a first transistor including a channel region;

an adjustment layer comprising a first portion and a second portion coupled, an orthographic projection of the first portion on a base of the display substrate at least partially overlapping with an orthographic projection of at least a portion of the channel region comprised by the sub-pixel drive circuit on the base; the second portion is coupled to the adjustable signal output port.

Optionally, the first part includes:

a plurality of adjustment patterns, wherein the adjustment patterns correspond to at least part of the sub-pixel driving circuits one by one, and the orthographic projection of the adjustment pattern on the substrate at least partially overlaps with the orthographic projection of the channel region in the corresponding sub-pixel driving circuit on the substrate;

and a plurality of first conductive connecting parts, wherein adjacent adjusting patterns are coupled through at least one first conductive connecting part.

Optionally, the second part includes:

a first common connection including at least a portion extending in a first direction, the first common connection being coupled with the first portion;

at least one second conductive connection comprising at least a portion extending along a second direction, the second conductive connection being coupled with the first common connection and the adjustable signal output port, respectively.

Optionally, the second conductive connection portion includes:

at least two conductive subpatterns, wherein the at least two conductive subpatterns are arranged along the first direction; the conductive subpatterns are respectively coupled with the first common connection part and the adjustable signal output port;

a second common connection respectively coupled with the at least two conductive subpatterns.

Optionally, the first transistor includes a driving transistor and/or a data writing transistor.

Optionally, in a case that the first transistor includes the driving transistor and the data writing transistor, the display substrate includes two layers of the adjustment layers that are arranged in different layers; the adjustable signal output ports comprise a first adjustable signal output port and a second adjustable signal output port;

a first adjusting layer in the two adjusting layers comprises a first part which is orthographic projected on the substrate and at least partially overlapped with the orthographic projection of at least part of the channel region of the driving transistor on the substrate; the first adjustment layer includes a second portion coupled to the first adjustable signal output port;

the orthographic projection of a first part of a second adjusting layer in the two adjusting layers on the substrate at least partially overlaps with the orthographic projection of at least part of the channel region of the data writing transistor on the substrate; the second adjustment layer includes a second portion coupled to the second adjustable signal output port.

Optionally, an orthographic projection of the adjustment pattern included in the first portion of the first adjustment layer on the substrate does not overlap with an orthographic projection of the adjustment pattern included in the first portion of the second adjustment layer on the substrate.

Optionally, the adjusting layer is located on a side of the sub-pixel driving circuit facing the substrate.

Optionally, the display substrate further includes a driving chip, and the driving chip is coupled to the adjustable signal output port.

Optionally, the adjustable signal output port is located in a lighting test port setting area included in the peripheral area.

Optionally, the adjustment layer is made of a metal material or a semiconductor material.

Optionally, the display substrate further includes a power layer, and the power layer is insulated from the adjusting layer.

Based on the technical solution of the display substrate, a second aspect of the invention provides a display device, which includes the display substrate.

In the technical scheme provided by the invention, the voltage value of the adjusting signal transmitted by the adjusting layer can be set according to needs, and various characteristics (such as Vth/Mob/Ion/Dr range) of the first transistor can be adjusted and controlled, so that the defects caused by the characteristics of the transistor and characteristic deviation caused by unstable factory process are effectively improved, and meanwhile, the optical characteristics of the display substrate can be adjusted and improved by adjusting the characteristics of the transistor, and the display effect of the display substrate under different optical characteristics such as brightness, chromaticity and the like is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is a diagram illustrating a relationship between a voltage value of an adjustable signal and a threshold voltage of a driving transistor according to an embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating a relationship between a voltage value of an adjustable signal and a mobility of a driving transistor according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating a relationship between a voltage value of an adjustable signal and an on-current of a driving transistor according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a relationship between a voltage level of an adjustable signal and a voltage threshold swing of a driving transistor according to an embodiment of the present invention;

FIG. 5 is a first layout diagram of the adjustment layer and the power layer according to the embodiment of the invention;

FIG. 6 is a schematic view of the layout of the conditioning layer of FIG. 5;

FIG. 7 is a layout diagram of the power plane in FIG. 5;

FIG. 8 is a second layout diagram of the adjustment layer and the power layer according to the embodiment of the invention;

FIG. 9 is a schematic layout view of the second adjustment layer of FIG. 8;

fig. 10 is a third layout diagram of the adjustment layer and the power layer according to the embodiment of the invention.

Detailed Description

In order to further explain the display substrate and the display device provided by the embodiments of the present invention, the following detailed description is made with reference to the accompanying drawings.

Referring to fig. 5 and 6, an embodiment of the invention provides a display substrate, including: a display area and a peripheral area surrounding the display area; the display substrate further includes:

an adjustable signal output port 1, wherein the adjustable signal output port 1 is located in the peripheral area;

an adjustment layer 2, the adjustment layer 2 comprising a first portion 20 and a second portion 21 coupled to each other, an orthographic projection of the first portion 20 on a base of the display substrate at least partially overlapping an orthographic projection of at least a part of the channel region comprised by the sub-pixel driving circuit on the base; the second portion 21 is coupled to the adjustable signal output port 1.

Illustratively, the adjustable signal output port 1 can output an adjustable signal with an adjustable voltage value.

Illustratively, the sub-pixel driving circuit includes a 7T1C circuit (i.e., including 7 transistors and 1 capacitor), a 3T1C circuit (i.e., including 3 transistors and 1 capacitor), and so on.

Illustratively, the plurality of sub-pixel driving circuits are distributed in an array in the display area.

Illustratively, the sub-pixel driving circuit comprises a first transistor, which can be selected as a transistor with a driving function, and/or a transistor with a switching function.

Illustratively, the first transistor includes an active layer and a base gate. The basic grid is made of a grid metal layer. The active layer includes a channel portion forming the channel region, and an orthographic projection of the base gate on the substrate covers an orthographic projection of the channel region on the substrate.

Illustratively, the adjustment layer 2 includes a first portion 20 and a second portion 21 formed as a unitary structure.

Illustratively, an orthographic projection of the first portion 20 on a base of the display substrate at least partially overlaps with an orthographic projection of the channel region on the base included in all of the sub-pixel driving circuits.

Illustratively, the orthographic projection of the first portion 20 on the base of the display substrate covers the orthographic projection of the channel region on the base of all the sub-pixel driving circuits.

Illustratively, the second portion 21 is coupled to the adjustable signal output port 1, and the second portion 21 is capable of transmitting an adjustable signal received from the adjustable signal output port 1 to the first portion 20. The first part 20 can act as an auxiliary gate for the first transistor, and by controlling the voltage value of the adjustable signal, adjustment of the characteristics of the first transistor can be achieved.

It should be noted that the first transistor is formed as a double gate structure, and the gate thereof includes the base gate and the auxiliary gate. The first transistor is capable of operating under common control of the base gate and the auxiliary gate.

It has been found that the characteristics of the first transistor, such as: the threshold voltage Vth, the mobility Mob, the on-current Ion, the voltage threshold swing Dr range, etc. may directly affect the display effect of the display product. The characteristics of the first transistor must be within the required specifications to achieve the display requirements. The characteristic problems of the first transistor, which are common at present, include: display bright and dark dot problems due to Vth shift; the problem that pixels cannot be lighted when Ion is small; too small Mob results in disadvantages such as slow response speed.

By controlling the Voltage (BSM Voltage) of the adjustable signal transmitted on the adjustment layer 2, the characteristic parameters of the first transistor can be well adjusted. Illustratively, the voltage of the tunable signal varies from-5V to +5V, and the Vth/Mob/Ion of the first transistor decreases with linearity, as shown in fig. 1 to 3; while the Dr range parameter increases linearly as shown in fig. 4. In terms of product characteristics, the adjustment of the characteristics of the first transistor by the adjustment layer 2 can bring about improvement of optical characteristics such as display uniformity, afterimage, Flicker (Flicker), and the like. In addition, after the adjusting layer 2 is arranged in the display substrate, the afterimage level of the display substrate is reduced from 7 JNCCD of 0s to 3 JNCCD, and the improvement effect is remarkable.

Note that fig. 1 to 4 show the relationship between the BSM Voltage and the characteristic parameter of the driving transistor DTFT. x represents BSM Voltage, y represents ordinate, R²Representing the degree of fit, values close to 1 indicate a good fit. The dotted line is the fitted curve.

As can be seen from the specific structure of the display substrate, in the display substrate provided in the embodiment of the present invention, the voltage value of the adjustment signal transmitted by the adjustment layer 2 can be set as required, so as to adjust and control various characteristics (e.g., Vth/Mob/Ion/Dr range) of the first transistor, thereby effectively improving the defects caused by the transistor characteristics and the characteristic shift caused by the unstable factory process, and adjusting and improving the optical characteristics of the display substrate by adjusting the transistor characteristics, so as to improve the display effect of the display substrate under different optical characteristics, such as luminance and chromaticity.

As shown in fig. 5, 6, 8 and 9, in some embodiments, the first portion 20 includes:

a plurality of adjustment patterns 201, wherein the adjustment patterns 201 correspond to at least some of the sub-pixel driving circuits one to one, and the orthographic projection of the adjustment pattern 201 on the substrate at least partially overlaps the orthographic projection of the channel region in the corresponding sub-pixel driving circuit on the substrate;

a plurality of first conductive connection portions 202, adjacent to the adjustment patterns 201 being coupled by at least one of the first conductive connection portions 202.

Illustratively, the plurality of adjustment patterns 201 are distributed in an array. The plurality of adjustment patterns 201 correspond to all the sub-pixel driving circuits one to one. The orthographic projection of the adjusting graph 201 on the substrate at least partially overlaps the orthographic projection of the channel region in the corresponding sub-pixel driving circuit on the substrate. Illustratively, the orthographic projection of the adjustment pattern 201 on the substrate covers the orthographic projection of the channel region in the corresponding sub-pixel driving circuit on the substrate.

Illustratively, the adjustment pattern 201 and the first conductive connection portion 202 are both of a rectangular design.

Illustratively, the plurality of adjustment patterns 201 are divided into a plurality of rows of adjustment patterns 201 and a plurality of columns of adjustment patterns 201, the plurality of rows of adjustment patterns 201 are arranged along a second direction, each row of adjustment patterns 201 includes a plurality of adjustment patterns 201 arranged along a first direction, and the second direction intersects with the first direction. The plurality of columns of adjustment patterns 201 are arranged along a first direction, and each column of adjustment patterns 201 includes a plurality of adjustment patterns 201 arranged along a second direction.

Illustratively, the second direction comprises a vertical direction and the first direction comprises a lateral direction.

Illustratively, the adjustment patterns 201 adjacent to each other in the second direction are coupled to each other by at least one of the first conductive connection portions 202, and the adjustment patterns 201 adjacent to each other in the first direction are coupled to each other by at least one of the first conductive connection portions 202.

Illustratively, in the adjustment pattern 201 and the first conductive connection portion 202 which are located in the same column along the second direction, the width of the adjustment pattern 201 is larger than the width of the first conductive connection portion 202 in a direction parallel to the substrate and in a direction perpendicular to the second direction.

Illustratively, in the adjustment pattern 201 and the first conductive connection portion 202 which are located in the same row along the first direction, the width of the adjustment pattern 201 is larger than the width of the first conductive connection portion 202 in a direction parallel to the substrate and in a direction perpendicular to the first direction.

Illustratively, an orthographic projection of the first conductive connection portion 202 on the substrate does not overlap with an orthographic projection of the channel region on the substrate.

As shown in fig. 5 and 6, the first portion 20 further includes a third common connection portion 203, the third common connection portion 203 and the first common connection portion 210 are oppositely disposed along the second direction, and the third common connection portion 203 and the first common connection portion 210 are respectively located at two opposite sides of the display area.

In the display substrate provided in the above embodiment, by providing that the first portion 20 includes the plurality of adjustment patterns 201 and the plurality of first conductive connection portions 202, the first portion 20 can be formed into a grid-like structure laid out in the whole display area, and the parasitic capacitance generated between the first portion 20 and other structures in the display substrate is effectively reduced while the characteristics of each first transistor are adjusted.

As shown in fig. 5 and 6, in some embodiments, providing the second portion 21 includes:

a first common connection 210, the first common connection 210 including at least a portion extending in a first direction, the first common connection 210 being coupled with the first portion 20;

at least one second electrically conductive connection 211, said second electrically conductive connection 211 comprising at least a portion extending in a second direction, said second electrically conductive connection 211 being coupled to said first common connection 210 and to said adjustable signal output port 1, respectively.

Illustratively, the first common connection 210 is coupled to a plurality of first conductive connections 202 included in the first portion 20.

Illustratively, the second portion 21 includes at least two second conductive connection portions 211, the at least two second conductive connection portions 211 are arranged along the first direction, and the at least two second conductive connection portions 211 are respectively coupled to the first common connection portion 210.

Illustratively, the display substrate includes the adjustable signal output ports 1 corresponding to the second conductive connection portions 211 one by one, and the second conductive connection portions 211 are coupled to the corresponding adjustable signal output ports 1.

The above arrangement is advantageous for the uniformity of the adjustment signal transmitted by the adjustment layer 2.

As shown in fig. 5 and 6, in some embodiments, providing the second conductive connection 211 includes:

at least two conductive subpatterns 2110, wherein the at least two conductive subpatterns 2110 are arranged along the first direction; the conductive subpattern 2110 is coupled to the first common connection 210 and the adjustable signal output port 1 respectively;

second common connection portions 2111, the second common connection portions 2111 being coupled to the at least two conductive subpatterns 2110, respectively.

Illustratively, the at least two conductive subpatterns 2110 are arranged at intervals along the first direction.

Illustratively, at least two conductive sub-patterns 2110 included in the same second conductive connection portion 211 are connected to the same corresponding adjustable signal output port 1.

Illustratively, the second common connection portion 2111 is formed as an integral structure with the at least two conductive subpatterns 2110.

The arrangement mode not only can ensure the electrical connection performance of the first part 20 with the adjustable signal output port 1 through the second conductive connecting part 211, but also is beneficial to improving the reliability of the second conductive connecting part 211. That is, when one conductive sub-pattern 2110 is broken, the other conductive sub-patterns 2110 can still realize normal electrical connection.

In some embodiments, the first transistor includes a driving transistor and/or a data writing transistor.

Illustratively, the driving transistor is configured to generate a driving signal for driving the light emitting element to emit light, and is capable of transmitting the driving signal to the light emitting element.

Illustratively, the data writing transistor is coupled to a corresponding data line in the display substrate, and is configured to receive a data signal provided by the data line and transmit the data signal to the driving transistor.

Illustratively, the first transistor may include a plurality of transistors.

The first transistor comprises the driving transistor and/or the data writing transistor, so that the characteristics of the driving transistor and/or the data writing transistor can be effectively regulated and controlled, and the working stability and the display effect of the display substrate are improved.

As shown in fig. 6 to 9, in some embodiments, in the case where the first transistor includes the driving transistor and the data writing transistor, the display substrate includes two layers of the adjustment layer 2 disposed in different layers; the adjustable signal output port 1 comprises a first adjustable signal output port and a second adjustable signal output port;

a first adjusting layer 2a of the two adjusting layers 2 comprises a first part 20 which is orthographically projected on the substrate and at least partially overlapped with the orthographically projected part of the channel region of the driving transistor on the substrate; the first adjusting layer 2a comprises a second portion 21 coupled to the first adjustable signal output port;

the second adjusting layer 2b of the two adjusting layers 2 comprises a first part 20 which is orthographically projected on the substrate and at least partially overlapped with the orthographically projected channel region of the data writing transistor on the substrate; the second adjusting layer 2b comprises a second portion 21 coupled to the second tunable signal output port.

Note that the range outlined by a dotted line in fig. 5 and 8 is a layout area of one sub-pixel driving circuit. The area of the adjustment graph 201 can be set according to actual needs. The adjustment pattern 201 may overlap with only a channel region of one transistor, or may overlap with channel regions of at least two transistors.

Illustratively, the set number of first adjustable signal output ports includes at least one.

Illustratively, the set number of second adjustable signal output ports includes at least one.

Illustratively, the first adjustment layer 2a includes a first portion 20 having an orthogonal projection on the substrate that at least partially overlaps with an orthogonal projection of all of the channel regions of the driving transistors on the substrate.

Illustratively, the first adjustment layer 2a includes a first portion 20 that is orthographically projected onto the substrate, covering all of the channel regions of the driving transistors.

Illustratively, the second adjustment layer 2b comprises an orthographic projection of the first portion 20 on said substrate at least partially overlapping an orthographic projection of all channel regions of said data writing transistors on said substrate.

Illustratively, the second adjustment layer 2b comprises an orthographic projection of the first portion 20 on said substrate, covering the orthographic projection of the channel region of all of said data writing transistors on said substrate.

In the display substrate provided in the above embodiment, the voltage value of the adjustment signal transmitted by the first adjustment layer 2a may be set as required, so as to adjust and control various characteristics (e.g., Vth/Mob/Ion/Dr range) of the driving transistor, thereby effectively improving the defects caused by the characteristics of the driving transistor and the characteristic shift caused by the unstable factory process, and simultaneously adjusting and improving the optical characteristics of the display substrate by adjusting the characteristics of the driving transistor, so as to improve the display effect of the display substrate under different optical characteristics, such as luminance and chromaticity.

In the display substrate provided in the above embodiment, the voltage value of the adjustment signal transmitted by the second adjustment layer 2b may be set as required, so as to adjust and control various characteristics (e.g., Vth/Mob/Ion/Dr range) of the data writing transistor, thereby effectively improving the defects caused by the characteristics of the data writing transistor and the characteristic shift caused by the unstable factory process, and simultaneously adjusting and improving the optical characteristics of the display substrate by adjusting the characteristics of the data writing transistor, so as to improve the display effect of the display substrate under the optical characteristics of different brightness, chromaticity, and the like.

In the display substrate provided by the above embodiment, by providing the two adjustment layers 2 including different layers, it is possible to individually adjust and control characteristics of the driving transistor and the data writing transistor.

In some embodiments, the first regulation layer 2a is coupled with the second regulation layer 2 b.

For example, the first adjustment layer 2a and the second adjustment layer 2b are coupled by a via at an upper frame and/or a lower frame of the display substrate.

Exemplarily, the first adjusting layer 2a and/or the second adjusting layer 2b are coupled to the power layer 3.

Exemplarily, an orthographic projection of the first adjusting layer 2a on the substrate, and/or an orthographic projection of the second adjusting layer 2b on the substrate, and an orthographic projection of the power supply layer 3 on the substrate at least partially overlap. Therefore, the transmittance of the display substrate can be effectively improved.

As shown in fig. 6 to 9, in some embodiments, an orthographic projection of the adjustment pattern 201 included in the first portion 20 of the first adjustment layer 2a on the substrate is arranged not to overlap with an orthographic projection of the adjustment pattern 201 included in the first portion 20 of the second adjustment layer 2b on the substrate.

The arrangement mode reduces the parasitic capacitance generated between the adjusting pattern 201 in the first adjusting layer 2a and the adjusting pattern 201 in the second adjusting layer 2b, and is beneficial to improving the working performance of the display substrate.

In some embodiments, the adjustment layer 2 is located on the side of the sub-pixel driving circuit facing the substrate, as shown in fig. 5 and 8.

Illustratively, the adjustment layer 2 is located between the active layer and the substrate.

Illustratively, the base includes a first PI (polyimide) substrate and a second PI substrate that are stacked, and the adjustment layer 2 is located between the first PI substrate and the second PI substrate.

Exemplary, the display substrate includes a first isolation layer (Barrier layer) and a second isolation layer between the substrate and the active layer, the first isolation layer is stacked with the second isolation layer, and the adjustment layer 2 is between the first isolation layer and the second isolation layer.

The adjusting layer 2 is arranged on one side, facing the substrate, of the sub-pixel driving circuit, so that the risk of short circuit between the adjusting layer 2 and a conducting layer in the sub-pixel driving circuit is reduced, and the stability and the reliability of the display substrate are effectively improved.

As shown in fig. 5 and 8, in some embodiments, the display substrate further includes a driving chip coupled to the adjustable signal output port 1.

Illustratively, the display substrate includes a bonding area, and the adjustable signal output port 1 is located in the bonding area.

Illustratively, the driving chip is coupled to the adjustable signal output port 1, and the driving chip is capable of providing an adjustable signal with adjustable voltage for the adjustable signal output port 1 alone.

The driving chip is coupled to the adjustable signal output port 1, so that the display substrate can control the adjustable signal through the driving chip before and after leaving the factory, and the performance of the transistor can be adjusted.

As shown in fig. 5 and 8, in some embodiments, the adjustable signal output port 1 is located in a lighting test port setting area included in the peripheral area.

In an exemplary embodiment, the peripheral area includes a lighting test port setting area, and the lighting test port is provided with a lighting test signal when a lighting test is performed on the display substrate.

Illustratively, the adjustable signal output port 1 is located in the lighting test port setting area, and may provide an independent adjustable signal for the adjustable signal output port 1 in the lighting test stage.

In some embodiments, the adjustment layer 2 is made of a metal material or a semiconductor material.

Illustratively, the display substrate includes a light shielding layer, and the adjustment layer 2 and the light shielding layer are disposed in the same layer and material. The arrangement mode enables the adjusting layer 2 and the light shielding layer to be formed simultaneously in the same composition process, thereby being beneficial to simplifying the manufacturing process flow of the display substrate and reducing the manufacturing cost of the display substrate.

Illustratively, the adjusting layer 2 is made of Si or Mo.

The adjusting layer 2 is made of the metal material or the semiconductor material, so that the performance of transmitting an adjusting signal by the adjusting layer 2 is ensured, and the adjusting effect on the characteristics of the transistor is also ensured.

As shown in fig. 5 to 7, in some embodiments, the display substrate further includes a power layer 3, and the power layer 3 is insulated from the adjustment layer 2.

Illustratively, the power layer 3 is made of a source-drain metal layer in the display substrate.

Illustratively, the power supply layer 3 is arranged in a different layer from the adjustment layer 2.

The power supply layer 3 and the adjusting layer 2 are insulated, so that the potential of the adjusting layer 2 is prevented from being fixed, and the adjusting effect of the adjusting layer 2 on the characteristics of the transistor is ensured.

Referring to fig. 10, in some embodiments, the adjusting layer 2 is disposed to be coupled to the power layer 3.

Illustratively, an orthographic projection of the adjusting layer 2 on the substrate and an orthographic projection of the power supply layer 3 on the substrate have an overlapping area, the adjusting layer 2 and the power supply layer 3 are coupled through a Via, and the orthographic projection of the Via on the substrate is located in the overlapping area.

Illustratively, the Via is located at an upper frame and/or a lower frame of the display substrate. Illustratively, the Via is located at other positions of the display substrate besides the upper frame and the lower frame.

The arrangement mode enables the adjusting layer 2 to be provided with signals by the power supply layer 3, and effectively saves the cost of driving an IC.

The embodiment of the invention also provides a display device which comprises the display substrate provided by the embodiment.

The display device may be: the display device comprises a television, a display, a digital photo frame, a mobile phone, a tablet personal computer and any other product or component with a display function, wherein the display device further comprises a flexible circuit board, a printed circuit board, a back plate and the like.

In the display substrate provided in the above embodiment, the voltage value of the adjustment signal transmitted by the adjustment layer may be set as required, so as to adjust and control various characteristics (e.g., Vth/Mob/Ion/Dr range) of the first transistor, thereby effectively improving the defects caused by the transistor characteristics and the characteristic shift caused by the unstable factory process, and simultaneously adjusting and improving the optical characteristics of the display substrate by adjusting the transistor characteristics, so as to improve the display effect of the display substrate under different optical characteristics, such as luminance, chromaticity, and the like.

The display device provided by the embodiment of the invention has the beneficial effects when the display device comprises the display substrate, and the description is omitted.

It should be noted that "same layer" in the embodiments of the present invention may refer to a film layer on the same structural layer. Or, for example, the film layer on the same layer may be a layer structure formed by forming a film layer for forming a specific pattern by using the same film forming process and then patterning the film layer by using the same mask plate through a one-time patterning process. Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

In the embodiments of the methods of the present invention, the sequence numbers of the steps are not used to limit the sequence of the steps, and for those skilled in the art, the sequence of the steps is not changed without creative efforts.

It should be noted that, in the present specification, all the embodiments are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the method embodiments, since they are substantially similar to the product embodiments, they are described simply, and reference may be made to the partial description of the product embodiments for relevant points.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected," "coupled," or "connected," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A display substrate, comprising: a display area and a peripheral area surrounding the display area; the display substrate further includes:

an adjustable signal output port located in the peripheral region;

2. The display substrate of claim 1, wherein the first portion comprises:

3. The display substrate of claim 1, wherein the second portion comprises:

4. The display substrate according to claim 3, wherein the second conductive connection portion comprises:

5. The display substrate according to claim 1, wherein the first transistor comprises a driving transistor and/or a data writing transistor.

6. The display substrate according to claim 5, wherein in a case where the first transistor includes the driving transistor and the data writing transistor, the display substrate includes two layers of the adjustment layer which are provided in different layers; the adjustable signal output ports comprise a first adjustable signal output port and a second adjustable signal output port;

7. The display substrate according to claim 6, wherein an orthographic projection of the adjustment pattern included in the first portion in the first adjustment layer on the substrate does not overlap with an orthographic projection of the adjustment pattern included in the first portion in the second adjustment layer on the substrate.

8. The display substrate of claim 1, wherein the adjustment layer is located on a side of the sub-pixel driving circuit facing the substrate.

9. The display substrate of claim 1, further comprising a driver chip coupled to the adjustable signal output port.

10. The display substrate according to claim 1, wherein the adjustable signal output port is located in a lighting test port setting area included in the peripheral area.

11. The display substrate of claim 1, wherein the adjustment layer is made of a metal material or a semiconductor material.

12. The display substrate of claim 1, further comprising a power layer, wherein the power layer is insulated from the adjustment layer.

13. A display device comprising the display substrate according to any one of claims 1 to 12.