CN113555381A - Magnetic random access memory array and semiconductor device - Google Patents

Magnetic random access memory array and semiconductor device Download PDF

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Publication number
CN113555381A
CN113555381A CN202010335025.2A CN202010335025A CN113555381A CN 113555381 A CN113555381 A CN 113555381A CN 202010335025 A CN202010335025 A CN 202010335025A CN 113555381 A CN113555381 A CN 113555381A
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source
array
random access
access memory
magnetic random
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吴巍
徐征
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Fujian Jinhua Integrated Circuit Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

The invention provides a magnetic random access memory array and a semiconductor device, which can effectively utilize the area space of a substrate by the layout mode of a plurality of active regions extending along a third direction and a plurality of word lines extending along a second direction on the premise of occupying the same substrate area, realize the characteristic size of a smaller memory cell and higher memory density, and have lower chip cost. Further, a cell area of 4F can be achieved2And (F is a characteristic size) close-packed storage array, so that the storage density and the device integration level are improved.

Description

Magnetic random access memory array and semiconductor device
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a magnetic random access memory array and a semiconductor device.
Background
Magnetic Random Access Memory (MRAM) is a new Memory and storage technology, can be read and written randomly as fast as SRAM/DRAM, and can permanently retain data after power off as Flash Memory. Each MRAM memory cell consists of one magnetic tunnel junction and one MOS transistor, and may also consist of two magnetic tunnel junctions and two MOS transistors. Each memory cell needs to be connected to three wires: the grid electrode of the MOS tube is connected to a word line of the chip and is responsible for switching on or switching off the unit; one pole (source or drain) of the MOS transistor is connected to the source line, the other pole (drain or source) of the MOS transistor is connected to one pole of the magnetic tunnel junction, and the other pole of the magnetic tunnel junction is connected to the bit line.
As MRAM technology continues to advance, how to make MRAM memory cells smaller to increase MRAM density has become one of the technical problems that those skilled in the art are demanding to solve.
Disclosure of Invention
It is an object of the present invention to provide a magnetic random access memory array and a semiconductor device that can have a reduced memory cell area and an increased memory density.
To solve the above technical problem, the present invention provides a magnetic random access memory array, comprising:
the semiconductor device comprises a semiconductor substrate, a plurality of strip-shaped active regions arranged along a first direction and a second direction are arranged in the semiconductor substrate, each active region extends along a third direction, the second direction is vertical to the first direction, and the third direction is intersected with the first direction and the second direction;
the word lines are arranged on the semiconductor substrate along a first direction, extend along a second direction and cross over the active regions, and divide the corresponding active regions into a source region and a drain region;
a plurality of source lines, each formed through the first metal layer and connected to the corresponding source region;
and each magnetic tunnel junction is connected with the corresponding drain region at the bottom through the corresponding second metal layer, and is connected with a third metal layer at the top, and the third metal layer is used for forming a corresponding bit line.
Optionally, each active region and the word line disposed above the active region form a corresponding MOS transistor, and the corresponding MOS transistor formed at the active region and the corresponding magnetic tunnel junction above the drain region constitute one memory cell.
Optionally, each memory cell has only one MOS transistor at least.
Optionally, the source region and the drain region of the MOS transistor of each memory cell except the memory cell on the array boundary of the magnetic random access memory array are shared with the surrounding adjacent memory cells, and the area of each memory cell is 4F2Wherein F is the feature size.
Optionally, each drain region is connected to the second metal layer at the bottom of the magnetic tunnel junction through a drain contact plug located above the drain region, and each source region is connected to the source line through a source contact plug located above the source region; the drain contact plugs and the source contact plugs are arranged in rows and columns into an array of plugs.
Optionally, the row direction of the plug array is the first direction, the column direction of the plug array is the second direction, and a row of the source contact plugs is sandwiched between two rows of the drain contact plugs.
Optionally, the bit line and the source line are arranged in parallel, or the bit line and the source line are arranged in an out-of-plane intersecting manner.
Optionally, the bit line intersects the word line at an angle, or the bit line intersects the word line at an angle that is not perpendicular.
Optionally, the included angle between the first direction and the third direction includes, but is not limited to, 45 degrees.
Based on the same inventive concept, the invention also provides a semiconductor device comprising the magnetic random access memory array.
Compared with the prior art, the magnetic random access memory array and the semiconductor device with the magnetic random access memory array have the following beneficial effects:
1. on the premise of occupying the same substrate area, the layout mode of a plurality of active regions extending along the first direction and a plurality of word lines extending along the second direction can effectively utilize the substrate area space, realize the characteristic size of a smaller storage unit and higher storage density, and the chip cost is lower.
2. Can realize the unit area of 4F2And (F is a characteristic size) close-packed storage array, so that the storage density and the device integration level are improved.
3. The source lines and the bit lines are perpendicular to the word lines, and the projections of the source lines and the bit lines are not overlapped, so that the distance between two adjacent bit lines or between two source lines is increased, the manufacturing difficulty of the source lines, the bit lines, the drain contact plugs and the source contact plugs is reduced, the interference between adjacent storage units can be reduced, and the device performance is improved.
Drawings
Fig. 1 is a schematic diagram of a layout structure of a magnetic random access memory array according to an embodiment of the present invention (structures such as bit lines BL and source lines SL are omitted);
FIG. 2 is a schematic layout of source and bit lines of a magnetic random access memory array in accordance with an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view taken along line XX' in the MRAM array of FIG. 2 (with the interlayer dielectric layer and other structures omitted, and with the source and bit lines parallel and longitudinally non-overlapping);
FIG. 4 is a schematic cross-sectional view taken along line XX' in the MRAM array of FIG. 2 (with the interlevel dielectric layer and the like omitted, and with the source and bit lines overlapping in the longitudinal direction, and possibly intersecting in opposite planes);
FIG. 5 is a schematic diagram of another layout of source lines and bit lines of a magnetic random access memory array in accordance with an embodiment of the present invention.
Detailed Description
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. As used herein, "and/or" means either or both.
Referring to fig. 1 to 3, an embodiment of the invention provides a magnetic random access memory array including a semiconductor substrate 100, a plurality of word lines WL, a plurality of source lines SL, a plurality of magnetic tunnel junctions 106, and a plurality of bit lines BL.
The semiconductor substrate 100 may be a silicon substrate, a germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like. The semiconductor substrate 100 may be implanted with impurities to form the active region 101, and the impurities may include n-type impurities such as phosphorus, arsenic, or the like, or p-type impurities such as boron, gallium, or the like. The space between adjacent active regions 101 is a field region (not shown), which may be formed by a Shallow Trench Isolation (STI) process or a local field oxide isolation (LOCOS) process.
In this embodiment, a plurality of active regions 101 are formed in the semiconductor substrate 100, all the active regions 101 are in a stripe shape, and may be arranged along a first direction and a second direction that are perpendicular to each other, a length of the active region 101 extends along a third direction, the third direction intersects with both the first direction and the second direction, and an included angle between the third direction and the first direction includes, but is not limited to, 45 degrees, that is, may also be 45 degrees, or may not be 45 degrees. All the active regions 101 are arranged in an array, wherein each active region 101 may extend continuously in the third direction to the entire third direction length of the corresponding semiconductor substrate 100 or may be disconnected in some regions, thereby forming a plurality of active region 101 blocks aligned in the first direction and the second direction.
A plurality of word lines WL are arranged along a first direction and formed on the semiconductor substrate 100, and each of the word lines WL extends along a second direction perpendicular to the first direction and straddles the plurality of active regions 101. Each of the word lines WL divides the corresponding active region 101 into a source region 101a and a drain region 101 b. Each active region 101 and the corresponding word line WL arranged above the active region 101 form a corresponding MOS transistor, that is, the word line WL serves as a gate of the MOS transistor, the active regions 101 on both sides of the word line WL are a source region 101a and a drain region 101b of the MOS transistor, respectively, and the active region 101 covered by the word line WL is a channel region of the MOS transistor. The word line WL may be made of polysilicon or a metal gate, a gate dielectric layer (not shown) is further disposed between the word line WL and the semiconductor substrate 100, and a Spacer (not shown) may be further formed on the SideWall of the word line WL. The line width of the word line WL may be equal to or less than the column pitch of the plug array formed by the source contact plug and the drain contact plug, so as to avoid interference between memory cells caused by overlapping the word line WL with other active regions 101, which affects device performance.
Several source lines SL are formed through the first metal layer 103 and connected to the corresponding source regions 101a through the corresponding source contact plugs 102.
The bottom of each Magnetic Tunnel Junction (MTJ)106 is connected to the corresponding drain region 101b through the corresponding second metal layer 105 and the drain contact plug 104 under the second metal layer 105, and the top of each magnetic tunnel junction 106 is connected to a third metal layer 107, and the third metal layer 107 is used for forming the corresponding bit line BL. The MTJ 106 is only formed on the drain region of the MOS transistor connected to the bit line BL, the MOS transistor formed in each active region 101 and the magnetic tunnel junction 106 above the active region 101 form a memory cell (as shown by a dashed line in fig. 1), and the area of each memory cell is 2F × 2F — 4F2. The source contact plug 102, the drain contact plug 104, the first metal layer 103, the second metal layer 105, and the third metal layer 107 may each include a metal and/or a metal nitride. All of the source contact plugs 102 and the drain contact plugs 104 are arranged in a plug array in rows and columns, the row direction of the plug array being a first direction perpendicular to a second direction, and the column direction of the plug array being the second direction, thereby causing the magnetic tunnel junctions 106 to be arranged in a corresponding array in the layout of the plug array.
The magnetic tunnel junction 106 may include a barrier layer (not shown), which may reduce or prevent abnormal growth of metals in the pinning layer, the lower ferromagnetic layer, the ferromagnetic coupling spacer layer, the upper ferromagnetic layer, and the like, which are sequentially formed on the second metal layer 105, a pinning layer, a lower ferromagnetic layer, an antiferromagnetic coupling spacer layer, an upper ferromagnetic layer, and the like, and the barrier layer may include an amorphous metal or metal nitride, such as tantalum, tantalum nitride, titanium nitride, and the like. The pinning layer may include, for example, FeMn, IrMn, PtMn, MnO, MnS, MnTe, MnF2、FeF2、FeCl2、FeO、CoCl2、CoO、NiCl2NiO, Cr, etc. The lower and upper ferromagnetic layers may comprise, for example, Fe, Ni, Co, or the like. The antiferromagnetic coupling spacer layer can include, for example, Ru, Ir, Rh, or the like. The lower ferromagnetic layer may have a fixed or "pinned" magnetic orientation, while the upper ferromagnetic layer has a variable or "free" magnetic orientation and may be switched between two or more different magnetic polarities, each representing a different data state, such as a different binary state. However, in other implementations, the MTJ 106 may be "flipped" vertically such that the lower ferromagnetic layer has a "free" magnetic orientation and the upper ferromagnetic layer has a "fixed" magnetic orientation.
Referring to fig. 3, in the embodiment, the bit line BL and the source line SL are arranged in parallel, metal layers where the bit line BL and the source line SL are located are not overlapped at all, the bit line BL sequentially passes through the magnetic tunnel junction 106, the second metal layer 105, and the drain contact plug 104 to contact the drain region 101b, and the source line SL contacts the source region 101a through the source contact plug 102. All the drain contact plugs 104 and the source contact plugs 102 are arranged in a plug array along a first direction and a second direction, please refer to fig. 1 and 2, in a top view, a row direction of the plug array is the first direction, a column direction of the plug array is the second direction, two adjacent rows of the drain contact plugs 104 are aligned, two adjacent rows of the source contact plugs 102 are aligned, and one row of the source contact plugs 102 is sandwiched between two adjacent rows of the drain contact plugs 104. And the bit lines BL are coplanar with and perpendicular to the word lines WL (i.e., the bit lines BL intersect and perpendicular to the projection of the word lines WL onto the surface of the semiconductor substrate 100). At this time, in this embodiment, two adjacent memory cells may share the bit line BL and the source line SL. The source line SL and bit line BL structure shown in fig. 3, on one hand, can reduce the interference between adjacent memory cells and improve the device performance; on the other hand, the distance between two adjacent contact plugs on two adjacent bit lines BL can be relatively increased, the manufacturing difficulty of the contact plugs is reduced, the problems of bridging and the like are avoided, and the device performance is improved. At this time, each word line WL and each word line WLThe cross point connection position of the bit line BL corresponds to a memory cell, each memory cell is of a 1-transistor (T)1 Magnetic Tunnel Junction (MTJ) structure, or a 2-transistor (T)2 Magnetic Tunnel Junction (MTJ) structure, and the area of each memory cell is 2F × 2F — 4F2. Where F is a characteristic dimension, the length of each memory cell in a direction perpendicular to the second direction is 2F, and the length in the second direction is 2F.
In addition, the adjacent word lines WL, the adjacent bit lines BL, the adjacent source lines SL, the adjacent magnetic tunnel junctions 106, the adjacent contact plugs, the word lines WL and the bit lines BL, the word lines WL and the source lines SL, the word lines WL and the magnetic tunnel junctions 106, the source lines SL and the bit lines, and the second metal layers 105 of the adjacent memory cells are insulated and isolated by corresponding insulating dielectric layers (not shown).
In addition, in the technical solution of the present invention, the layout of the bit lines BL and the source lines SL is not limited to the layout structure shown in fig. 2 in a top view, is not limited to the layout structure shown in fig. 3 in a cross-sectional view, and may be any other suitable layout method. Specifically, for example, as shown in fig. 4, in another embodiment of the present invention, the bit line BL and the source line SL may also be disposed in an intersecting manner from top to bottom, the metal layer where the bit line BL and the source line SL are located is partially overlapped, the bit line BL sequentially passes through the magnetic tunnel junction 106, the second metal layer 105, and the drain contact plug 104 ' to contact with a portion of the metal layer 103 ' of the metal layer 103 where the source line SL is located, the metal layer 103 ' contacts the drain region 101b through the drain contact plug 104, and the source line SL contacts the source region 101a through the source contact plug 102. The bit line BL is also perpendicular to the word line WL. For another example, referring to fig. 5, in another embodiment of the present invention, the following steps may be further performed: the bit lines BL and the source lines SL are arranged in parallel, and the bit lines BL and the word lines WL are intersected in a non-perpendicular manner (i.e., the projections of the bit lines BL and the word lines WL on the surface of the semiconductor substrate 100 are intersected and the included angle is not 90 degrees), and optionally, the bit lines BL and the source lines SL are arranged along the third direction. At this time, the memory cells in two adjacent rows share the same bit line BL and/or the same source line SL.
Referring to fig. 1 to 5, based on the same inventive concept, an embodiment of the invention further provides a semiconductor device including the magnetic random access memory array, and the structures of the bit line BL and the source line SL of the magnetic random access memory array may be as shown in fig. 3 or fig. 4. The semiconductor device may be a memory, a sense amplifier, a magnetic sensor, a memory integrated chip, or the like.
In summary, the magnetic random access memory array and the semiconductor device having the magnetic random access memory array of the present invention can effectively utilize the substrate area space by the layout of the plurality of active regions extending along the third direction and the plurality of word lines extending along the second direction, and realize smaller feature size of the memory cell and higher memory density, and lower chip cost, while occupying the same substrate area. Further, a cell area of 4F can be achieved2And (F is a characteristic size) close-packed storage array, so that the storage density and the device integration level are improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

1. A magnetic random access memory array, comprising:
the semiconductor device comprises a semiconductor substrate, a plurality of strip-shaped active regions arranged along a first direction and a second direction are arranged in the semiconductor substrate, each active region extends along a third direction, the second direction is vertical to the first direction, and the third direction is intersected with the first direction and the second direction;
the word lines are arranged on the semiconductor substrate along a first direction, extend along a second direction and cross over the active regions, and divide the corresponding active regions into a source region and a drain region;
a plurality of source lines, each of which is formed through a first metal layer and connects to a corresponding source region;
and each magnetic tunnel junction is connected with the corresponding drain region at the bottom through the corresponding second metal layer, and is connected with a third metal layer at the top, and the third metal layer is used for forming a corresponding bit line.
2. The magnetic random access memory array of claim 1 wherein each of the active regions and the word lines disposed above the active region form a respective MOS transistor, the respective MOS transistor formed at the active region and the respective magnetic tunnel junction above the drain region forming a memory cell.
3. The magnetic random access memory array of claim 2 wherein each of said memory cells has a minimum of only one MOS transistor.
4. The MRAM array of claim 3, wherein the source and drain regions of the MOS transistor of each memory cell other than the memory cell at the array boundary of the MRAM array are shared with surrounding adjacent memory cells, each of the memory cells having an area of 4F2Wherein F is the feature size.
5. The magnetic random access memory array of claim 1 wherein each of the drain regions is connected to the second metal layer at the bottom of the magnetic tunnel junction by a drain contact plug located above the drain region, and each of the source regions is connected to the source line by a source contact plug located above the source region; the drain contact plugs and the source contact plugs are arranged in rows and columns into an array of plugs.
6. The MRAM array of claim 5, wherein a row direction of the array of plugs is the first direction, a column direction of the array of plugs is the second direction, and a row of the source contact plugs is sandwiched between two rows of the drain contact plugs.
7. The magnetic random access memory array of claim 1 wherein the bit line and the source line are disposed in parallel or the bit line and the source line are disposed in an out-of-plane intersection.
8. The MRAM array of claim 1 or 7, wherein the bit line intersects the word line off-plane perpendicularly, or wherein the bit line intersects the word line off-plane and is not perpendicular.
9. The magnetic random access memory array of claim 1 wherein the angle between the first direction and the third direction includes, but is not limited to, 45 degrees.
10. A semiconductor device comprising the magnetic random access memory array of any one of claims 1 to 9.
CN202010335025.2A 2020-04-24 2020-04-24 Magnetic random access memory array and semiconductor device Pending CN113555381A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103137645A (en) * 2011-11-25 2013-06-05 三星电子株式会社 Semiconductor memory device having three-dimensionally arranged resistive memory cells
US20150221699A1 (en) * 2014-02-04 2015-08-06 Samsung Electronics Co., Ltd. Magnetic memory device
CN106104790A (en) * 2014-03-06 2016-11-09 株式会社 东芝 Magnetoresistive memory device
US20170170234A1 (en) * 2015-12-11 2017-06-15 Jae-Kyu Lee Magnetoresistive random access memory device and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103137645A (en) * 2011-11-25 2013-06-05 三星电子株式会社 Semiconductor memory device having three-dimensionally arranged resistive memory cells
US20150221699A1 (en) * 2014-02-04 2015-08-06 Samsung Electronics Co., Ltd. Magnetic memory device
CN106104790A (en) * 2014-03-06 2016-11-09 株式会社 东芝 Magnetoresistive memory device
US20170170234A1 (en) * 2015-12-11 2017-06-15 Jae-Kyu Lee Magnetoresistive random access memory device and method of manufacturing the same

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