CN113555380A - Magnetic random access memory array and semiconductor device - Google Patents

Magnetic random access memory array and semiconductor device Download PDF

Info

Publication number
CN113555380A
CN113555380A CN202010333744.0A CN202010333744A CN113555380A CN 113555380 A CN113555380 A CN 113555380A CN 202010333744 A CN202010333744 A CN 202010333744A CN 113555380 A CN113555380 A CN 113555380A
Authority
CN
China
Prior art keywords
source
array
line
active regions
bit line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010333744.0A
Other languages
Chinese (zh)
Inventor
吴巍
徐征
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujian Jinhua Integrated Circuit Co Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN202010333744.0A priority Critical patent/CN113555380A/en
Publication of CN113555380A publication Critical patent/CN113555380A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

The invention provides a magnetic random access memory array and a semiconductor device, which effectively utilize space, realize smaller characteristic size of a memory unit, have higher integral density and lower chip cost by staggered arrangement between two adjacent rows of active regions on the premise of occupying the same substrate area. Further, a cell area of 8F can be realized2And (F is a characteristic size) close-packed storage array, so that the storage density and the device integration level are improved. In addition, the source line and the bit line can be intersected with the word line and are not vertical to the word line, so that the memory cells corresponding to the adjacent active regions in the same row and the same column do not share the same bit line, the interference between the adjacent memory cells can be reduced, and the device performance is improved.

Description

Magnetic random access memory array and semiconductor device
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a magnetic random access memory array and a semiconductor device.
Background
Magnetic Random Access Memory (MRAM) is a new Memory and storage technology, can be read and written randomly as fast as SRAM/DRAM, and can permanently retain data after power off as Flash Memory. Each MRAM memory cell consists of one magnetic tunnel junction and one MOS transistor, and may also consist of two magnetic tunnel junctions and two MOS transistors. Each memory cell needs to be connected to three wires: the grid electrode of the MOS tube is connected to a word line of the chip and is responsible for switching on or switching off the unit; one pole (source or drain) of the MOS transistor is connected to the source line, the other pole (drain or source) of the MOS transistor is connected to one pole of the magnetic tunnel junction, and the other pole of the magnetic tunnel junction is connected to the bit line.
As MRAM technology continues to advance, how to make MRAM memory cells smaller to increase MRAM density has become one of the technical problems that those skilled in the art are demanding to solve.
Disclosure of Invention
It is an object of the present invention to provide a magnetic random access memory array and a semiconductor device that can have a reduced memory cell area and an increased memory density.
To solve the above technical problem, the present invention provides a magnetic random access memory array, comprising:
the semiconductor device comprises a semiconductor substrate, a plurality of active regions and a plurality of control circuits, wherein the plurality of active regions are arranged in rows and columns to form an array, and two adjacent rows of the active regions are arranged in a staggered mode;
the plurality of word lines are formed on the semiconductor substrate, extend along the row direction and cross the plurality of active regions in the same row, and divide the corresponding active regions into a source region and a drain region;
a plurality of source lines, each of which is formed through a first metal layer and connects to a corresponding source region;
and each magnetic tunnel junction is connected with the corresponding drain region at the bottom through the corresponding second metal layer, and is connected with a third metal layer at the top, and the third metal layer is used for forming a corresponding bit line.
Optionally, each active region and the word line arranged above the active region form a corresponding MOS transistor, the MOS transistor and the magnetic tunnel junction above the active region form a memory cell, and the area of the memory cell is 8F2Which isF is the characteristic dimension of the magnetic random access memory array, and the length of the memory cell in the row direction is 2 times the length in the column direction.
Optionally, a distance between two adjacent active regions on the same row is smaller than a length of the active regions in the row direction.
Optionally, the bit line and the source line are arranged in parallel.
Optionally, the bit line and the word line are intersected in a non-coplanar manner and are not perpendicular, or the bit line and the word line are perpendicular.
Optionally, when the bit line intersects with the word line in a non-coplanar manner and is not perpendicular to the word line, two adjacent memory cells on the same row and the same column do not share the bit line and the source line; when the bit lines are vertical to the word lines, the storage units in two adjacent rows share the same bit line and/or the same source line.
Optionally, when the bit line and the word line intersect in a non-coplanar manner and are not perpendicular, the included angle between the bit line and the word line includes, but is not limited to, 45 degrees.
Optionally, each drain region is connected to the second metal layer at the bottom of the magnetic tunnel junction through a drain contact plug located above the drain region, and each source region is connected to the source line through a source contact plug located above the source region; the drain contact plugs and the source contact plugs are arranged in the rows and columns into a plug array.
Alternatively, the drain contact plugs and the source contact plugs in each column of the plug array are alternately arranged, and the drain contact plugs and the source contact plugs in each row of the plug array are alternately arranged. .
Based on the same inventive concept, the invention also provides a semiconductor device comprising the magnetic random access memory array.
Compared with the prior art, the magnetic random access memory array and the semiconductor device with the magnetic random access memory array have the following beneficial effects:
1. on the premise of occupying the same substrate area, the space is effectively utilized through the staggered arrangement between two adjacent rows of active regions, the characteristic size of a smaller storage unit is realized, the overall density is higher, and the chip cost is lower.
2. Can realize the unit area of 8F2(F is the characteristic size of the magnetic random access memory array) to improve the storage density and the device integration level.
3. The source lines and the bit lines are intersected and not vertical to the word lines, so that the distance between two adjacent bit lines or between two source lines is increased, the manufacturing difficulty of the source lines, the bit lines, the drain contact plugs and the source contact plugs is reduced, the interference between adjacent memory cells can be reduced, and the device performance is improved.
Drawings
Fig. 1 is a schematic diagram of a layout structure of a magnetic random access memory array according to an embodiment of the present invention (structures such as bit lines BL and source lines SL are omitted);
FIG. 2 is a schematic cross-sectional view of the MRAM array of FIG. 1 along line XX' (with the interlayer dielectric layer omitted, etc.) in accordance with an embodiment of the present invention;
FIG. 3 is a schematic layout of source and bit lines of a magnetic random access memory array in accordance with an embodiment of the present invention;
FIG. 4 is a schematic layout of source and bit lines of a magnetic random access memory array in accordance with an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of the MRAM array of FIG. 1 along line XX' (the interlayer dielectric layer and the like are omitted), in accordance with another embodiment of the present invention.
Detailed Description
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. As used herein, "and/or" means either or both.
Referring to fig. 1 to 3, an embodiment of the invention provides a magnetic random access memory array including a semiconductor substrate 100, a plurality of word lines WL, a plurality of source lines SL, a plurality of magnetic tunnel junctions 106, and a plurality of bit lines BL.
The semiconductor substrate 100 may be a silicon substrate, a germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like. The semiconductor substrate 100 may be implanted with impurities to form the active region 101, and the impurities may include n-type impurities such as phosphorus, arsenic, or the like, or p-type impurities such as boron, gallium, or the like. The space between adjacent active regions 101 is a field region (not shown), which may be formed by a Shallow Trench Isolation (STI) process or a local field oxide isolation (LOCOS) process.
In this example. A plurality of active regions 101 are formed in the semiconductor substrate 100, all the active regions 101 are arranged in rows and columns to form an array, and two adjacent rows of the active regions 101 are arranged in a staggered manner, and the active regions 101 in every other row are aligned in the column direction. Each active region 101 has a rectangular shape (or a short stripe structure), and a long side thereof extends in the row direction. The distance D between two adjacent active regions 101 on the same row (i.e. the column distance of the array) is smaller than the extension length L of the active regions 101 in the row direction. For example, when L is 3D, the width of the active region 101 is also D, and the row pitch of the array is also D, the size of each memory cell in the memory array defined by the active region array in the row direction is 4F, the size of each memory cell in the column direction is 2F, and the area of each memory cell is 4F × 2F — 8F2Wherein F is the minimum Size of the mram array that is fabricated as part or most of the semiconductor integrated circuit chip, and is also often referred to as Feature Size (Feature Size).
A plurality of word lines WL are formed on the semiconductor substrate 100, each word line WL extending in a column direction and crossing over a plurality of active regions 101 in the same column and a corresponding space between the active regions 101 in the column, and each word line WL dividing the corresponding active region 101 into a source region 101a and a drain region 101 b. Each active region 101 and the word line WL arranged above the active region 101 form a corresponding MOS transistor, that is, the word line WL serves as a gate of the MOS transistor, the active regions 101 on both sides of the word line WL are a source region 101a and a drain region 101b of the MOS transistor, respectively, and the active region 101 covered by the word line WL is a channel region of the MOS transistor. The word line WL may be made of polysilicon or a metal gate, a gate dielectric layer (not shown) is further disposed between the word line WL and the semiconductor substrate 100, and a Spacer (not shown) may be further formed on the SideWall of the word line WL. The line width of the word line WL may be equal to or less than the column pitch D of the array formed by the active region 101, so as to avoid interference between memory cells caused by the overlap of the word line WL and the unnecessary active region 101, which affects device performance.
Several source lines SL are formed through the first metal layer 103 and connected to the corresponding source regions 101a through the corresponding source contact plugs 102.
The bottom of each Magnetic Tunnel Junction (MTJ)106 is connected to the corresponding drain region 101b through the corresponding second metal layer 105 and the drain contact plug 104 under the second metal layer 105, and the top of each magnetic tunnel junction 106 is connected to a third metal layer 107, and the third metal layer 107 is used for forming the corresponding bit line BL. The MTJ 106 is only formed on the drain region of the MOS transistor connected to the bit line BL, and the corresponding MOS transistor formed at each active region 101 and the magnetic tunnel junction 106 above the drain region 101b of the MOS transistor constitute a memory cell. The source contact plug 102, the drain contact plug 104, the first metal layer 103, the second metal layer 105, and the third metal layer 107 may each include a metal and/or a metal nitride. The magnetic tunnel junction 106 may include a barrier layer (not shown), which may reduce or prevent abnormal growth of metals in the pinning layer, the lower ferromagnetic layer, the ferromagnetic coupling spacer layer, the upper ferromagnetic layer, and the like, which are sequentially formed on the second metal layer 105, a pinning layer, a lower ferromagnetic layer, an antiferromagnetic coupling spacer layer, an upper ferromagnetic layer, and the like, and the barrier layer may include an amorphous metal or metal nitride, such as tantalum, tantalum nitride, titanium nitride, and the like. The pinning layer may include, but is not limited to, FeMn, IrMn, PtMn, MnO, MnS, MnTe, MnF2、FeF2、FeCl2、FeO、CoCl2、CoO、NiCl2NiO, Cr, and the like. The lower and upper ferromagnetic layers may include, but are not limited to, FeAnd metals such as Ni and Co. The antiferromagnetic coupling spacer layer may include, but is not limited to, Ru, Ir, Rh, etc. The lower ferromagnetic layer may have a fixed or "pinned" magnetic orientation, while the upper ferromagnetic layer has a variable or "free" magnetic orientation and may be switched between two or more different magnetic polarities, each representing a different data state, such as a different binary state. However, in other implementations, the MTJ 106 may be "flipped" vertically such that the lower ferromagnetic layer has a "free" magnetic orientation and the upper ferromagnetic layer has a "fixed" magnetic orientation.
Referring to fig. 2 and fig. 3, in the present embodiment, the bit line BL and the source line SL are arranged in parallel, metal layers where the bit line BL and the source line SL are located are not overlapped at all, the bit line BL contacts with a drain region sequentially through a magnetic tunnel junction 106, a second metal layer 105, and a drain contact plug 104, and the source line SL contacts with a source region through a source contact plug 102. All of the drain contact plugs 104 and the source contact plugs 102 are arranged in rows and columns in a plug array. Referring to fig. 1 and 3, in a top view, in each row of plugs, the drain contact plugs 104 and the source contact plugs 102 are alternately arranged, in each column of plugs, the drain contact plugs 104 and the source contact plugs 102 are also alternately arranged, the drain contact plugs 104 in two adjacent rows are staggered and misaligned, the source contact plugs 102 in two adjacent rows are staggered and misaligned, the drain contact plugs 104 in two adjacent columns are staggered and misaligned, and the source contact plugs 102 in two adjacent columns are staggered and misaligned. And the bit lines BL are intersected and not perpendicular to the word lines WL (i.e., the bit lines BL are intersected and not perpendicular to the projections of the word lines WL on the surface of the semiconductor substrate 100), for example, the angle between the bit lines BL and the word lines WL may be 45 degrees, but is not limited to 45 degrees.
In addition, the adjacent word lines WL, the adjacent bit lines BL, the adjacent source lines SL, the adjacent magnetic tunnel junctions 106, the adjacent contact plugs, the word lines WL and the bit lines BL, the word lines WL and the source lines SL, the word lines WL and the magnetic tunnel junctions 106, the source lines SL and the bit lines, and the second metal layers 105 of the adjacent memory cells are insulated and isolated by corresponding insulating dielectric layers (not shown).
The source line SL and bit line BL structure shown in fig. 3, on one hand, can reduce the interference between adjacent memory cells and improve the device performance; on the other hand, the distance between two adjacent contact plugs on the same source line SL or bit line BL can be relatively increased, the manufacturing difficulty of the source line, the bit line and the contact plugs is reduced, the problems of bridging and the like are avoided, then the interference between adjacent memory cells can be reduced, and the device performance is improved. At this time, the intersection connection portion of each word line WL and each bit line BL corresponds to a memory cell, and each memory cell is a 1-transistor (T)1 Magnetic Tunnel Junction (MTJ) structure.
It should be noted that the layout of the bit lines BL and the source lines SL is not limited to the layout structure shown in fig. 3 in a top view, is not limited to the layout structure shown in fig. 2 in a cross-sectional view, and may be any other suitable layout method. Specifically, for example, referring to fig. 4, in other embodiments of the present invention, it may further be that: the bit lines BL and the source lines SL are arranged in parallel, the bit lines BL and the word lines WL are intersected perpendicularly (that is, the bit lines BL and the word lines WL are intersected and perpendicular to each other on the projection of the word lines WL on the surface of the semiconductor substrate 100), and at this time, two adjacent rows of the memory cells share the same bit line BL and/or the same source line SL. For another example, referring to fig. 5, in another embodiment of the present invention, the bit line BL and the source line SL may also be disposed in an intersecting manner from top to bottom, the metal layer where the bit line BL and the source line SL are located is partially overlapped, the bit line BL sequentially passes through the magnetic tunnel junction 106, the second metal layer 105, and the drain contact plug 104 ' to contact with a part of the metal layer 103 ' of the metal layer 103 where the source line SL is located, the metal layer 103 ' contacts the drain region 101b through the drain contact plug 104, and the source line SL contacts the source region 101a through the source contact plug 102. The bit line BL is also perpendicular to the word line WL.
Referring to fig. 1 to 5, based on the same inventive concept, an embodiment of the invention further provides a semiconductor device including the magnetic random access memory array, and the structure of the bit line BL and the source line SL of the magnetic random access memory array can be as shown in fig. 3 or as shown in fig. 4. The semiconductor device may be a memory, a sense amplifier, a magnetic sensor, a memory integrated chip, or the like.
In summary, the magnetic random access memory array and the semiconductor device having the magnetic random access memory array of the present invention effectively utilize space, realize smaller feature size of the memory cell, have higher overall density, and have lower chip cost by the staggered arrangement between two adjacent rows of active regions on the premise of occupying the same substrate area. Further, a cell area of 8F can be realized2And (F is a characteristic size) close-packed storage array, so that the storage density and the device integration level are improved. In addition, the source line and the bit line can be intersected with the word line in a non-coplanar manner and are not perpendicular to each other, so that the memory cells corresponding to the adjacent active regions in the same row and the same column do not share the same source line and the same bit line, and therefore, the interference between the adjacent memory cells can be reduced, and the device performance is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

1. A magnetic random access memory array, comprising:
the semiconductor device comprises a semiconductor substrate, a plurality of active regions and a plurality of control circuits, wherein the plurality of active regions are arranged in rows and columns to form an array, and two adjacent rows of the active regions are arranged in a staggered mode;
the plurality of word lines are formed on the semiconductor substrate, extend along the row direction and cross the plurality of active regions in the same row, and divide the corresponding active regions into a source region and a drain region;
a plurality of source lines, each of which is formed through a first metal layer and connects to a corresponding source region;
and each magnetic tunnel junction is connected with the corresponding drain region at the bottom through the corresponding second metal layer, and is connected with a third metal layer at the top, and the third metal layer is used for forming a corresponding bit line.
2. The MRAM array of claim 1, wherein each of the active regions and the word lines disposed above the active regions form a respective MOS transistor, the MOS transistor and the magnetic tunnel junction above the drain region forming a memory cell, the memory cell having an area of 8F2Where F is a characteristic dimension of the magnetic random access memory array, and the length of the memory cells in the row direction is 2 times the length in the column direction.
3. The magnetic random access memory array of claim 1 wherein the spacing between two adjacent active regions on a same row is less than the length of the active regions in the row direction.
4. The magnetic random access memory array of claim 1, wherein the bit line and the source line are disposed in parallel.
5. The MRAM array of claim 1 or 4, wherein the bit line intersects the word line in a non-perpendicular manner or the bit line is perpendicular to the word line.
6. The MRAM array of claim 5, wherein when the bit line intersects the word line in a non-perpendicular manner, no bit line and no source line are shared by two adjacent memory cells in a same row and a same column; when the bit lines are vertical to the word lines, the storage units in two adjacent rows share the same bit line and/or the same source line.
7. The MRAM array of claim 6, wherein the angle between the bit line and the word line includes, but is not limited to, 45 degrees when the bit line and the word line are non-coplanar and non-perpendicular.
8. The magnetic random access memory array of claim 1 wherein each of the drain regions is connected to the second metal layer at the bottom of the magnetic tunnel junction by a drain contact plug located above the drain region, and each of the source regions is connected to the source line by a source contact plug located above the source region; the drain contact plugs and the source contact plugs are arranged in the rows and columns into a plug array.
9. The magnetic random access memory array of claim 8, wherein the drain contact plugs and the source contact plugs in each column of the array of plugs are arranged alternately, and the drain contact plugs and the source contact plugs in each row of the array of plugs are arranged alternately.
10. A semiconductor device comprising the magnetic random access memory array of any one of claims 1 to 9.
CN202010333744.0A 2020-04-24 2020-04-24 Magnetic random access memory array and semiconductor device Pending CN113555380A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010333744.0A CN113555380A (en) 2020-04-24 2020-04-24 Magnetic random access memory array and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010333744.0A CN113555380A (en) 2020-04-24 2020-04-24 Magnetic random access memory array and semiconductor device

Publications (1)

Publication Number Publication Date
CN113555380A true CN113555380A (en) 2021-10-26

Family

ID=78129704

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010333744.0A Pending CN113555380A (en) 2020-04-24 2020-04-24 Magnetic random access memory array and semiconductor device

Country Status (1)

Country Link
CN (1) CN113555380A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024148748A1 (en) * 2023-01-12 2024-07-18 长鑫存储技术有限公司 Semiconductor structure and layout method therefor, and column gating circuit and memory

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040099616A (en) * 2003-05-19 2004-12-02 주식회사 하이닉스반도체 Layout method for semiconductor device
US20050139880A1 (en) * 2003-12-24 2005-06-30 Hynix Semiconductor Inc. Method for manufacturing magnetic random access memory
JP2013055134A (en) * 2011-09-01 2013-03-21 Toshiba Corp Semiconductor storage device
US20150221699A1 (en) * 2014-02-04 2015-08-06 Samsung Electronics Co., Ltd. Magnetic memory device
CN110729303A (en) * 2018-07-17 2020-01-24 中芯国际集成电路制造(上海)有限公司 NAND memory and forming method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040099616A (en) * 2003-05-19 2004-12-02 주식회사 하이닉스반도체 Layout method for semiconductor device
US20050139880A1 (en) * 2003-12-24 2005-06-30 Hynix Semiconductor Inc. Method for manufacturing magnetic random access memory
JP2013055134A (en) * 2011-09-01 2013-03-21 Toshiba Corp Semiconductor storage device
US20150221699A1 (en) * 2014-02-04 2015-08-06 Samsung Electronics Co., Ltd. Magnetic memory device
CN110729303A (en) * 2018-07-17 2020-01-24 中芯国际集成电路制造(上海)有限公司 NAND memory and forming method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024148748A1 (en) * 2023-01-12 2024-07-18 长鑫存储技术有限公司 Semiconductor structure and layout method therefor, and column gating circuit and memory

Similar Documents

Publication Publication Date Title
US10672460B2 (en) Dual port SRAM cell with dummy transistors
US20180351080A1 (en) Magnetoresistive random access memory device and method of manufacturing the same
US9543404B2 (en) Vertical BJT for high density memory
US7049654B2 (en) Memory with split gate devices and method of fabrication
US8987811B2 (en) Semiconductor devices including a vertical channel transistor and methods of fabricating the same
US9570510B2 (en) Magnetoresistive random access memory devices and methods of manufacturing the same
US7579614B2 (en) Magnetic random access memory
US7119389B2 (en) Dynamic random access memory cells having laterally offset storage nodes
US9299392B2 (en) Semiconductor memory devices
US9159767B2 (en) Methods of manufacturing magnetoresistive random access memory devices
US20100019297A1 (en) Multi-Stacked Spin Transfer Torque Magnetic Random Access Memory and Method of Manufacturing the Same
US10008539B2 (en) Magnetoresistive random access memory device and method of manufacturing the same
US9337418B2 (en) Method of manufacturing a magnetoresistive random access memory device
KR102081989B1 (en) Magnetic memory device and method of manufacturing the same
US8456888B2 (en) Semiconductor memory device including variable resistance elements and manufacturing method thereof
US11271038B2 (en) Semiconductor devices
CN113555046A (en) Magnetic random access memory and read-write method thereof
US11930644B2 (en) Semiconductor structure and storage circuit
CN113555380A (en) Magnetic random access memory array and semiconductor device
US20070296007A1 (en) Shared ground contact isolation structure for high-density magneto-resistive RAM
US9437654B2 (en) Magnetic memory devices
US20120134195A1 (en) Memory Device and Manufacturing Method Thereof
CN113555382A (en) Magnetic random access memory array and semiconductor device
CN113555381A (en) Magnetic random access memory array and semiconductor device
US20170256549A1 (en) Static random access memory

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20240507

Address after: No.88 Lianhua Avenue, integrated circuit Science Park, Jinjiang City, Quanzhou City, Fujian Province, 362200

Applicant after: FUJIAN JINHUA INTEGRATED CIRCUIT Co.,Ltd.

Country or region after: China

Address before: Room 1501, No. 17, Little Swan Garden, Liangxi District, Wuxi City, Jiangsu Province, 214000

Applicant before: Wu Wei

Country or region before: China

Applicant before: Xu Zheng