CN110729303A - NAND memory and forming method thereof - Google Patents
NAND memory and forming method thereof Download PDFInfo
- Publication number
- CN110729303A CN110729303A CN201810786443.6A CN201810786443A CN110729303A CN 110729303 A CN110729303 A CN 110729303A CN 201810786443 A CN201810786443 A CN 201810786443A CN 110729303 A CN110729303 A CN 110729303A
- Authority
- CN
- China
- Prior art keywords
- drain
- lines
- source
- active regions
- nand memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Abstract
The invention provides a NAND memory and a forming method thereof, wherein a substrate comprises a plurality of first active regions and isolation regions which are alternately arranged, and a second active region connected with the first active regions, a plurality of source selection lines, drain selection lines and word lines which are intersected with the first active regions are formed on the substrate, the word lines are positioned between the source selection lines and the drain selection lines, the second active regions are positioned between the adjacent source selection lines, then a plurality of common source contacts are formed on the second active regions between the adjacent source selection lines, a drain contact is formed on each first active region between the adjacent drain selection lines, compared with the strip-shaped common source contacts in the prior art, the areas of the common source contacts and the drain contacts do not differ too much, thereby avoiding the etching load effect in the process of forming contact holes by etching, and ensuring the dimensional accuracy of the common source contacts and the drain contacts, improving the performance of the NAND memory.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a NAND memory and a forming method thereof.
Background
With the development of semiconductor technology, various semiconductor memory devices, such as a NOR (NOR) flash memory, a NAND (NAND) flash memory, and the like, have been developed. Semiconductor memory devices have advantages of fast access speed, high memory density, and the like, compared to conventional memory devices such as magnetic memory devices. Among them, the NAND structure is receiving more and more attention.
The memory cell array of the NAND memory includes a string structure. The string structure includes: a drain select transistor, wherein the drain is connected to a bit line (bit line); a source select transistor, wherein a source is connected to a common source line; and a plurality of memory cells connected in series between the drain select transistor and the source select transistor. The plurality of string structures are electrically isolated and coupled in parallel. The gate of the drain select transistor is connected in parallel to a drain select line, the gate of the source select transistor is connected in parallel to a source select line, and the gate of the memory cell is connected in parallel to a word line (word line). The string structures are also connected to each other in the vertical direction. The drain of a drain select transistor in one string of structures is connected to the drain of a drain select transistor in another string of structures, and the source of a source select transistor in one string of structures is connected to the source of a source select transistor in another string of structures.
The junction region formed between adjacent drain select lines is the drain, a drain contact is formed on the drain, the junction region formed between adjacent source select lines is the common source, and a common source contact is formed on the common source. However, when forming the drain contact and the common source contact, a contact hole needs to be etched first, and an etching loading effect (etching loading) is usually generated in the etching process, so that the common source contact or the drain contact does not meet a predetermined precision requirement, thereby affecting the performance of the finally formed NAND memory.
Disclosure of Invention
The invention provides a NAND memory and a forming method thereof, which can avoid the occurrence of etching load effect in the process of forming a drain contact and a source contact and improve the performance of the NAND memory.
The forming method of the NAND memory provided by the invention comprises the following steps: providing a substrate, wherein the substrate comprises a plurality of first active regions and isolation regions which are alternately arranged, and a second active region connected with the first active regions;
forming a plurality of source selection lines, drain selection lines and word lines on the substrate, wherein the source selection lines, the drain selection lines and the word lines intersect the first active regions, the word lines are located between the source selection lines and the drain selection lines, and the second active regions are located between adjacent source selection lines;
forming a plurality of common source contacts on the second active regions between adjacent ones of the source select lines, and forming a drain contact on each of the first active regions between adjacent ones of the drain select lines.
Furthermore, the first active region and the isolation region both extend along a first direction, the second active region extends along a second direction, and the first direction is perpendicular to the second direction.
Further, the source selection line, the drain selection line and the word line all extend along the second direction.
Further, two dummy word lines are formed between the source select line and the word line, and between the drain select line and the word line.
Furthermore, the cross section of the common source contact is rectangular or square, and the common source contacts are uniformly distributed on the second active region.
Further, each common source contact is located between two adjacent first active regions.
Further, before forming the source select line, the drain select line and the word line, the method for forming the NAND memory further comprises: an isolation structure is formed over the isolation region.
Correspondingly, the invention also provides a NAND memory, comprising: the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein the substrate comprises a plurality of first active regions and isolation regions which are alternately arranged, and a second active region connected with the first active regions;
a plurality of source select lines and drain select lines on the substrate, the source select lines and drain select lines intersecting the first active region, and the second active region being located between adjacent source select lines;
a plurality of word lines between the source select line and the drain select line;
a plurality of common source contacts on the second active region between adjacent ones of the source select lines, and a drain contact on each first active region between adjacent ones of the drain select lines.
Furthermore, the first active region and the isolation region both extend along a first direction, the second active region extends along a second direction, and the first direction is perpendicular to the second direction.
Further, the source selection line, the drain selection line and the word line all extend along the second direction.
Further, two dummy word lines are disposed between the source select line and the word line, and between the drain select line and the word line.
Furthermore, the cross section of the common source contact is rectangular or square, and the common source contacts are uniformly distributed on the second active region.
Further, each common source contact is located between two adjacent first active regions.
Further, the NAND memory further includes: an isolation structure located over the isolation region.
In the NAND memory and the forming method thereof provided by the present invention, a substrate includes a plurality of first active regions and isolation regions alternately arranged, and a second active region connected to the first active regions, a plurality of source select lines, drain select lines, and word lines intersecting the first active regions are formed on the substrate, the word lines are located between the source select lines and the drain select lines, and the second active regions are located between adjacent source select lines, then a plurality of common source contacts are formed on the second active regions between adjacent source select lines, a drain contact is formed on each first active region between adjacent drain select lines, that is, a plurality of common source contacts are formed between adjacent source select lines, a plurality of drain contacts are formed between adjacent drain select lines, as compared to the common source contacts in the form of a stripe between adjacent source select lines in the prior art, according to the invention, the areas of the common source contact and the drain contact do not differ too much, so that an etching load effect is avoided in the process of forming the contact hole by etching, the size precision of the common source contact and the drain contact is ensured, and the performance of the NAND memory is improved.
Drawings
FIG. 1 is a top view of a NAND memory.
FIG. 2 is a flow chart illustrating a method for forming a NAND memory according to an embodiment of the invention.
FIG. 3 is a top view of a NAND memory provided in an embodiment of the invention.
Detailed Description
FIG. 1 is a top view of a NAND memory, as shown in FIG. 1, the method of forming the NAND memory generally comprising: firstly, providing a substrate 10, wherein the substrate 10 comprises a plurality of active regions 11 and isolation regions 12 which are alternately arranged; then, an isolation structure is formed in the isolation region 12; next, a plurality of source select lines SSG, drain select lines DSG, and word lines WL (e.g., including WL0, WL1, WL2, … …, WLn-2, WLn-1, WLn) are formed on the substrate 10, while two Dummy word lines Dummy are formed between the source select lines SSG and the word lines WL0, and between the drain select lines DSG and the word lines WLn, respectively; then, junction regions are formed on each active region 11 between adjacent select lines (SSG, DSG), between a word line and an adjacent select line, and between adjacent word lines. The junction region formed between the adjacent drain select lines DSG is a drain, and the junction region formed between the adjacent source select lines SSG is a common source.
And then, forming an interlayer insulating layer on the structure, etching the interlayer insulating layer to form a drain contact hole and a common source contact hole, exposing the drain electrode through the drain contact hole, exposing the common source through the common source contact hole, filling materials in the drain contact hole and the common source contact hole, and respectively forming a drain contact CCT and a common source contact CSC.
As shown in fig. 1, the cross section of the drain contact CCT is rectangular, the common source contact CSC is located in each active region 11 between the adjacent drain selection lines DSG, the common source contact CSC is strip-shaped and located in the region of the adjacent source selection line SSG, the common source contact CSC and the common source contact CSC are not in the same shape, the area of the common source contact CSC is much larger than that of the drain contact CCT, and the depth of the common source contact hole is much larger than that of the drain contact hole in order to prevent leakage current. Therefore, when two contact holes with different areas and depths are formed by etching, an etching load effect is generated, so that the etching rate of the contact hole with the larger area is lower than that of the contact hole with the smaller area, the common source contact CSC or the drain contact CCT cannot reach the preset precision, and the performance of the finally formed NAND memory is influenced.
In view of the above problems, applicants provide a NAND memory and a method of forming the same, comprising: providing a substrate, wherein the substrate comprises a plurality of first active regions and isolation regions which are alternately arranged, and a second active region connected with the first active regions; forming a plurality of source selection lines, drain selection lines and word lines on the substrate, wherein the source selection lines, the drain selection lines and the word lines intersect the first active regions, the word lines are located between the source selection lines and the drain selection lines, and the second active regions are located between adjacent source selection lines; a plurality of common source contacts are formed between adjacent ones of the source select lines, and a drain contact is formed on each of the first active regions between adjacent ones of the drain select lines.
In the NAND memory and the forming method thereof provided by the present invention, a substrate includes a plurality of first active regions and isolation regions alternately arranged, and a second active region connected to the first active regions, a plurality of source select lines, drain select lines, and word lines intersecting the first active regions are formed on the substrate, the word lines are located between the source select lines and the drain select lines, and the second active regions are located between adjacent source select lines, then a plurality of common source contacts are formed on the second active regions between adjacent source select lines, a drain contact is formed on each first active region between adjacent drain select lines, that is, a plurality of common source contacts are formed between adjacent source select lines, a plurality of drain contacts are formed between adjacent drain select lines, as compared to the common source contacts in the form of a stripe between adjacent source select lines in the prior art, according to the invention, the areas of the common source contact and the drain contact do not differ too much, so that an etching load effect generated in the process of forming the contact hole by etching is avoided, the size precision of the common source contact and the drain contact is ensured, and the performance of the NAND memory is improved.
In order to make the contents of the present invention more clearly understood, the contents of the present invention will be further described with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
The present invention is described in detail with reference to the drawings, and for convenience of explanation, the drawings are not enlarged partially according to the general scale, and should not be construed as limiting the present invention.
Fig. 2 is a flowchart illustrating a method for forming a NAND memory according to an embodiment of the present invention, and as shown in fig. 2, the method for forming a NAND memory according to the present invention includes the following steps:
step S100: providing a substrate, wherein the substrate comprises a plurality of first active regions and isolation regions which are alternately arranged, and a second active region connected with the first active regions;
step S200: forming a plurality of source selection lines, drain selection lines and word lines on the substrate, wherein the source selection lines, the drain selection lines and the word lines intersect the first active regions, the word lines are located between the source selection lines and the drain selection lines, and the second active regions are located between adjacent source selection lines;
step S300: forming a plurality of common source contacts on the second active regions between adjacent ones of the source select lines, and forming a drain contact on each of the first active regions between adjacent ones of the drain select lines.
Fig. 3 is a top view of a NAND memory according to an embodiment of the invention, referring to fig. 2 and referring to fig. 3, the method for forming the NAND memory according to the invention is described in detail:
in step S100, a substrate 100 is provided, where the substrate 100 includes a plurality of first active regions 110 and isolation regions 120 alternately arranged, and a second active region 120 connected to the first active regions 110.
In the present embodiment, the substrate 100 is a semiconductor substrate, and may be, for example, a Silicon (Si) substrate, a germanium (Ge) substrate, a Silicon germanium (SiGe) substrate, a Silicon On Insulator (SOI), a Germanium On Insulator (GOI), or the like. In other embodiments, the substrate 100 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide (GaAs), indium phosphide (InP), or silicon carbide (SiC), and the like, may also be a stacked structure, such as silicon/silicon germanium (Si/SiGe), and the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) and the like. In this embodiment, the base 100 is a silicon substrate. A doped region or a semiconductor structure may also be formed in the substrate 100, which is not limited in the present invention.
The substrate 100 includes a plurality of first active regions 110 and isolation regions 120 alternately arranged, and a second active region 120 connected to the first active regions 110. The first active region 110 and the isolation region 120 are parallel to each other and extend along a first direction, and the second active region 130 extends along a second direction, preferably, the first direction is perpendicular to the second direction.
As an example, a tunnel insulating layer, a charge storage layer, and an isolation mask may be sequentially formed on the substrate. The isolation mask is formed with a pattern exposing the isolation region. The isolation mask may have a stacked structure including a buffer oxide layer, a nitride layer, and an anti-reflection layer. And then, taking the isolation mask as a mask, etching the charge storage layer, the tunneling insulating layer and the substrate of the isolation region by adopting an etching process, forming a groove in the isolation region, and taking the region without the groove as an active region. Active regions in a region where a common source is later formed are connected to each other as a second active region 130, and active regions alternately arranged with trenches are used as first active regions 110, the first active regions 110 and the second active regions 130 together constituting an active region. And then, removing the isolation mask and then forming an isolation structure in the trench.
In step S200, a plurality of source select lines SSG, drain select lines DSG, and word lines WL0-WLn (e.g., including WL0, WL1, WL2, … …, WLn-2, WLn-1, WLn) are formed on the substrate 100, the word lines WL0-WLn are located between the source select lines SSG and the drain select lines DSG, the source select lines SSG, drain select lines DSG, and word lines WL all intersect the first active region 110, and the second active region 130 is located between adjacent source select lines SSG.
In the present embodiment, the source select line SSG, the drain select line DSG, and the word lines WL0-WLn all extend in the second direction, the word lines WL0-WLn being located between the source select line SSG and the drain select line DSG. The second active region 130 is located between adjacent source selection lines SSG, and two Dummy word lines Dummy are formed between the source selection lines SSG and the bit lines WL0, and two Dummy word lines Dummy are also formed between the drain selection lines DSG and the word lines WLn. The Dummy word line Dummy also extends in the second direction. And the Dummy word line Dummy is formed in the same process step as the word line WL 0-WLn.
As an example, a dielectric layer, a conductive layer for a control gate, and a hard mask layer are sequentially formed on the charge storage layer. And then, with the hard mask layer as a mask, etching the conducting layer, the dielectric layer, the charge storage layer and the tunneling insulating layer to form a source selection line SSG, a drain selection line DSG, a word line WL0-WLn and a virtual word line Dummy. And finally, removing the hard mask layer.
In step S300, a plurality of common source contacts CSC are formed on the second active region 130 between the adjacent source selection lines SSG, and a drain contact CCT is formed on each first active region 110 between the adjacent drain selection lines DSG.
The drain contacts CCT are located on each first active region 110 between adjacent drain select lines DSG, the common source contacts CSC have a rectangular or square cross-section, or other shapes known to those skilled in the art, and the common source contacts CSC are uniformly distributed on the second active region 130. Preferably, each common source contact CSC is located between two adjacent first active regions 110.
As an example, a junction region is formed in the above structure by performing an ion implantation process, and the junction region is formed between the adjacent source select line SSG, drain select line DSG, and adjacent word lines WL 0-WLn. The junction region between the adjacent drain select lines DSG is a drain, the drains are isolated from each other by an isolation structure, and the junction region between the adjacent source select lines SSG is a common source, which is also continuously formed and parallel to the source select lines SSG, because the junction region is continuously connected between the adjacent source select lines SSG.
And then, forming an interlayer insulating layer on the structure, and etching the interlayer insulating layer to form a drain contact hole and a common source contact hole, wherein the drain contact hole exposes the drain, and the common source contact hole exposes the common source. And the common source contact holes have a rectangular, square or other shape known to those skilled in the art, and are uniformly distributed on the second active region 130. Preferably, each common source contact hole is located between two adjacent first active regions 110. Referring to fig. 3 and fig. 1, compared with the prior art, in the embodiment, the common source contact hole is changed from a strip-shaped contact hole to a plurality of contact holes in a long direction or a square shape, and the area difference between the common source contact hole and the drain contact is reduced, so that the etching load effect can be avoided in the process of forming the contact hole by etching.
And finally, filling a material layer in the drain contact hole and the common source contact hole to form a drain contact CCT and a common source contact CSC. The common source contacts CSC are rectangular, square, or other shapes known to those skilled in the art in cross-section and are evenly distributed over the second active region. Preferably, each common source contact CSC is located between two adjacent first active regions 110.
In summary, in the method for forming a NAND memory provided by the present invention, a substrate 100 includes a plurality of first active regions 110 and isolation regions 120 alternately arranged, and a second active region 130 connecting the first active regions 110, a plurality of source select lines SSG, drain select lines DSG, and word lines WL0-WLn intersecting the first active regions 110 are formed on the substrate 100, the word lines WL0-WLn are located between the source select lines SSG and the drain select lines DSG, and the second active region 130 is located between adjacent source select lines SSG, then a plurality of common source contacts CSC are formed on the second active region 130 between adjacent source select lines SSG, a drain contact CCT is formed on each first active region between adjacent drain select lines DSG, i.e., a plurality of common source contacts CCT are formed between adjacent source select lines SSG, a plurality of drain contacts CCT are formed between adjacent drain select lines DSG, compared with the strip-shaped common source electrode contact between the adjacent source electrode selection lines in the prior art, the area difference between the common source electrode contact and the drain electrode contact is reduced, so that an etching load effect generated in the process of forming the contact hole by etching is avoided, the size precision of the common source electrode contact and the drain electrode contact is ensured, and the performance of the NAND memory is improved.
Accordingly, the present invention further provides a NAND memory formed by the method described above, with reference to fig. 3, the NAND memory includes:
a substrate 100, wherein the substrate 100 includes a plurality of first active regions 110 and isolation regions 120 alternately arranged, and a second active region 130 connected to the first active regions 110;
a plurality of source and drain select lines SSG and DSG on the substrate 100, the source and drain select lines SSG and DSG intersecting the first active region 110, and the second active region 130 being between adjacent source select lines SSG;
a plurality of word lines WL0-WLn between the source select line SSG and drain select line DSG;
a plurality of common source contacts CSC on the second active region 130 between the adjacent source selection lines SSG, and a drain contact CCT on each first active region between the adjacent drain selection lines DSG.
Further, the first active region 110 and the isolation region 120 both extend along a first direction, and the second active region 130 extends along a second direction, where the first direction is perpendicular to the second direction.
Further, the source select line SSG, the drain select line DSG, and the word lines WL0-WLn all extend in the second direction.
Further, two Dummy word lines Dummy are provided between the source select line SSG and the word line WL0, and between the drain select line DSG and the word line WLn.
Further, the cross section of the common source contact CSC is rectangular or square, and the common source contacts CSC are uniformly distributed on the second active region 130.
Further, each common source contact CSC is located between two adjacent first active regions 110.
Further, the NAND memory further includes: an isolation structure (not shown) located over the isolation region 120.
In summary, in the NAND memory and the forming method thereof provided by the present invention, the substrate includes a plurality of first active regions and isolation regions alternately arranged, and a second active region connected to the first active regions, a plurality of source select lines, drain select lines, and word lines intersecting the first active regions are formed on the substrate, the word lines are located between the source select lines and the drain select lines, and the second active regions are located between adjacent source select lines, then a plurality of common source contacts are formed on the second active regions between adjacent source select lines, a drain contact is formed on each first active region between adjacent drain select lines, that is, a plurality of common source contacts are formed between adjacent source select lines, a plurality of drain contacts are formed between adjacent drain select lines, as compared with the prior art in which the common source contacts are stripe-shaped between adjacent source select lines, according to the invention, the areas of the common source contact and the drain contact do not differ too much, so that an etching load effect is avoided in the process of forming the contact hole by etching, the size precision of the common source contact and the drain contact is ensured, and the performance of the NAND memory is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (14)
1. A method for forming a NAND memory, comprising:
providing a substrate, wherein the substrate comprises a plurality of first active regions and isolation regions which are alternately arranged, and a second active region connected with the first active regions;
forming a plurality of source selection lines, drain selection lines and word lines on the substrate, wherein the source selection lines, the drain selection lines and the word lines intersect the first active regions, the word lines are located between the source selection lines and the drain selection lines, and the second active regions are located between adjacent source selection lines;
forming a plurality of common source contacts on the second active regions between adjacent ones of the source select lines, and forming a drain contact on each of the first active regions between adjacent ones of the drain select lines.
2. The method of forming a NAND memory of claim 1 wherein the first active region and the isolation region both extend in a first direction and the second active region extends in a second direction, the first direction being perpendicular to the second direction.
3. The method of claim 2, wherein the source select line, the drain select line, and the word line all extend in the second direction.
4. The method of forming a NAND memory as claimed in claim 3, wherein two dummy word lines are formed between the source select line and the word line, and between the drain select line and the word line.
5. The method of claim 1, wherein the common source contact has a rectangular or square cross-section, and a plurality of common source contacts are uniformly distributed on the second active region.
6. The method of forming a NAND memory as claimed in claim 5, wherein each common source contact is located between two adjacent first active regions.
7. The method of forming a NAND memory as claimed in any one of claims 1 to 6, wherein before forming the source select line, the drain select line and the word line, the method further comprises: an isolation structure is formed over the isolation region.
8. A NAND memory, comprising:
the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein the substrate comprises a plurality of first active regions and isolation regions which are alternately arranged, and a second active region connected with the first active regions;
a plurality of source select lines and drain select lines on the substrate, the source select lines and drain select lines intersecting the first active region, and the second active region being located between adjacent source select lines;
a plurality of word lines between the source select line and the drain select line;
a plurality of common source contacts on the second active region between adjacent ones of the source select lines, and a drain contact on each of the first active regions between adjacent ones of the drain select lines.
9. The NAND memory of claim 8, wherein the first active region and the isolation region both extend in a first direction, the second active region extends in a second direction, and the first direction is perpendicular to the second direction.
10. The NAND memory of claim 9, wherein the source select line, drain select line, and word line all extend in the second direction.
11. The NAND memory of claim 10, wherein two dummy word lines are provided between the source select line and the word line, and between the drain select line and the word line.
12. The NAND memory of claim 8 wherein the common source contact is rectangular or square in cross-section and a plurality of the common source contacts are evenly distributed over the second active region.
13. The NAND memory of claim 12 wherein each common source contact is located between two adjacent first active regions.
14. The NAND memory of any of claims 8 to 13, further comprising: an isolation structure located over the isolation region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810786443.6A CN110729303A (en) | 2018-07-17 | 2018-07-17 | NAND memory and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810786443.6A CN110729303A (en) | 2018-07-17 | 2018-07-17 | NAND memory and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110729303A true CN110729303A (en) | 2020-01-24 |
Family
ID=69217575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810786443.6A Pending CN110729303A (en) | 2018-07-17 | 2018-07-17 | NAND memory and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110729303A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112349722A (en) * | 2020-10-15 | 2021-02-09 | 长江存储科技有限责任公司 | Semiconductor device structure and preparation method thereof |
| WO2021254067A1 (en) * | 2020-06-18 | 2021-12-23 | 京东方科技集团股份有限公司 | Thin-film transistor and manufacturing method therefor, display substrate, and display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040076072A1 (en) * | 2002-10-15 | 2004-04-22 | Renesas Technology Corp. | Nonvolatile semiconductor memory device |
| CN101015020A (en) * | 2004-07-06 | 2007-08-08 | 斯班逊有限公司 | Method of improving erase voltage distribution for a flash memory array having dummy wordlines |
| CN101174635A (en) * | 2006-10-31 | 2008-05-07 | 海力士半导体有限公司 | Flash memory device and method of manufacturing the same |
| CN105742290A (en) * | 2011-03-04 | 2016-07-06 | 海力士半导体有限公司 | Nonvolatile memory device, method of fabricating the same, and method of operating the same |
| US20170069642A1 (en) * | 2014-10-31 | 2017-03-09 | SK Hynix Inc. | Nonvolatile memory devices having single-layered gates |
| CN106653759A (en) * | 2016-12-23 | 2017-05-10 | 武汉新芯集成电路制造有限公司 | Flash memory structure and manufacturing method thereof |
-
2018
- 2018-07-17 CN CN201810786443.6A patent/CN110729303A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040076072A1 (en) * | 2002-10-15 | 2004-04-22 | Renesas Technology Corp. | Nonvolatile semiconductor memory device |
| CN101015020A (en) * | 2004-07-06 | 2007-08-08 | 斯班逊有限公司 | Method of improving erase voltage distribution for a flash memory array having dummy wordlines |
| CN101174635A (en) * | 2006-10-31 | 2008-05-07 | 海力士半导体有限公司 | Flash memory device and method of manufacturing the same |
| CN105742290A (en) * | 2011-03-04 | 2016-07-06 | 海力士半导体有限公司 | Nonvolatile memory device, method of fabricating the same, and method of operating the same |
| US20170069642A1 (en) * | 2014-10-31 | 2017-03-09 | SK Hynix Inc. | Nonvolatile memory devices having single-layered gates |
| CN106653759A (en) * | 2016-12-23 | 2017-05-10 | 武汉新芯集成电路制造有限公司 | Flash memory structure and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 拉扎维: "《模拟CMOS集成电路设计》", 28 February 2003, 西安交通大学出版社 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021254067A1 (en) * | 2020-06-18 | 2021-12-23 | 京东方科技集团股份有限公司 | Thin-film transistor and manufacturing method therefor, display substrate, and display device |
| CN112349722A (en) * | 2020-10-15 | 2021-02-09 | 长江存储科技有限责任公司 | Semiconductor device structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114121818B (en) | Semiconductor device and method of forming the same | |
| KR101524823B1 (en) | 3-dimensional semiconductor device | |
| KR100640620B1 (en) | NOR type flash memory device having twin bit cell scheme | |
| KR20190118751A (en) | Semiconductor device | |
| US20200194373A1 (en) | Three-dimensional semiconductor memory devices | |
| KR20210082259A (en) | Memory Arrays and Methods Used to Form Memory Arrays | |
| US11107826B2 (en) | Semiconductor memory device | |
| KR20190133362A (en) | Semiconductor device and manufacturing method thereof | |
| KR20080010900A (en) | Non-volatile memory device, method of operating the same and method of fabricating the same | |
| US20210351199A1 (en) | Three-dimensional semiconductor memory device and method of detecting electrical failure thereof | |
| KR20110094985A (en) | Three dimensional semiconductor memory device and method of operating the same | |
| KR20210080571A (en) | Memory Arrays and Methods Used to Form Memory Arrays | |
| JP2018160593A (en) | Semiconductor device and method for manufacturing the same | |
| US20230102075A1 (en) | Semiconductor device | |
| KR20230047181A (en) | NOR type memory device, manufacturing method thereof, and electronic device including the memory device | |
| US9640432B2 (en) | Memory device structure and fabricating method thereof | |
| CN110729303A (en) | NAND memory and forming method thereof | |
| US20140284682A1 (en) | Nonvolatile semiconductor storage device | |
| CN111816673A (en) | Magnetic random access memory and forming method thereof | |
| US10998378B2 (en) | Method for producing transistors, in particular selection transistors for non-volatile memory, and corresponding device | |
| KR100810414B1 (en) | Flash memory device and method of manufacturing the same | |
| JPH02360A (en) | Manufacture of non-volatile semiconductor device | |
| JP2002141425A (en) | Side wall process for improving flash memory cell performance | |
| CN109411479B (en) | Semiconductor device and manufacturing method thereof | |
| US10002906B2 (en) | Method for fabricating an array of diodes, in particular for a non-volatile memory, and corresponding device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200124 |
|
| RJ01 | Rejection of invention patent application after publication |