CN113540970A

CN113540970A - VCSEL chip, manufacturing method and laser chip

Info

Publication number: CN113540970A
Application number: CN202110808432.5A
Authority: CN
Inventors: 祝进田
Original assignee: Jiechuang Semiconductor Suzhou Co ltd
Current assignee: Jiechuang Semiconductor Suzhou Co ltd
Priority date: 2021-07-16
Filing date: 2021-07-16
Publication date: 2021-10-22
Anticipated expiration: 2041-07-16
Also published as: CN113540970B

Abstract

The invention discloses a VCSEL chip, a manufacturing method and a laser chip, wherein the VCSEL chip comprises the following components: a semi-insulating substrate; a buffer layer formed on the semi-insulating substrate; the VCSEL epitaxial structure grows on the surface of the buffer layer, which is far away from the semi-insulating substrate; and the p-side electrode extends to the semi-insulating substrate from the surface of the VCSEL epitaxial structure, which is far away from the semi-insulating substrate, and an air gap is formed between the p-side electrode and the side surface of the VCSEL epitaxial structure at an interval. The p electrode of the invention adopts a suspended electrode, and air is arranged below the suspended electrode, so that the capacitance introduced by the p electrode is almost zero, and the working speed of the chip is maximum.

Description

VCSEL chip, manufacturing method and laser chip

Technical Field

The invention belongs to the technical field of semiconductor lasers, and particularly relates to a VCSEL chip, a manufacturing method and an electronic device.

Background

The III-V compound semiconductor high-speed VCSEL chip is a core device for optical communication. The method has more and more extensive application in the fields of Data Centers (DC), active cables (AOC), HDMI and the like. With the increase of the capacity of transmitting information and the increase of the transmission speed, the requirements on the conversion speed of the electro-optical conversion device are higher and higher. The general parameter affecting the laser operation rate is the product of RC (R is the series resistance of the chip, and C is the capacitance of the chip), and the smaller R and C are, the faster the operation rate of the device is.

In the prior art, a VCSEL chip generally includes a substrate and an epitaxial structure grown on the substrate, a p-side electrode extends from a top end of the epitaxial structure to a position below the epitaxial structure along a sidewall of the epitaxial structure, and in the structure, an insulating medium is disposed between the p-side electrode and the sidewall of the epitaxial structure, so that a capacitance of the whole chip is relatively large.

In addition, in order to reduce the capacitance of the device, the chip is usually made smaller and smaller, but when the chip size is small to a certain extent, the resistance of the device becomes larger and larger, so that the product of RC is basically unchanged or even becomes larger, and the working rate of the chip cannot be further improved.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

Disclosure of Invention

The invention aims to provide a VCSEL chip, a manufacturing method and an electronic device, which can greatly reduce the capacitance of the chip and improve the working rate of the chip.

To achieve the above object, an embodiment of the present invention provides a VCSEL chip including:

a semi-insulating substrate;

a buffer layer formed on the semi-insulating substrate;

the VCSEL epitaxial structure grows on the surface of the buffer layer, which is far away from the semi-insulating substrate;

and the p-side electrode extends to the semi-insulating substrate from the surface of the VCSEL epitaxial structure, which is far away from the semi-insulating substrate, and an air gap is formed between the p-side electrode and the side surface of the VCSEL epitaxial structure at an interval.

In one or more embodiments of the present invention, the VCSEL epitaxial structure includes an N-type DBR, an active layer, an oxidation confinement layer, a P-type DBR, and an ohmic contact layer sequentially formed on a buffer layer.

In one or more embodiments of the invention, the semiconductor device further comprises a suspension space formed by etching the VCSEL epitaxial structure towards the semi-insulating substrate, and through which the p-side electrode extends.

In one or more embodiments of the present invention, the suspension space includes:

the first space is obtained by etching the ohmic contact layer to the N-type DBR or the N-type DBR with a certain depth;

the second space is obtained by etching the exposed region of the N-type DBR to the buffer layer or the buffer layer with a certain depth;

a third space obtained by etching the exposed region of the buffer layer to the semi-insulating substrate or the semi-insulating substrate to a certain depth,

the p-side electrode sequentially passes through the first space, the second space and the third space.

In one or more embodiments of the present invention, the p-side electrode extends in a linear direction within the suspension space.

In one or more embodiments of the present invention, the p-side electrode has a thickness of 3 to 5 μm, and/or

The width of the p-side electrode is 10-15 μm.

In one or more embodiments of the present invention, the semiconductor device further includes an n-side electrode disposed on an exposed region of the buffer layer where the VCSEL epitaxial structure is not disposed.

In one or more embodiments of the invention, the semi-insulating substrate is a semi-insulating GaAs substrate,

the buffer layer is an N-type GaAs layer.

The embodiment of the invention provides a method for manufacturing a VCSEL chip, which comprises the following steps:

sequentially growing a buffer layer and a VCSEL epitaxial structure on a semi-insulating substrate;

etching the VCSEL epitaxial structure to a certain depth inside the buffer layer or the buffer layer to form a buffer layer exposed region, and manufacturing an n-side electrode in the buffer layer exposed region;

etching the VCSEL epitaxial structure to a certain depth inside the semi-insulating substrate or the semi-insulating substrate to form a semi-insulating substrate exposed area;

and manufacturing a suspended p-side electrode between the top surface of the VCSEL epitaxial structure and the exposed region of the semi-insulating substrate, wherein an air gap is formed between the p-side electrode and the side surface of the VCSEL epitaxial structure at an interval.

An embodiment of the present invention provides a laser chip, including:

a semi-insulating substrate;

an epitaxial structure grown on the semi-insulating substrate;

Compared with the prior art, the p electrode adopts a suspended electrode, and air is arranged below the suspended electrode, so that the capacitance introduced by the p electrode is almost zero, and the working speed of the chip is maximized.

Drawings

FIG. 1 is a schematic structural diagram of a VCSEL chip according to an embodiment of the invention;

fig. 2-8 are flow diagrams of fabrication of VCSEL chips according to an embodiment of the present invention.

Detailed Description

The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.

A laser chip according to a preferred embodiment of the present invention includes:

a semi-insulating substrate;

an epitaxial structure grown on the semi-insulating substrate;

The laser chip of this case can be applied to laser chips such as DFB, EML and VCSEL, through the unsettled of p side electrode, can make the modulation speed maximize of chip.

Hereinafter, a VCSEL chip is exemplified, and as shown in fig. 1, a VCSEL chip according to a preferred embodiment of the present invention includes:

a semi-insulating substrate 10;

a buffer layer 20 formed on the semi-insulating substrate 10;

a VCSEL epitaxial structure 30 grown on a surface of the buffer layer 20 facing away from the semi-insulating substrate 10;

and the p-side electrode 40 extends from the surface of the VCSEL epitaxial structure 30, which faces away from the semi-insulating substrate 10, to the semi-insulating substrate 10, and an air gap 50 is formed between the p-side electrode 40 and the side face of the VCSEL epitaxial structure 30 in a spaced mode.

In the present case, the p-side electrode 40 spans the upper and lower ends of the epitaxial structure and is suspended in the air, so that an air medium is formed between the p-side electrode and the side surface of the epitaxial structure, and the dielectric constant of the air is the minimum, compared with the mode of attaching the electrode to the side wall of the epitaxial structure in the prior art, the chip capacitance can be greatly reduced, and compared with the mode, the working rate can be improved by more than 50%.

In one embodiment, the semi-insulating substrate 10 is a semi-insulating GaAs substrate, and the buffer layer 20 is an N-type GaAs layer. The buffer layer 20 serves to isolate the influence of defects of the semi-insulating substrate 10 on the upper epitaxial material.

In one embodiment, the VCSEL epitaxial structure 30 includes an N-type DBR31, an active layer 32, an oxide confinement layer 33, a P-type DBR34, and an ohmic contact layer 35 sequentially formed on the buffer layer 20.

The P-type DBR33 and the N-type DBR31 are structures formed in a plurality of periods in a pair-wise manner by two different refractive index materials alternately arranged. In an embodiment, the DBR may include an AlAs layer and an AlGaAs layer stacked in sequence, and the material of the DBR is not specifically limited in this application and needs to be specifically selected according to the actual application.

The active layer 32 is formed on the N-type DBR31 for providing gain-generated laser, and in some embodiments of the invention, the active layer 32 is a single layer of quantum well, quantum dot, and quantum wire structure, or a multilayer of quantum well, quantum dot, and quantum wire structure, etc.; and/or the material of the active layer is any active medium material, such as one of the following materials: a group III-V semiconductor material or a group II-VI semiconductor material; and/or the gain peak wavelength range of the active layer covers the near ultraviolet to infrared bands.

In some examples, the III-V semiconductor material is, for example, GaAs/A1GaAs, InP/InGaAsP, GaN/AlGaN, or the like, and the II-VI semiconductor material is, for example, ZnO.

The oxide confinement layer 33 is disposed between the active layer 32 and the P-type DBR34, and serves to form a current confinement aperture through which a current injected into the active layer is confined.

The ohmic contact layer 35 is preferably a p-type GaAs material.

In one embodiment, the suspension space 60 is formed by etching the VCSEL epitaxial structure 30 toward the semi-insulating substrate 10, and the p-side electrode 40 extends through the suspension space.

In the present embodiment, the suspension space 60 is a space left by etching the epitaxial structure 30 or the buffer layer 20, so that on one hand, the size of the chip can be reduced, and on the other hand, the p-side electrode can be extended by using the space.

In a specific embodiment, in order to facilitate the extension of the p-side electrode with the shortest distance and fully consider the arrangement of the n-side electrode, the suspension space 60 is formed by penetrating the following spaces:

a first space 61 etched from the ohmic contact layer 35 to a depth of the N-type DBR31 or the N-type DBR 31;

the second space 62 is obtained by etching the exposed region of the etched N-type DBR31 to the buffer layer 20 or the buffer layer 20 with a certain depth;

the third space 63 is obtained by etching the exposed region of the buffer layer 63 to the semi-insulating substrate or a certain depth of the semi-insulating substrate.

The p-side electrode 40 is formed by etching a space, sequentially penetrates through the first space 61, the second space 62 and the third space 63, and is then connected to the semi-insulating substrate 10.

In another embodiment, the suspending space 60 may also be directly etched from the ohmic contact layer 35 to the semi-insulating substrate or a certain depth of the semi-insulating substrate.

In a preferred embodiment, the p-side electrode 40 extends in a linear direction within the suspension space 60. The p-side electrode 40 is inclined at an angle with respect to the semi-insulating substrate 10, which may be determined according to the width of the suspension space 60 in the horizontal direction and the height in the vertical direction, for example, the angle may be 30 to 60 degrees.

In other embodiments, the suspended portion of the p-side electrode 40 may also extend in a zigzag manner or in a certain arc manner, which is not limited in the present application.

In one embodiment, the p-side electrode is made of Au, Ti/Au or Ti/Pt/Au, so as to have a certain self-supporting force, the thickness of the p-side electrode 40 is preferably 3-5 μm, and the width of the p-side electrode 40 is 10-15 μm.

In one embodiment, the device further includes an n-side electrode 70, and the n-side electrode 70 is disposed on an exposed region of the buffer layer 20 where the VCSEL epitaxial structure 30 is not disposed. The exposed region of the buffer layer 20 where the VCSEL epitaxial structure 30 is not located is formed during the fabrication of the second space 62 as described above. To avoid interference with the p-side electrode 40, an n-side electrode 70 is provided on the other side of the chip opposite the p-side suspension electrode.

The N-side electrode 70 may be of AuGeNi/Au, Au/Ge/Ni, or Au/Ge structure.

In one embodiment, the semi-insulating substrate 10 is a semi-insulating GaAs substrate, and the buffer layer 20 is an N-type GaAs layer.

As shown in fig. 2 to 8, a method for fabricating a VCSEL chip according to a preferred embodiment of the present invention includes the steps of:

step s1, referring to fig. 2, provides a semi-insulating GaAs substrate 10, and then grows an N-type GaAs buffer layer 20 and a VCSEL epitaxial structure 30 on the semi-insulating GaAs substrate 10 using MOCVD (metal organic chemical vapor phase epitaxy) technique, where the VCSEL epitaxial structure 30 includes an N-type DBR31, an active layer 32, a P-type DBR33, and an ohmic contact layer 34 sequentially formed on the N-type GaAs buffer layer 20. The ohmic contact layer 34 employs a p-type GaAs layer.

Step s2, referring to fig. 3, depositing a silicon dioxide or silicon nitride mask layer (not shown) on the surface of the ohmic contact layer 34; then coating electron beam glue or photoresist on the silicon dioxide or silicon nitride mask layer, and forming a patterned mask on the electron beam glue or the photoresist by using an electron beam exposure process or a nano-imprint technology; the epitaxial structure grown in step s1 is then etched to a depth of the N-type DBR31 or N-type DBR31 to obtain the first space 61.

Step s3, referring to fig. 4, the structure formed in step s2 is placed in a wet oxidation furnace and wet oxidation is performed to form a dense uniform oxidation limiting layer 33. The oxide confinement layer 33 is used to form a current confinement aperture through which current injected into the active layer is confined.

In step s4, referring to fig. 5, an ohmic contact 41 is formed on the top surface of the ohmic contact layer 34, and the ohmic contact 41 may be made of Au, Ti/Au, or Ti/Pt/Au.

The ohmic contact 41 may be formed by a sputtering method, but is not limited thereto, and may be formed by an electron beam evaporation method or a thermal evaporation method.

Step s5, referring to fig. 6, the second space 62 is obtained by etching the exposed region of the N-type DBR31 to the buffer layer 20 or the buffer layer 20 to a certain depth by ICP etching.

Step s6, referring to fig. 7, an n-side electrode 70 is fabricated in the exposed region of the buffer layer 20 where the VCSEL epitaxial structure is not disposed, where the n-side electrode 70 may be an AuGeNi/Au, Au/Ge/Ni, or Au/Ge structure.

The n-side electrode 70 may be formed by a sputtering method, but is not limited thereto, and may be formed by an electron beam evaporation method or a thermal evaporation method.

Step s7, referring to fig. 8, etching the exposed region of the buffer layer 20 to the semi-insulating substrate 10 or the semi-insulating substrate 10 by ICP etching to a certain depth, so as to obtain the second space 63.

In step s8, referring to fig. 1, the suspended p-side electrode 40 is fabricated by photolithography, sputtering (Sputter) and metal Plating (Au Plating). The p-side electrode 40 extends from the ohmic contact 41 to the semi-insulating substrate 10, and the suspended portion extends linearly, so that a certain air gap is formed between the suspended portion and the side surface of the chip.

In the scheme, a region where a p-side electrode is to be manufactured is filled with photoresist, and the size and the position of sputtered metal are defined through photoetching; then sputtering to form a first layer of metal in the electrode area, wherein the metal material manufactured by the sputtering technology is firmly contacted with other materials and is not easy to fall off; further forming the size and the position of the electroplated metal by etching the photoresist; and finally, a second layer of metal is formed by electroplating, and the supporting strength of the metal can be enhanced by electroplating, so that the metal is not easy to break.

The P-side electrode manufactured by the method has the advantages that the whole pad part is arranged on the semi-insulating GaAs substrate, the whole part of the connecting pad and the P ohmic contact is suspended in the air, and the capacitance introduced by the P-side electrode is almost zero, so that the modulation speed of laser chips such as DFBs, EMLs and VCSELs manufactured by the method can be maximized.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

1. A VCSEL chip, comprising:

a semi-insulating substrate;

a buffer layer formed on the semi-insulating substrate;

2. The VCSEL chip of claim 1, wherein the VCSEL epitaxial structure comprises an N-type DBR, an active layer, an oxide confinement layer, a P-type DBR, and an ohmic contact layer sequentially formed on a buffer layer.

3. The VCSEL chip of claim 1 or 2, further comprising a suspension space formed by etching the VCSEL epitaxial structure toward the semi-insulating substrate for the p-side electrode to extend through.

4. The VCSEL chip of claim 3, wherein the suspension space comprises:

5. The VCSEL chip of claim 3, wherein the p-side electrode extends in a linear direction within the hanging space.

6. The VCSEL chip of claim 1, wherein a thickness of the p-side electrode is 3 to 5 μm, and/or

The width of the p-side electrode is 10-15 μm.

7. The VCSEL chip of claim 1, further comprising an n-side electrode disposed on an exposed region of the buffer layer where the VCSEL epitaxial structure is not disposed.

8. The VCSEL chip of claim 1, wherein the semi-insulating substrate employs a semi-insulating GaAs substrate,

the buffer layer is an N-type GaAs layer.

9. A method of fabricating a VCSEL chip in accordance with any of claims 1 to 8, comprising:

10. A laser chip, comprising:

a semi-insulating substrate;

an epitaxial structure grown on the semi-insulating substrate;