CN113536719A - PCB simulation circuit and PCB simulation circuit analysis method - Google Patents
PCB simulation circuit and PCB simulation circuit analysis method Download PDFInfo
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- CN113536719A CN113536719A CN202010286968.0A CN202010286968A CN113536719A CN 113536719 A CN113536719 A CN 113536719A CN 202010286968 A CN202010286968 A CN 202010286968A CN 113536719 A CN113536719 A CN 113536719A
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Abstract
The invention provides a PCB board simulation circuit, which comprises a main analog frequency signal source, a main analog frequency signal source and a PCB board simulation circuit, wherein the main analog frequency signal source is used for providing a plurality of signals including clock signals and data signals; the S parameter integration module is connected with the main analog frequency signal source and is used for integrating S parameters corresponding to communication signal routing of the PCB; the communication line balancing circuit is connected with the S parameter integration module and is used for balancing the clock signal and the data signal output by the S parameter integration module respectively; and the chip port circuit is used for carrying out simulation modeling on the chip in the PCB. The PCB simulation circuit obtained through the design of the simulation circuit has a forward direction guiding value, and meanwhile, the electromagnetic compatibility of the communication signals of the PCB can be effectively improved. The invention also provides an analysis method of the PCB simulation circuit, namely, the PCB simulation circuit is operated, and the obtained result is highly consistent with the result of the experimental test.
Description
Technical Field
The invention relates to the field of circuit design, in particular to a PCB (printed circuit board) simulation circuit and a PCB simulation circuit analysis method.
Background
The automotive industry has increasingly demanded higher data transmission, resulting in increasing demand for microsecond communications. Microsecond communication, as the name implies, is a communication signal with a communication period in microseconds, i.e., a communication frequency in the order of MHz. Microsecond communication can well meet the requirements of the communication aspect in an automobile PCB, and on the other hand, microsecond communication frequency is high, change is fast, and the electromagnetic compatibility standard of the automobile gauge adopted in the test is severe, so that the factors can bring about a very large risk of exceeding the standard of electromagnetic radiation. In previous practical applications, the following methods are generally used to deal with the problem of electromagnetic compatibility of microsecond communication signals:
(1) the communication frequency is finely adjusted so that the frequency point does not fall within the range of the test standard, but the frequency point is difficult to be effective for the items of which the customers specify the communication frequency or the full frequency band with the test requirements.
(2) According to the electromagnetic compatibility test result of the whole vehicle, risks are evaluated, the assessment standard is reduced or deviation acceptance of customers is sought, but the scheme sometimes hardly persuade the customers.
(3) According to the prior art, trial rectification is carried out on the circuit, but the scheme has certain blindness, and possible methods need to be tried one by one, and the scheme lacks forward direction guiding value.
Disclosure of Invention
The invention aims to provide a PCB simulation circuit and a PCB simulation circuit analysis method, which can reliably and credibly perform simulation analysis on a PCB, and further can provide a forward design scheme for improving the electromagnetic compatibility of PCB communication signals so as to solve the problem of electromagnetic compatibility.
In order to achieve the above object, the present invention provides a PCB board simulation circuit, including:
a main analog frequency signal source for providing a plurality of signals including a clock signal and a data signal according to a real signal of the PCB board;
the S parameter integration module is connected with the main analog frequency signal source and used for integrating S parameters corresponding to communication signal routing of the PCB, and the S parameters are scattering parameters;
the communication line balancing circuit is connected with the S parameter integrated module and is used for balancing the clock signal and the data signal output by the S parameter integrated module respectively;
and the chip port circuit is used for carrying out simulation modeling on the chip in the PCB.
Optionally, in the PCB board simulation circuit, the main analog frequency signal source includes a plurality of pulse sources for providing corresponding frequency signals and at least one analog resistor, and one end of each of the pulse sources and the analog resistors is grounded, and the other end of each of the pulse sources and the analog resistors is connected to a corresponding input terminal of the S parameter integration module.
Optionally, in the PCB board simulation circuit, the plurality of signals include an uplink frequency signal, a downlink differential clock signal, and a downlink differential data signal, where the downlink differential clock signal includes a downlink differential clock negative signal and a downlink differential clock positive signal, and the downlink differential data signal includes a downlink differential data negative signal and a downlink differential data positive signal.
Optionally, in the PCB board simulation circuit, the communication line balancing circuit includes a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, and a second capacitor; one end of a second resistor, one end of a third resistor and one end of a first capacitor are connected with each other, the other end of the first capacitor is grounded, the other end of the second resistor is connected with one end of the S parameter integration module, which is used for outputting a positive signal of a downlink differential clock, the other end of the third resistor is connected with one end of the S parameter integration module, which is used for outputting a negative signal of the downlink differential clock, and the second resistor, the third resistor and the first capacitor form a clock balancing circuit, which is used for balancing the downlink differential clock signal; one ends of the fourth resistor, the fifth resistor and the second capacitor are connected with each other, the other end of the second capacitor is grounded, the other end of the fourth resistor is connected with one end of the S parameter integration module, which is used for outputting the downlink differential data positive signal, the other end of the fifth resistor is connected with one end of the S parameter integration module, which is used for outputting the downlink differential data negative signal, and the fourth resistor, the fifth resistor and the second capacitor form a data balance circuit, which is used for balancing the downlink differential data signal.
Optionally, in the PCB simulation circuit, the PCB simulation circuit further includes a differential mode filter circuit, the differential mode filter circuit includes a first differential mode filter capacitor and a second differential mode filter capacitor, and two ends of the first differential mode filter capacitor are respectively connected to one end of the S parameter integration module for outputting a negative signal of the downlink differential clock and one end of the S parameter integration module for outputting a positive signal of the downlink differential clock; and two ends of the second differential-mode filter capacitor are respectively connected with one end of the S parameter integration module for outputting the downlink differential data negative signal and one end of the S parameter integration module for outputting the downlink differential data positive signal.
Optionally, in the PCB simulation circuit, the PCB simulation circuit further includes a common mode filter circuit, the common mode filter circuit includes four common mode filter capacitors, and four ends of the common mode filter capacitors are respectively connected to one end of the S parameter integration module for outputting a positive signal of the downlink differential clock, one end of the S parameter integration module for outputting a negative signal of the downlink differential clock, one end of the S parameter integration module for outputting a positive signal of the downlink differential clock, and one end of the S parameter integration module for outputting a negative signal of the downlink differential clock, and the other ends of the common mode filter capacitors are all grounded.
Optionally, in the PCB simulation circuit, the S parameter integrated module is integrated with S parameters extracted by using each input pin and each output pin of each chip as a port, and the S parameters are obtained through testing or simulation.
Optionally, in the PCB board simulation circuit, the chip port circuit simplifies each chip on the PCB board into one path of matching impedance having a corresponding resistance value.
In order to achieve the above and other related objects, the present invention further provides a method for analyzing a PCB board simulation circuit, including:
the method comprises the following steps: carrying out simulation modeling on a signal source, communication signal wiring, a communication line balance circuit and a chip of the PCB to obtain a PCB simulation circuit, wherein the step of carrying out simulation modeling on the signal source of the PCB comprises the following steps: providing a plurality of signals including a clock signal and a data signal according to a real signal of the PCB; the step of carrying out simulation modeling on the communication signal routing of the PCB comprises the following steps: gathering S parameters corresponding to communication signal routing of the PCB, wherein the S parameters are scattering parameters; the step of performing simulation modeling on the communication line balance circuit of the PCB comprises the following steps: balancing the clock signal and the data signal respectively;
step two: and operating the PCB simulation circuit to obtain a simulation result.
Optionally, in the method for analyzing a PCB board simulation circuit, before or after the second step, a differential mode filter circuit and/or a common mode filter circuit are added to the PCB board simulation circuit, and the PCB board simulation circuit added with the differential mode filter circuit and/or the common mode filter circuit is operated to obtain a simulation result.
In summary, the present invention provides a PCB simulation circuit, wherein the PCB simulation circuit obtained by the design of the simulation circuit has a forward direction guiding value, and in practical application, the circuit and the trace of the PCB can be optimized, supplemented or corrected according to the simulation result, so as to effectively improve the magnetic compatibility of the PCB communication signal, especially the microsecond communication signal of the PCB, and finally solve the problem of electromagnetic compatibility. The forward design is carried out by utilizing simulation, so that the cost of product design can be effectively reduced. The scheme saves the cost in the aspects of manpower and material resources, can be conveniently applied to the design of other similar differential communication signal circuits, and has better application prospect.
The simulation result obtained by the PCB simulation circuit analysis method provided by the invention is highly consistent with the result of an experimental test, the PCB simulation circuit can be established by the method, the PCB simulation circuit is more accurate, and the simulation analysis method is more scientific and has higher reliability.
Drawings
FIG. 1 is a schematic diagram of a PCB simulation circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a PCB simulation circuit added with a differential mode filter circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a PCB simulation circuit with an added common mode filter circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a PCB simulation circuit added with a common mode filter circuit and a differential mode filter circuit according to an embodiment of the present invention;
FIG. 5 is a simulation result of radiation emission of a PCB board simulation circuit according to an embodiment of the present invention;
FIG. 6 shows a PCB circuit radiation emission test result in an embodiment of the present invention;
FIG. 7 is a simulated result of radiation emission of a PCB board simulation circuit added with a differential mode filter circuit according to an embodiment of the present invention;
FIG. 8 is a simulation result of radiation emission of a PCB board simulation circuit added with a common mode filter circuit according to an embodiment of the present invention;
FIG. 9 is a simulation result of radiation emission of a PCB simulation circuit added with a common mode filter circuit and a differential mode filter circuit according to an embodiment of the present invention;
in fig. 1-9:
1-a main analog frequency signal source, a 2-S parameter integration module, a 3-communication line balancing circuit and a 4-chip port circuit.
Detailed Description
The PCB simulation circuit proposed by the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The microsecond communication is a communication signal with the communication frequency in the magnitude of MHz, so that the requirement on communication in an automobile PCB can be well met, and on the other hand, the microsecond communication frequency is high and is fast in change, and meanwhile, the electromagnetic compatibility standard of an automobile gauge adopted in the test is severe, and the factors can bring a very large risk of exceeding the standard of electromagnetic radiation. In previous practical applications, the following methods are generally used to deal with the problem of electromagnetic compatibility of microsecond communication signals:
(1) finely adjusting the communication frequency to ensure that the frequency point does not fall within the range of the test standard;
but this scheme is difficult to work for items that have customer-specified communication frequencies or full frequency bands with testing requirements.
(2) According to the electromagnetic compatibility test result of the whole vehicle, evaluating the risk, and reducing the assessment standard or seeking the deviation acceptance of customers;
but such a solution can sometimes be difficult to persuade a customer.
(3) Trial rectification is carried out on the circuit according to the previous rectification experience;
however, this solution is somewhat blind and requires trial-and-error of possible methods, and lacks positive guidance.
The invention provides a PCB simulation circuit, aiming at solving the problem of electromagnetic compatibility and improving the electromagnetic compatibility of PCB communication signals, in particular microsecond communication signals of the PCB. The circuit designed by the invention can effectively reduce the electromagnetic radiation level of microsecond communication signals on the PCB and solve the problem of electromagnetic compatibility.
Referring to fig. 1, the PCB board simulation circuit includes:
a main analog frequency signal source 1 for providing a plurality of signals including a clock signal and a data signal according to a real signal of a PCB board;
the S parameter integration module 2 is connected with the main analog frequency signal source 1, the S parameter integration module 2 is used for integrating S parameters corresponding to communication signal routing of the PCB, and the S parameters are scattering parameters;
the communication line balancing circuit 3 is connected with the S parameter integrated module 2, and the communication line balancing circuit 3 is used for balancing the clock signal and the data signal output by the S parameter integrated module 2 respectively;
and the chip port circuit 4 is used for carrying out simulation modeling on the chip in the PCB.
The main analog frequency signal source 1 may be configured according to the frequency, duty ratio, rise time, and fall time of the real signal of the PCB. For example, the main analog frequency signal source 1 includes a plurality of pulse sources for providing corresponding frequency signals and at least one analog resistor, and the normal operating frequency of each pulse source can be adjusted according to the real signals of the PCB board. Further, the main analog frequency signal source 1 includes first to fifth pulse sources S1-S5 and an analog resistor R1, wherein the first pulse source S1 simulates an uplink (chip to MCU) frequency signal, and the normal operating frequency thereof is preferably 1 MHz-100 MHz; the second pulse source S2 and the third pulse source S3 simulate a downstream (MCU to chip) differential clock signal, and the normal working frequency is preferably 1 MHz-100 MHz; the fourth pulse source S4 and the fifth pulse source S5 simulate downstream (MCU to chip) differential data signals, and the working frequency is preferably 1 MHz-100 MHz. That is, the plurality of signals include an uplink frequency signal, a downlink differential clock signal, and a downlink differential data signal, where the downlink differential clock signal includes a downlink differential clock negative signal and a downlink differential clock positive signal, and the downlink differential data signal includes a downlink differential data negative signal and a downlink differential data positive signal. The analog resistor R1 can be an analog enable signal connection resistor, the resistance value of the analog resistor R1 can be adjusted according to the real signal of the PCB, and the enable signal is always set at the valid bit when the analog resistor R1 works normally, so the analog resistor R1 is in a communication state by default, namely, the analog resistor R1 is directly connected through a certain resistor, and further, the preferred resistor R1 is 25-75 ohms.
The S parameter integration module 2 integrates S parameters extracted by using each input pin and each output pin of each chip as a port, and the chips include control chips such as an MCU and various functional chips such as a memory chip and a clock chip connected to the control chips such as the MCU. The S Parameter, also called scattering Parameters (S-Parameters) can reflect reflection, impedance matching, transmission characteristics of a signal, crosstalk condition of a signal, and the like, and the integrity condition of a signal can be well reflected by using the S Parameter, so the S Parameter is an important Parameter in microwave transmission. The S parameter is a network parameter established on the basis of the relationship between incident waves and reflected waves. In microwave circuit analysis, the S-parameter is used to describe the reflected signal at a port of the device and the intensity of the signal energy propagating from that port to another port. The process of the S parameter integration module 2 for collecting the S parameters corresponding to the PCB communication signal routing mainly includes: and analyzing and importing the S parameter. The analysis of the S parameter may be obtained through testing or simulation, the simulation is performed based on simulation software to obtain the S parameter in this embodiment, and the specific process includes: firstly, carrying out lamination setting according to the actual condition of a PCB; then, ports, such as a Serial Data Output signal line (SDO), a Frequency Clock Negative signal line (FCLN), a Frequency Clock Positive signal line (FCLP), a Serial Input Negative signal line (SIN), a Serial Input Positive signal line (SIP), and a low level active signal line (CSN), are added to both ends of the signal line to be analyzed; and finally, setting a solving frequency (1 MHz-100 MHz) according to the signal frequency, and operating software to solve an S parameter, wherein the S parameter document is output in a file of 'S12P'. The importing of the S parameter comprises: firstly, adding a blank multi-port S parameter integrated module in the PCB simulation circuit; the S parameter integration module and the exported ". S12P" file are then linked to enable import of the S parameters. The S parameters can conveniently and accurately replace real PCB wiring, and can truly reflect the mutual influence among the wirings, namely the S parameters led into the S parameter integrated module 2 can very simply and accurately express the wiring of a PCB microsecond communication signal actual transmission circuit. Therefore, it is convenient, fast, accurate and efficient to use S parameters to replace the cumbersome PCB.
After the step of gathering the S parameters corresponding to the traces of the PCB by the S parameter integrated module 2, each port of the S parameter integrated module 2 is connected to a corresponding circuit device (such as a pulse source, a load) respectively, so as to complete a simulation circuit in which the S parameters are used to replace a real circuit, and the electromagnetic compatibility analysis of the PCB communication signals, especially microsecond communication signals of the PCB, can be performed based on the circuit.
The communication line balancing circuit 3 is designed based on previous experience, and aims to improve the signal-to-noise ratio and EMC (electromagnetic compatibility) performance of the corresponding differential signal line. The communication line balancing circuit 3 may be adjusted according to a frequency signal provided by a main analog frequency signal source 1, for example, when the signal in the main analog frequency signal source 1 includes a downlink differential clock signal and a downlink differential data signal, the communication line balancing circuit 3 may include a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1 and a second capacitor C2, wherein one end of the second resistor R2, one end of the third resistor R3 and one end of the first capacitor C1 are connected to each other, the other end of the first capacitor C1 is Grounded (GND), the other end of the second resistor R2 is connected to one end of the S parameter integrating module 2 for outputting a downlink differential clock positive signal, the other end of the third resistor R3 is connected to one end of the S parameter integrating module 2 for outputting a downlink differential clock negative signal, and the second resistor R2, the third resistor R3, the third resistor R3, and the third resistor R1 are connected to one end of the S parameter integrating module 2 for outputting a downlink differential clock negative signal The third resistor R3 and the first capacitor C1 form a clock balancing circuit, and the clock balancing circuit is used for balancing the downlink differential clock signals; one ends of the fourth resistor R4, the fifth resistor R5 and the second capacitor C2 are connected with each other, the other end of the second capacitor C2 is grounded, the other end of the fourth resistor R4 is connected with one end, used for outputting the downlink differential data positive signal, of the S parameter integration module 2, the other end of the fifth resistor R5 is connected with one end, used for outputting the downlink differential data negative signal, of the S parameter integration module 2, and a data balance circuit is formed by the fourth resistor R4, the fifth resistor R5 and the second capacitor C2 and used for balancing the downlink differential data signal. The value of the communication line balancing circuit is obtained from experience and is relatively fixed.
The chip end circuit 4 adopts a general simulation, a chip model needs to be introduced here, and a chip is generally an unoptimizable factor, so that the chip port circuit 4 simplifies each chip on the PCB into a path of matching impedance with a corresponding resistance value in this embodiment. Further, each of the chips is simplified into a path of normalized matching impedance with 50 ohms, for example, in fig. 1, the sixth resistor R6 to the eleventh resistor R11 are all resistors with 50 ohms.
One end of each pulse source and one end of each analog resistor in the main analog frequency signal source 1 are grounded, the other end of each pulse source and the other end of each analog resistor are respectively connected with the corresponding input end of the S parameter integration module 2, and the corresponding output end of the S parameter integration module 2 is connected with the communication balance circuit 3 or the chip port circuit 4. The input end and the output end are ports at two ends of a signal line, and the number, type and position of the signal line may be adjusted according to a signal in the main analog frequency signal source 1, for example, referring to fig. 1, the signal line may include SDO, FCLN, FCLP, SIN, SIP and CSN.
For example, the first pulse source S1 and the analog resistor R1 in the main analog frequency signal source 1 are connected to one end of the S parameter integration module 2 through an SDO input terminal and a CSN input terminal, respectively, the other end of the S parameter integration module 2 is directly connected to the sixth resistor R6 and the eleventh resistor R11 of the chip port 4 through an SDO output terminal and a CSN output terminal, respectively, and the other ends of the sixth resistor R6 and the eleventh resistor R11 are directly grounded, that is, the analog uplink frequency signal simulated by the first pulse source S1 and the analog resistor R1 do not need to be balanced by the communication line balancing circuit 3; the downlink differential clock negative signal and the downlink differential clock positive signal simulated by the second pulse source S2 and the third pulse source S3 in the main analog frequency signal source 1 are respectively connected to the S parameter integration module 2 through an FCLN input end and an FCLP input end, and the S parameter integration module 2 is respectively connected to the communication line balancing circuit 3 through an FCLN output end and an FCLP output end, specifically, the FCLN output end is connected to one end of the third resistor R3 in the communication line balancing circuit 3, the FCLP output end is connected to one end of the second resistor R2 in the communication line balancing circuit 3, then the other end of the second resistor R2 and the other end of the third resistor R3 are merged and then connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded, that is, the downlink differential clock signals simulated by the second pulse source S2 and the third pulse source S3 pass through the second resistor R2, the communication line balancing circuit 3, The third resistor R3 and the first capacitor C1 are balanced, so that the signal-to-noise ratio and the EMC performance of the corresponding differential signal line are improved; the downstream differential data negative signal and the downstream differential data positive signal simulated by the fourth pulse source S4 and the fifth pulse source S5 in the primary analog frequency signal source 1 are respectively connected to the S parameter integration module 2 through an SIN input terminal and an SIP input terminal, the S parameter integration module 2 is connected to the communication line balancing circuit 3 through an SIN output terminal and an SIP output terminal, specifically, the SIN output terminal is connected to a fifth resistor R5 in the communication line balancing circuit 3, the SIP output terminal is connected to one end of a fourth resistor R4 in the communication line balancing circuit 3, then the other end of the fourth resistor R4 and the other end of the fifth resistor R5 are merged and then connected to one end of a second capacitor C2, and the other end of the second capacitor C2 is grounded, that is, the downstream differential clock signals simulated by the fourth pulse source S4 and the fifth pulse source S5 pass through the fourth resistor R4, the SIP input terminal, and the SIP input terminal of the communication line balancing circuit 3, The fifth resistor R5 and the second capacitor C2 are balanced, and the signal-to-noise ratio and the EMC performance of the corresponding differential signal line are improved.
In the above embodiment, each output terminal of the S parameter integration module 2 is also connected to the chip port 4, for example, the output terminal FCLN of the S parameter integration module 2 for outputting the negative signal of the downstream differential clock is connected to the seventh resistor R7 in the chip port 4; an output end FCLP of the S-parameter integration module 2, which is used for outputting a positive signal of a downlink differential clock, is connected to an eighth resistor R8 in the chip port 4; an output end SIN of the S parameter integration module 2 for outputting a downlink differential data negative signal is connected to a ninth resistor R9 in the chip port 4; the output end SIP of the S parameter integration module 2 for outputting the positive signal of the downlink differential clock is connected to the tenth resistor R10 in the chip port 4.
In order to further improve the electromagnetic compatibility of the PCB simulation circuit, the PCB simulation circuit may further include a differential mode filter circuit to remove differential mode interference that may exist in practical applications. The differential mode filter circuit can be adjusted according to the frequency signal provided by the main analog frequency signal source 1 and is connected with the corresponding output end in the S parameter integration module 2. For example, referring to fig. 2, when the main analog frequency signal source 1 includes a downlink differential clock negative signal, a downlink differential clock positive signal, a downlink differential data negative signal, and a downlink differential data positive signal, the differential mode filter circuit includes two differential mode filter capacitors, that is, a first differential mode filter capacitor C3 and a second differential mode filter capacitor C4, and two ends of the first differential mode filter capacitor C3 are connected to one end of the S parameter integration module 2 for outputting the downlink differential clock negative signal and one end for outputting the downlink differential clock positive signal; two ends of the second differential-mode filter capacitor C4 are connected to one end of the S parameter integration module 2 for outputting a negative signal of downlink differential data and one end of the S parameter integration module for outputting a positive signal of downlink differential data. For example, in fig. 2, two ends of the first differential-mode filter capacitor C3 are connected to the FCLN output terminal of the S parameter integration module 2 for outputting a negative signal of the downstream differential clock and the FCLP output terminal for outputting a positive signal of the downstream differential clock; two ends of the second differential-mode filter capacitor C4 are connected to the SIN output end of the S parameter integration module 2 for outputting a negative downlink differential data signal and the SIP output end for outputting a positive downlink differential data signal.
Referring to fig. 3, a common mode filter circuit may be further included in the PCB simulation circuit to optimize the possible presence of common mode noise in practical applications. The common mode filter circuit may be adjusted according to a frequency signal provided in the main analog frequency signal source 1, and is connected to a corresponding output terminal in the S parameter integration module 2, for example, when the main analog frequency signal source 1 includes a downlink differential clock negative signal, a downlink differential clock positive signal, a downlink differential data negative signal, and a downlink differential data positive signal, the common mode filter circuit includes four common mode filter capacitors, and one end of each of the four common mode filter capacitors is connected to one end of the S parameter integration module 2 for outputting the downlink differential clock positive signal, one end of the S parameter integration module for outputting the downlink differential clock negative signal, one end of the S parameter integration module for outputting the downlink differential data positive signal, and one end of the S parameter integration module for outputting the downlink differential data negative signal. Specifically, the four common-mode filter capacitors are a first common-mode filter capacitor C5, a second common-mode filter capacitor C6, a third common-mode filter capacitor C7 and a fourth common-mode filter capacitor C8, one end of each of the first common-mode filter capacitor C5, the second common-mode filter capacitor C6, the third common-mode filter capacitor C7 and the fourth common-mode filter capacitor C8 is connected to the FCLP output terminal, the FCLN output terminal, the SIP output terminal and the SIN output terminal of the S parameter integration module 2, and the other end of each of the first common-mode filter capacitor C5, the second common-mode filter capacitor C6, the third common-mode filter capacitor C7 and the fourth common-mode filter capacitor C8 is grounded.
In addition, a differential mode filter circuit and a common mode filter circuit can be added in the PCB simulation circuit at the same time, the differential mode filter circuit and the common mode filter circuit are respectively connected with the corresponding output ends of the S parameter integration module 2, and the differential mode filter circuit and the common mode filter circuit can be adjusted according to the frequency signals in the main analog frequency signal source 1. For example, referring to fig. 4, the common-mode filter circuit includes four common-mode filter capacitors, the four common-mode filter capacitors are a first common-mode filter capacitor C5, a second common-mode filter capacitor C6, a third common-mode filter capacitor C7 and a fourth common-mode filter capacitor C8, one end of each of the first common-mode filter capacitor C5, the second common-mode filter capacitor C6, the third common-mode filter capacitor C7 and the fourth common-mode filter capacitor C8 is connected to the FCLP output terminal, the FCLN output terminal, the SIP output terminal and the SIN output terminal of the S parameter integration module 2, and the other end of each of the first common-mode filter capacitor C5, the second common-mode filter capacitor C6, the third common-mode filter capacitor C7 and the fourth common-mode filter capacitor C8 is grounded; the differential mode filter circuit comprises two differential mode filter capacitors, namely a first differential mode filter capacitor C3 and a second differential mode filter capacitor C4, and two ends of the first differential mode filter capacitor C3 are connected with an FCLN output end of the S parameter integration module 2 for outputting a negative signal of a downlink differential clock and an FCLP output end for outputting a positive signal of the downlink differential clock; two ends of the second differential-mode filter capacitor C4 are connected to the SIN output end of the S parameter integration module 2 for outputting a negative downlink differential data signal and the SIP output end for outputting a positive downlink differential data signal.
The invention can establish a plurality of optimized PCB simulation circuit models, so that a large amount of harmonic components can be successfully filtered out by the optimized circuit, the electromagnetic compatibility of a PCB communication signal circuit, especially a PCB microsecond communication signal circuit, is improved, and the aim of solving the electromagnetic compatibility problem is fulfilled.
The invention also provides a PCB simulation circuit analysis method, which is a PCB microsecond communication circuit based on practical items, finds the problem of the circuit, analyzes the electromagnetic compatibility of the circuit through simulation, and finally confirms the circuit design scheme for improving the electromagnetic compatibility of PCB communication signals, especially the microsecond communication signals of the PCB through experiments.
The PCB simulation circuit analysis method comprises the following steps:
the method comprises the following steps: carrying out simulation modeling on a signal source, communication signal wiring, a communication line balance circuit and a chip of the PCB to obtain a PCB simulation circuit, wherein the step of carrying out simulation modeling on the signal source of the PCB comprises the following steps: providing a plurality of signals including a clock signal and a data signal according to a real signal of the PCB; the step of carrying out simulation modeling on the communication signal routing of the PCB comprises the following steps: gathering S parameters corresponding to communication signal routing of the PCB, wherein the S parameters are scattering parameters; the step of performing simulation modeling on the communication line balance circuit of the PCB comprises the following steps: balancing the clock signal and the data signal respectively;
step two: and operating the PCB simulation circuit to obtain a simulation result.
In the first step, a signal source, a communication signal trace, a communication line balancing circuit and a chip of the PCB are simulated and modeled to obtain the PCB simulation circuit, and a specific structure of the PCB simulation circuit may be as shown in any one of fig. 1 to 4.
In the process of building the PCB simulation circuit, S parameter analysis needs to be performed on the routing of the PCB firstly, the S parameter analysis can be obtained through testing or simulation, S parameters are obtained through simulation based on simulation software in the embodiment, the analyzed S parameters are led into an S parameter integration module through software, namely the S parameter integration module integrates the S parameters corresponding to the communication signal routing of the PCB, and therefore the S parameters can be used for replacing a real circuit to perform electromagnetic compatibility analysis on the communication signal of the PCB.
The process of the S parameter integrated module for collecting the S parameter of the PCB communication signal routing mainly comprises the following steps: and analyzing and importing the S parameter. Wherein the analysis of the S parameter comprises: firstly, carrying out lamination setting according to the actual condition of a PCB; then, adding ports at two ends of the signal lines (such as SDO, FCLN, FCLP, SIN, SIP and CSN) to be analyzed; and finally, setting a solving frequency (covering 1 MHz-100 MHz) according to the signal frequency, and operating software to solve an S parameter, wherein the S parameter is output as a file of S12P. The importing of the S parameter comprises: firstly, adding a blank multi-port S parameter integrated module in the PCB simulation circuit; then, the S parameter integration module and the output S12P file are linked to realize the import of the S parameter. The S parameters can conveniently and accurately replace real PCB wiring, and can truly reflect the mutual influence among the wirings. Therefore, the S parameter is used for replacing a complicated PCB, so that the method is a convenient, quick, accurate and efficient scheme, and is a very key step in the analysis method.
And (4) continuing to build the simulation circuit after the steps are completed, wherein the simulation circuit is built by taking the S parameter as a core. That is, after the S parameter integrated module 2 collects the S parameters corresponding to the traces of the PCB, each port of the S integrated module is connected to a corresponding circuit device (such as a pulse source and a load) respectively to complete the simulation circuit using the S parameters instead of the real circuit, and the electromagnetic compatibility analysis of the PCB communication signals, especially the microsecond communication signals of the PCB, can be performed based on the circuit.
In the second step, the PCB board simulation circuit is operated, and the simulation result is obtained as shown in fig. 5, and comparing with the actual test result shown in fig. 6, it can be seen that an obvious signal appears every 33.3MHz, and the signals are stronger at 166.6MHz, 200MHz and 233.3MHz, that is, the simulation analysis well reproduces the experimental test result. The result obtained by the simulation analysis is highly consistent with the result of the experimental test, which shows that the simulation model is more accurate, and the simulation analysis method is more scientific and has higher reliability.
Before or after the second step, a differential mode filter circuit and/or a common mode filter circuit can be added to the PCB board simulation circuit, and the PCB board simulation circuit added with the differential mode filter circuit and/or the common mode filter circuit is operated to obtain a simulation result. The method comprises the following specific steps:
when the PCB board simulation circuit includes the differential mode filter circuit, the obtained simulation result is as shown in fig. 7, it can be found that signals appearing every 33.3MHz are reduced, that is, in practical application, the differential mode interference can be reduced by adding the differential mode filter circuit, and further the electromagnetic compatibility performance is improved;
when the PCB simulation circuit comprises the common mode filter circuit, the obtained simulation result is shown in FIG. 8, and it can be found that signals appearing every 33.3MHz are obviously reduced, and after the frequency is higher than 150MHz, almost no obvious single branch signal exists, which shows that the differential mode filter circuit plays a good role;
when the common mode filter circuit and the differential mode filter circuit are added to the PCB simulation circuit at the same time, the obtained simulation result is shown in FIG. 9, and the result is better than that of the differential mode filter circuit added alone, but is worse than that of the common mode filter circuit added alone. According to general mathematical experience, if the differential mode filter circuit and the common mode filter circuit are added to the circuit at the same time, so that the optimization scheme is maximized, the best optimization result is obtained. However, the results obtained after the operation of the simulation circuit of the PCB are not the same, and the two reasons are mainly: on one hand, the electromagnetic field is a vector field, and simple addition and subtraction operations cannot be performed according to a mathematical scalar; on the other hand, the addition of a circuit may cause the original circuit to resonate, which also makes it difficult to achieve the desired effect. Certainly, the risk points are difficult to predict in advance without simulation analysis, so that the advantages of the forward design analysis method are embodied, the importance and the advantages of simulation analysis performed by software are also embodied, and experience can be verified, supplemented and corrected. Under the condition of fully considering the optimization result, in the development of the next generation controller, a design scheme of increasing the common mode filter capacitance is preferably selected.
According to the invention, a plurality of optimized PCB simulation circuits are established, and simulation can find that a large amount of harmonic components are successfully filtered out from the optimized circuit, so that the electromagnetic compatibility of the circuit is remarkably improved.
Therefore, the core idea of the invention is to establish a PCB simulation circuit, and the electromagnetic compatibility of the PCB simulation circuit is obviously improved through the optimized design and operation of the PCB simulation circuit, so that the problem of the electromagnetic compatibility of the product can be solved. The method can be used for designing the differential communication signal circuit of the same type, and has the advantages of simple structure, low cost, high reliability, low cost, and good application prospect.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A PCB board emulation circuit, comprising:
a main analog frequency signal source for providing a plurality of signals including a clock signal and a data signal according to a real signal of the PCB board;
the S parameter integration module is connected with the main analog frequency signal source and used for integrating S parameters corresponding to communication signal routing of the PCB, and the S parameters are scattering parameters;
the communication line balancing circuit is connected with the S parameter integrated module and is used for balancing the clock signal and the data signal output by the S parameter integrated module respectively;
and the chip port circuit is used for carrying out simulation modeling on the chip in the PCB.
2. The PCB board simulation circuit of claim 1, wherein the main analog frequency signal source comprises a plurality of pulse sources for providing corresponding frequency signals and at least one analog resistor, and one end of each of the pulse sources and the analog resistor is grounded, and the other end of each of the pulse sources and the analog resistor is connected to a corresponding input terminal of the S-parameter integration module.
3. The PCB board emulation circuit of claim 2, wherein the plurality of signals comprises an upstream frequency signal, a downstream differential clock signal, and a downstream differential data signal, wherein the downstream differential clock signal comprises a downstream differential clock negative signal and a downstream differential clock positive signal, and wherein the downstream differential data signal comprises a downstream differential data negative signal and a downstream differential data positive signal.
4. The PCB board emulation circuit of claim 3, wherein the communication line balancing circuit comprises a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, and a second capacitor; one end of a second resistor, one end of a third resistor and one end of a first capacitor are connected with each other, the other end of the first capacitor is grounded, the other end of the second resistor is connected with one end of the S parameter integration module, which is used for outputting a positive signal of a downlink differential clock, the other end of the third resistor is connected with one end of the S parameter integration module, which is used for outputting a negative signal of the downlink differential clock, and the second resistor, the third resistor and the first capacitor form a clock balancing circuit, which is used for balancing the downlink differential clock signal; one ends of the fourth resistor, the fifth resistor and the second capacitor are connected with each other, the other end of the second capacitor is grounded, the other end of the fourth resistor is connected with one end of the S parameter integration module, which is used for outputting the downlink differential data positive signal, the other end of the fifth resistor is connected with one end of the S parameter integration module, which is used for outputting the downlink differential data negative signal, and the fourth resistor, the fifth resistor and the second capacitor form a data balance circuit, which is used for balancing the downlink differential data signal.
5. The PCB board simulation circuit of claim 3, further comprising a differential mode filter circuit, wherein the differential mode filter circuit comprises a first differential mode filter capacitor and a second differential mode filter capacitor, and two ends of the first differential mode filter capacitor are respectively connected with one end of the S parameter integration module for outputting a negative signal of the downstream differential clock and one end of the S parameter integration module for outputting a positive signal of the downstream differential clock; and two ends of the second differential-mode filter capacitor are respectively connected with one end of the S parameter integration module for outputting the downlink differential data negative signal and one end of the S parameter integration module for outputting the downlink differential data positive signal.
6. The PCB simulation circuit of claim 3 or 5, further comprising a common mode filter circuit, wherein the common mode filter circuit comprises four common mode filter capacitors, one end of each of the four common mode filter capacitors is respectively connected with one end of the S parameter integrated module for outputting a positive signal of the downlink differential clock, one end of the S parameter integrated module for outputting a negative signal of the downlink differential clock, one end of the S parameter integrated module for outputting a positive signal of the downlink differential data, and one end of the S parameter integrated module for outputting a negative signal of the downlink differential data, and the other ends of the four common mode filter capacitors are all grounded.
7. The PCB board simulation circuit of claim 1, wherein S-parameters extracted by using each input pin and each output pin of each chip as a port are integrated in the S-parameter integration module, and the S-parameters are obtained by testing or simulation.
8. The PCB emulation circuit of claim 1, wherein the chip port circuit reduces each of the chips on the PCB to a path of matching impedance having a corresponding resistance.
9. A PCB board simulation circuit analysis method is characterized by comprising the following steps:
the method comprises the following steps: carrying out simulation modeling on a signal source, communication signal wiring, a communication line balance circuit and a chip of the PCB to obtain a PCB simulation circuit, wherein the step of carrying out simulation modeling on the signal source of the PCB comprises the following steps: providing a plurality of signals including a clock signal and a data signal according to a real signal of the PCB; the step of carrying out simulation modeling on the communication signal routing of the PCB comprises the following steps: gathering S parameters corresponding to communication signal routing of the PCB, wherein the S parameters are scattering parameters; the step of performing simulation modeling on the communication line balance circuit of the PCB comprises the following steps: balancing the clock signal and the data signal respectively;
step two: and operating the PCB simulation circuit to obtain a simulation result.
10. The method for analyzing PCB board simulation circuit according to claim 9, wherein before or after the second step, a differential mode filter circuit and/or a common mode filter circuit is added to the PCB board simulation circuit, and the PCB board simulation circuit added with the differential mode filter circuit and/or the common mode filter circuit is operated to obtain the simulation result.
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