CN113535631A - Data distribution method and device, integrated chip and video image processing system - Google Patents
Data distribution method and device, integrated chip and video image processing system Download PDFInfo
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Abstract
The invention discloses a data distribution method, a data distribution device, an integrated chip and a video image processing system. The method comprises the following steps: determining a working frequency adjustment strategy of the video image processing system according to a pixel clock frequency of the video image processing system and a maximum working frequency threshold value of data processing; adjusting the working parameters of the video image processing system according to the working frequency adjusting strategy; and distributing the data to be processed to at least one data stream according to the working parameters. By the technical scheme, the working frequency of the integrated chip is reduced, and the running stability of the video image processing system is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of data communication, in particular to a data distribution method, a data distribution device, an integrated chip and a video image processing system.
Background
Video image processing systems are increasingly used in numerous fields such as device inspection/detection, security monitoring, industrial vision, and artificial intelligence. With the increasing of the resolution of the video image processing system, the number of channels (Lane) used on the terminal device for video display increases, and the Link Rate (LR) also increases, which makes higher and higher requirements on the stability, coordination, and the like of the hardware platform of the video image processing system.
Under the scene of greatly increased data processing capacity, the working frequency inside a chip for bearing data is higher due to over-concentrated data, so that the data processing performance of the chip is influenced, and the running stability of a video image processing system is reduced.
Disclosure of Invention
The invention provides a data distribution method, a data distribution device, an integrated chip and a video image processing system.
In a first aspect, an embodiment of the present invention provides a data distribution method, including:
determining a working frequency adjustment strategy of the video image processing system according to a pixel clock frequency of the video image processing system and a maximum working frequency threshold value of data processing;
adjusting the working parameters of the video image processing system according to the working frequency adjusting strategy;
and distributing the data to be processed to at least one data stream according to the working parameters.
Further, before determining the operating frequency adjustment policy of the video image processing system according to the pixel clock frequency of the video image processing system and the maximum operating frequency threshold of data processing, the method further includes:
and calculating the pixel clock frequency of the video image processing system according to a panel time sequence parameter, a Frame Rate (FR) parameter and the number of input pixels of each clock supported by the video image processing system.
Further, determining an operating frequency adjustment policy of the video image processing system according to a pixel clock frequency of the video image processing system and a maximum operating frequency threshold of data processing, includes:
comparing the pixel clock frequency to the maximum operating frequency threshold;
if the pixel clock frequency is greater than the maximum working frequency threshold, selecting a corresponding working frequency adjustment strategy according to a preset strategy threshold so as to enable the pixel clock frequency to be less than or equal to the maximum working frequency threshold;
the preset strategy threshold value is at least one, and the working frequency adjusting strategy is at least one.
Further, the method also comprises the following steps:
if the pixel clock frequency corresponding to the adjusted working parameter is greater than the maximum working frequency threshold, re-determining a working frequency adjustment strategy and adjusting the working parameter of the video image processing system according to the working frequency adjustment strategy until the pixel clock frequency corresponding to the working parameter is less than or equal to the maximum working frequency threshold, so as to obtain the adjusted working parameter.
Further, the operating frequency adjustment strategy includes at least one of:
adjusting the number of input pixels of each clock;
adjusting the pixel number processed by each clock of the data bearing chip;
adjusting the caching quantity of the data stream;
adjusting the number of channels supported by the video image processing system;
the operating parameter default or current values are used.
Further, the method also comprises the following steps: generating a data allocation instruction, wherein the data allocation instruction comprises:
a maximum operating frequency threshold indication field for indicating a maximum operating frequency threshold for data processing;
a channel number indication field for indicating the number of channels supported by the video image processing system;
a frame rate indication field for indicating an actual frame rate of the panel;
and the data stream buffering quantity indication field is used for indicating the buffering and output format of the data.
Further, the data allocation instructions further include:
and the master-slave module definition field is used for indicating the signaling interaction relation between the integrated chip and the modules of the video image processing system in the data distribution process.
In a second aspect, an embodiment of the present invention provides a data distribution apparatus, including:
the decision module is used for determining a working frequency adjusting strategy of the video image processing system according to the pixel clock frequency of the video image processing system and the maximum working frequency threshold value of data processing;
the adjusting module is used for adjusting the working parameters of the video image processing system according to the working frequency adjusting strategy;
and the distribution module is used for distributing the effective data to be processed to the data flow according to the working parameters.
In a third aspect, an embodiment of the present invention provides an integrated chip, including:
one or more processors;
storage means for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement the data distribution method of the first aspect.
In a fourth aspect, an embodiment of the present invention further provides a video image processing system, including: an embedded control module, an external module and an integrated chip according to claim 9, the integrated chip being connected to the embedded control module and the external module, respectively;
the embedded control module is used for initiating a data distribution request to the integrated chip;
the external module is used for storing video data to be processed and providing a physical layer interface for displaying the video image data.
The embodiment of the invention provides a data distribution method, a data distribution device, an integrated chip and a video image processing system. The method comprises the following steps: determining a working frequency adjustment strategy of the video image processing system according to a pixel clock frequency of the video image processing system and a maximum working frequency threshold value of data processing; adjusting the working parameters of the video image processing system according to the working frequency adjusting strategy; and distributing the data to be processed to at least one data stream according to the working parameters. By the technical scheme, the working frequency of the integrated chip is reduced, and the running stability of the video image processing system is improved.
Drawings
Fig. 1 is a flowchart of a data distribution method according to an embodiment of the present invention;
fig. 2 is a flowchart of a data distribution method according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a data distribution apparatus according to a third embodiment of the present invention;
fig. 4 is a schematic diagram of a hardware structure of an integrated chip according to a fourth embodiment of the present invention;
fig. 5 is a schematic structural diagram of a video image processing system according to a fifth embodiment of the present invention;
fig. 6 is a schematic diagram illustrating an implementation of a video image processing system according to a fifth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a flowchart of a data distribution method according to an embodiment of the present invention, which is applicable to a situation of splitting data to be processed in a Video image processing system, and in particular, to a Video image processing system based on a Field Programmable Gate Array (FPGA) and an embedded system, and in particular, to a Video image processing system with a Video Electronics Standards Association (VESA) digital Video Interface standard (DisplayPort, DP), a Mobile Industry Processor Interface standard (MIPI), and a High Definition Multimedia Interface standard (HDMI).
The data distribution method of the present embodiment may be executed by a data distribution apparatus, which may be implemented by software and/or hardware and integrated in an integrated chip. In this embodiment, the data to be processed includes video image data, the video image data is a sequence of continuous still images, and the video image processing system is a system for processing video images based on an image processing algorithm. The integrated chip includes, but is not limited to, an FPGA, a Micro Controller Unit (MCU), a Digital Signal Processor (DSP), and the like.
As shown in fig. 1, the method specifically includes the following steps:
s110, determining an operating frequency adjusting strategy of the video image processing system according to the pixel clock frequency of the video image processing system and the maximum operating frequency threshold of data processing.
Specifically, the pixel clock frequency refers to the frequency of a pixel clock signal, and is related to the working parameters of a display panel in the video image processing system, the higher the resolution of the display panel is, the higher the frequency of the pixel clock signal is, and the pixel clock signal can direct the RGB color signals to be sequentially transmitted to the display panel, and ensure the correctness of data transmission. If the pixel clock frequency in the system is higher than the maximum operating frequency threshold of the chip in the video image processing system, the data processing performance of the chip is reduced, and the stability of the system operation is reduced. In this embodiment, by calculating the pixel clock frequency and using the maximum working frequency threshold of the chip for data processing as the reference for working frequency optimization, the working parameters in the system are adjusted according to a certain strategy, so that the actually working pixel clock frequency is lower than the maximum working frequency threshold, and the pixel clock frequency is kept in a lower range, so as to improve the stability of system operation.
And S120, adjusting the working parameters of the video image processing system according to the working frequency adjusting strategy.
Specifically, the operating parameters may include the number of pixels input per clock of the video image processing system, the number of pixels processed per clock inside the chip, the number of buffered data streams, the number of channels, and the like, and the operating frequency adjustment policy may include increasing or decreasing one or more of the operating parameters, so as to adjust the total number of pixels, the pixel clock frequency, the frame rate, and the like in the system, so as to decrease the actual pixel clock frequency.
And S130, distributing the data to be processed to at least one data stream according to the working parameters.
Specifically, on the premise that the actual pixel clock frequency is reduced to be below the maximum working frequency threshold, the data to be processed is shunted, including the modes of cutting the number of parallel input data streams, cutting the number of parallel output data streams, caching the data streams and the like, so that the data processing pressure of the chip is reduced, the performance of the chip is more stable, and the data processing is more reliable.
According to the data distribution method provided by the embodiment of the invention, the pixel clock frequency is calculated, the corresponding maximum working frequency threshold is set, and the corresponding working frequency adjustment strategy is selected according to the pixel clock frequency to adjust the working parameters, so that the actual working frequency is kept within the maximum working frequency threshold, and on the basis, the data to be processed is shunted, the internal actual working frequency of a chip is obviously reduced, and the stability and the reliability of the system for processing the data are improved.
Example two
Fig. 2 is a flowchart of a data distribution method according to a second embodiment of the present invention, where the second embodiment is optimized based on the foregoing embodiments, and specifically describes an adjustment process of an operating frequency adjustment strategy and an operating parameter. It should be noted that technical details that are not described in detail in the present embodiment may be referred to any of the above embodiments.
Specifically, as shown in fig. 2, the method specifically includes the following steps:
s210, calculating the pixel clock frequency of the video image processing system according to the panel time sequence parameter, the frame rate parameter and the input pixel number of each clock supported by the video image processing system.
Specifically, the pixel clock frequency is calculated according to a panel timing parameter, a frame rate parameter and an input pixel number of each clock supported by the video image processing system. For example, panel timing parameters include:
row Front (HFP): 48;
line Start (HS): 32, a first step of removing the first layer;
trailing edge (HBP): 80;
line blanking (Horizontal Blank, HB): HFP + HS + HBP 48+32+80 160;
number of pixels available for line (XDOT): 3840;
total number of rows (Horizontal Total, HT): HB + XDOT 3840+160 4000;
field Front edge (Vertical Front Porch, HFP): 3;
field Start (HS): 5;
field Back Porch (HBP): 54, a first electrode;
vertical blanking (HB): VFP + VS + VBP + 3+5+ 54-62;
pixel number available for field (Vertical Active, YDOT): 2160;
total number of fields (Vertical Total, VT): VB + YDOT 2160+62 2222;
according to the panel time sequence parameters, the calculation mode of the pixel clock frequency is as follows:
pixel clock frequency (line total HT field total VT frame rate/pixel number of each clock input); the pixel clock frequency is also related to the frame rate and the number of pixels per clock input.
Table 1 is a mapping table of pixel clock frequency, frame rate, and number of input pixels. As shown in table 1, when the panel timing parameters are determined, the pixel clock frequency is positively correlated with the frame rate and negatively correlated with the number of pixels per clock.
TABLE 1 mapping relationship table of pixel clock frequency, frame rate and input pixel number
S220, is the pixel clock frequency greater than the maximum operating frequency threshold? If yes, go to S230, otherwise go to S270.
Specifically, the calculated pixel clock frequency is compared with a maximum working frequency threshold, and if the pixel clock frequency is greater than the maximum working frequency threshold, a corresponding working frequency adjustment strategy needs to be selected to adjust the working parameters; if the pixel clock frequency is not greater than the maximum working frequency threshold, the working parameters are not adjusted, the stability requirement of the chip can be met by adopting the current working parameters, and the data to be processed can be directly shunted according to the current working parameters.
S230, selecting a corresponding working frequency adjusting strategy according to a preset strategy threshold value so that the pixel clock frequency is smaller than or equal to the maximum working frequency threshold value.
Specifically, under the condition that the pixel clock frequency is greater than the maximum working frequency threshold, the corresponding working frequency adjustment policy may be selected according to the preset policy threshold, and the preset policy threshold is determined according to the maximum working frequency threshold, and may be used to measure the value of the frequency value at which the pixel clock frequency exceeds the maximum working frequency threshold, or to measure the value of the pixel clock frequency. In this embodiment, at least one preset policy threshold is set, and at least one operating frequency adjustment policy is set.
In one embodiment, the operating frequency adjustment strategy includes at least one of: adjusting the number of input pixels of each clock; adjusting the number of pixels processed by each clock of a data bearing chip (IP Core); adjusting the caching quantity of the data stream; adjusting the number of channels supported by the video image processing system; the operating parameter default or current values are used.
Table 2 is a mapping relationship table between the preset policy threshold and the operating frequency adjustment policy. As shown in table 2, for example, different operating frequency adjustment strategies may be determined according to the magnitude of the frequency value of the pixel clock frequency exceeding the maximum operating frequency threshold, and when the frequency value exceeding the maximum operating frequency threshold is greater than the preset strategy threshold 1, the operating frequency adjustment strategy 1 may be adopted; when the frequency value exceeding the maximum operating frequency threshold is smaller than the preset policy threshold 1 but larger than the preset policy threshold 2, the operating frequency adjustment policy 2, etc. may be employed.
Table 2 mapping relationship table of preset policy threshold and operating frequency adjustment policy
S240, adjusting the working parameters of the video image processing system according to the working frequency adjusting strategy.
For example, if the operating frequency adjustment strategy 1 is selected, the number of input pixels per clock is adjusted; and if the working frequency adjusting strategy 3 is selected, adjusting the data stream buffer amount and the like. It should be noted that a combination strategy of the above strategies may also be selected, for example, the number of input pixels per clock and the number of data stream buffers may be adjusted at the same time.
S250, is the pixel clock frequency corresponding to the operating parameter less than or equal to the maximum operating frequency threshold? If yes, go to step S260, otherwise, go back to step S230.
In this embodiment, if the pixel clock frequency corresponding to the adjusted operating parameter is greater than the maximum operating frequency threshold, the operating frequency adjustment policy is determined again and the operating parameter of the video image processing system is adjusted according to the operating frequency adjustment policy until the pixel clock frequency corresponding to the operating parameter is less than or equal to the maximum operating frequency threshold, so as to obtain the adjusted operating parameter.
In an embodiment, when the pixel clock frequency is greater than the maximum operating frequency threshold, different strategies may be successively adopted until the pixel clock frequency is reduced to below the maximum operating frequency threshold. For example, the maximum operating frequency threshold of the data-carrying chip (the chip for processing video image data in the integrated chip) is 135MHz, according to table 1, when the frame rate is 60Hz and the input pixel count/clock is 1, the pixel clock frequency is 533.28Hz, which is greater than the maximum operating frequency threshold, in this case, strategy 1 may be adopted first, and the input pixel count in each clock is adjusted to 2, so that a new pixel clock frequency is 266.64 MHz; the pixel clock frequency is still greater than the maximum working frequency threshold, at this time, policy 2 and policy 3 may be adopted, and in a general case, when the policy 2 is adopted to adjust the number of pixels/clock processed inside the chip, the cached data stream may be adjusted along with the policy 3 to obtain a new pixel clock frequency of 133.32MHz, and if the new pixel clock frequency is less than the maximum working frequency threshold, the finally determined working frequency adjustment policy is policy 1+ policy 2+ policy 3. Similarly, if the pixel clock frequency obtained according to strategy 1+ strategy 2+ strategy 3 is still greater than the maximum operating frequency threshold, the operating parameters may continue to be adjusted according to strategy 4 and/or strategy 5.
Table 3 is a mapping table of the pixel clock frequency and the operating frequency adjustment strategy. As shown in table 3, the preset policy threshold may be used to measure the pixel clock frequency, for example, when the frame rate is 30 and the number of input pixels in each clock is 1, the pixel clock frequency is 266.64Hz, and the corresponding operating frequency adjustment policy includes policy 1, policy 2, and policy 3, and needs to be executed in several times, where policy 1 is executed first, and then policy 2 and policy 3 are executed; when the frame rate is 30 and the number of input pixels per clock is 2, the pixel clock frequency is 133.32Hz, and the shunting may be performed directly according to policy 5.
TABLE 3 mapping relationship table of pixel clock frequency and working frequency adjustment strategy
And S260, distributing the data to be processed to at least one data stream according to the adjusted working parameters. Specifically, the integrated chip finally determines the operating parameters of the system, such as the number of input pixels in each clock, the pixel clock frequency, and the like, according to the finally determined operating frequency adjustment strategy, and accordingly shunts the data to be processed, so that the actual operating frequency of the chip is reduced.
And S270, distributing the data to be processed to at least one data stream according to the current working parameters.
Specifically, under the condition that the pixel clock frequency is less than the maximum working frequency threshold, the integrated chip does not need to adjust working parameters, and can shunt data to be processed according to the current working parameters, such as the number of input pixels in each clock, the pixel clock frequency and the like, so that the actual working frequency of the chip is reduced.
In one embodiment, the method further comprises: generating a data allocation instruction, wherein the data allocation instruction comprises: a maximum operating frequency threshold indication field for indicating a maximum operating frequency threshold for data processing; a channel number indication field for indicating the number of channels supported by the video image processing system; a frame rate indication field for indicating an actual frame rate of the panel; and the data stream buffering quantity indication field is used for indicating the buffering and output format of the data.
Specifically, the integrated chip defines the maximum working frequency threshold and working parameters in various systems by generating a data distribution instruction according to a preset format, provides a basis for calculating the pixel clock frequency, selecting a working frequency adjustment strategy and adjusting the working parameters, and performs signaling interaction between modules in the video image processing system according to the format, so that the transmission efficiency of data streams is improved, and the stability of data stream transmission is ensured.
In one embodiment, the data allocation instructions further comprise: and the master-slave module definition field is used for indicating the signaling interaction relation between the integrated chip and the modules of the video image processing system in the data distribution process.
Specifically, the master-slave module definition field defines that the modules of the video image processing system include a master module and a slave module, the master module and the slave module are defined according to the initiator and the receiver of the command, and the master-slave relationship between the modules corresponding to different signaling interaction processes may be different. For example, the embedded control module may serve as a master module to initiate data distribution signaling to an integrated chip (e.g., FPGA) to receive signaling and execute the signaling as a slave module; the integrated chip may also serve as a master module that initiates signaling to the embedded control module, which is a slave module at this time. For another example, data distribution signaling of the integrated chip is forwarded to the slave module by the master module among the modules in the integrated chip, the slave module completes data distribution and feeds back to the master module, the master module feeds back to the embedded control module, and the like. The data allocation instruction may further include a feedback field for defining a module state after the data allocation signaling interaction is completed, where the module state includes an ACK state and a NACK state, and completes a confirmation operation of the signaling interaction.
In the data distribution method provided by the second embodiment of the present invention, optimization is performed on the basis of the above embodiment, and when the pixel clock frequency is greater than the maximum working frequency threshold, a corresponding working frequency adjustment strategy can be selected according to a preset strategy threshold, or different strategies can be sequentially adopted according to a set sequence until the pixel clock frequency is reduced to be lower than the maximum working frequency threshold, so as to improve flexibility and reliability of working frequency adjustment; shunting the data to be processed according to the adjusted working parameters, and obviously reducing the working frequency of the chip; the data distribution instruction is generated according to the preset format, and the signaling interaction among the modules of the video image processing system is realized according to the master-slave structure relationship, so that the transmission efficiency of the data stream is improved, and the stability of the data stream transmission is ensured.
EXAMPLE III
Fig. 3 is a schematic structural diagram of a data distribution device according to a third embodiment of the present invention. As shown in fig. 3, the data distribution apparatus provided in this embodiment includes:
a decision module 310, configured to determine an operating frequency adjustment policy of a video image processing system according to a pixel clock frequency of the video image processing system and a maximum operating frequency threshold of data processing;
an adjusting module 320, configured to adjust a working parameter of the video image processing system according to the working frequency adjustment policy;
the allocating module 330 is configured to allocate the valid data to be processed to a data stream according to the working parameter.
According to the data distribution device provided by the third embodiment of the invention, the working parameters are adjusted and the data are distributed according to the pixel clock frequency and the maximum working frequency threshold value of the data processing, so that the actual working frequency is lower than the maximum working frequency threshold value, the working frequency of the integrated chip is reduced, and the running stability of the video image processing system is improved.
On the basis of the above embodiment, the method further includes:
and the calculating module is used for calculating the pixel clock frequency of the video image processing system according to the panel time sequence parameter, the frame rate parameter and the input pixel number of each clock supported by the video image processing system.
On the basis of the above embodiment, the decision module 310 includes:
a comparison unit for comparing the pixel clock frequency with the maximum operating frequency threshold;
a decision unit, configured to select a corresponding operating frequency adjustment policy according to a preset policy threshold if the pixel clock frequency is greater than the maximum operating frequency threshold, so that the pixel clock frequency is less than or equal to the maximum operating frequency threshold;
the preset strategy threshold value is at least one, and the working frequency adjusting strategy is at least one.
Further, the method also comprises the following steps:
and the readjusting module is used for re-determining a working frequency adjustment strategy and adjusting the working parameters of the video image processing system according to the working frequency adjustment strategy if the pixel clock frequency corresponding to the adjusted working parameters is greater than the maximum working frequency threshold value until the pixel clock frequency corresponding to the working parameters is less than or equal to the maximum working frequency threshold value, so as to obtain the adjusted working parameters.
Further, the operating frequency adjustment strategy includes at least one of:
adjusting the number of input pixels of each clock;
adjusting the pixel number processed by each clock of the data bearing chip;
adjusting the caching quantity of the data stream;
adjusting the number of channels supported by the video image processing system;
the operating parameter default or current values are used.
Further, the method also comprises the following steps:
a generating module, configured to generate a data allocation instruction, where the data allocation instruction includes:
a maximum operating frequency threshold indication field for indicating a maximum operating frequency threshold for data processing;
a channel number indication field for indicating the number of channels supported by the video image processing system;
a frame rate indication field for indicating an actual frame rate of the panel;
and the data stream buffering quantity indication field is used for indicating the buffering and output format of the data.
Further, the data allocation instructions further include:
and the master-slave module definition field is used for indicating the signaling interaction relation between the integrated chip and the modules of the video image processing system in the data distribution process.
The data distribution device provided by the third embodiment of the invention can be used for executing the data distribution method provided by any of the above embodiments, and has corresponding functions and beneficial effects.
Example four
Fig. 4 is a schematic diagram of a hardware structure of an integrated chip according to a fourth embodiment of the present invention. The integrated chip may be a Field Programmable Gate Array (FPGA), a Micro Control Unit (MCU), a Digital Signal Processor (DSP), or the like. As shown in fig. 4, the integrated chip provided in this embodiment includes: a processor 410 and a storage 420. The number of the processors in the integrated chip may be one or more, fig. 4 illustrates one processor 410, the processor 410 and the storage device 420 in the integrated chip may be connected by a bus or in other manners, and fig. 4 illustrates the connection by a bus.
The one or more programs are executed by the one or more processors 410, causing the one or more processors to implement the data distribution method described in any of the embodiments above.
The storage device 420 in the integrated chip serves as a computer-readable storage medium for storing one or more programs, which may be software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the data distribution method in the embodiment of the present invention (for example, the modules in the data distribution device shown in fig. 3, including the decision module 310, the adjustment module 320, and the distribution module 330). The processor 410 executes various functional applications of the integrated chip and data processing by executing software programs, instructions and modules stored in the storage device 420, that is, implements the data distribution method in the above method embodiment.
The storage device 420 mainly includes a storage program area and a storage data area, wherein the storage program area can store an operating system and an application program required by at least one function; the storage data area may store data created according to the use of the integrated chip, etc. (operating parameters, operating frequency adjustment strategies, etc. as in the above-described embodiments). Further, the storage 420 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, storage 420 may further include memory located remotely from processor 410, which may be connected to the integrated chip over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
And, when one or more programs included in the above integrated chip are executed by the one or more processors 410, the following operations are performed: determining a working frequency adjustment strategy of the video image processing system according to a pixel clock frequency of the video image processing system and a maximum working frequency threshold value of data processing; adjusting the working parameters of the video image processing system according to the working frequency adjusting strategy; and distributing the data to be processed to at least one data stream according to the working parameters.
The integrated chip proposed by the present embodiment and the data distribution method proposed by the above embodiments belong to the same inventive concept, and technical details that are not described in detail in the present embodiment can be referred to any of the above embodiments, and the present embodiment has the same beneficial effects as the data distribution method.
EXAMPLE five
The fifth embodiment of the invention provides a video image processing system. Fig. 5 is a schematic structural diagram of a video image processing system according to a fifth embodiment of the present invention. As shown in fig. 5, the system includes an embedded control module 10, an external module 30, and an integrated chip 20, wherein the integrated chip 20 is connected to the embedded control module 10 and the external module 30 respectively; the embedded control module 10 is configured to initiate a data allocation request to the integrated chip 20; the external module 30 is used for storing video data to be processed and providing a physical layer interface for displaying video image data.
The embedded control module 10 may adopt any embedded chip and system, and is configured to initiate a data allocation request, and may also be configured to request to read/write register data, request to enable/close a video display unit or module, request peripheral control or request to modify parameter settings of the video display module, and the like. The integrated chip 20 is configured to determine an operating frequency adjustment policy according to a clock pixel frequency, adjust an operating parameter, and allocate data to be processed, and is further configured to implement or execute operations that require a large amount of data processing and low round-trip delay (latency) such as storage control, peripheral control, and video interface IP core implementation.
Fig. 6 is a schematic diagram illustrating an implementation of a video image processing system according to a fifth embodiment of the present invention. As shown in fig. 6, the external module 30 includes an external storage module, a fast storage module, a peripheral module, and a video interface physical layer implementation module, where the external storage module is used to store the original data stream of the video or image to be displayed in the system. For example, the external storage module may employ a Flash memory (e.g., Nand Flash), a Solid State Drive (SSD), and other storage media. In the case of a fast memory module, which needs to perform a large amount of Data processing and low round-trip delay (latency) signaling execution within the integrated chip 20, a fast and low latency Physical device, such as a Double Data Rate SDRAM (DDR) or the like, may be used to temporarily store Data, a peripheral module may be a General-purpose input/output (GPIO), a Universal Asynchronous Receiver/Transmitter (UART), a Universal Serial Bus (USB), a network Port or the like, a video interface Physical Layer implementation module is used to drive a Physical Layer implementation of a Display module, such as a Physical Layer (PHY) of a transceiver/Receiver (TX/RX) of a Display interface (Display Port, DP), a port Physical Layer (D-PHY) of a Serial Display Interface (MIPI) of a Mobile Industry Processor Interface (Mobile Industry Processor Interface).
As shown in fig. 6, the integrated chip 20 may specifically include one or more of the following: the device comprises a bus interaction module, an MCU, a video stream preprocessing unit, a video data stream transmission control module, a clock control module, an embedded soft core control module, a bus controller module, a video pattern processing module, an internal storage controller module, a peripheral control module, a display clock generator module, a video time schedule controller module and a video interface IP core module.
Illustratively, the bus interaction module is used for selecting or deciding all modules connected with the bus interaction module; the MCU video stream preprocessing unit is used for preprocessing and converting the video data stream input from the external storage module according to the format and the parameter type set by the system so as to facilitate subsequent processing; the video data stream transmission control module is used for controlling the time sequence and parameters of the data stream after the data stream is preprocessed and converted; the clock control module is responsible for generating and controlling a global clock in the process of processing the video or the image; the embedded soft core control module is a control core of the FPGA module, is used for realizing core functions of time sequence control, parameter configuration, physical process realization and the like of all modules in the FPGA module, and can adopt Xilinx soft sum processors (MicroBlaze) and the like; the bus controller module is used for controlling all modules connected with the bus interaction module; the video pattern processing module is responsible for adapting to mode conversion and time sequence control of a video image data stream corresponding to the video interface IP core module; the internal storage controller module is used for realizing the control of the fast storage module, including the writing/reading of data stream, frame control and the like; the peripheral control module is used for controlling all peripheral modules, including starting/closing of the peripheral, working mode control and the like; the display clock generator module is used for realizing the time sequence control of all modules, namely the video interface IP core module and the video interface physical layer; the video time sequence controller module is responsible for data conversion, time sequence control and the like in the process of transmitting data input from the video pattern processing module to the video interface IP core module. It should be noted that a plurality of modules inside the integrated chip 20, and the embedded control module 10 and the external module 30 may have a master-slave relationship.
The video image processing system of this embodiment can establish a perfect signaling interaction mechanism by defining a preset message structure and format, and each group of modules having a master-slave relationship performs signaling forwarding and interaction in respective links, so as to clarify the interaction structure and specification of each module, implement organized and precise signaling interaction between master and slave modules, complete data stream conversion under the condition of ensuring seamless, smooth and no dead halt between a hardware system and a platform, and meanwhile ensure that the system has minimum effective system delay on the premise of event driving, and improve the reliability and efficiency of interaction.
The video image processing system provided by the fifth embodiment can be used for executing the data distribution method provided by any of the above embodiments, and has corresponding functions and advantages.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A data distribution method is applied to an integrated chip of a video image processing system, and is characterized by comprising the following steps:
determining a working frequency adjustment strategy of the video image processing system according to a pixel clock frequency of the video image processing system and a maximum working frequency threshold value of data processing;
adjusting the working parameters of the video image processing system according to the working frequency adjusting strategy;
and distributing the data to be processed to at least one data stream according to the working parameters.
2. The method of claim 1, further comprising, prior to determining an operating frequency adjustment policy for a video image processing system based on a pixel clock frequency of the video image processing system and a maximum operating frequency threshold for data processing:
and calculating the pixel clock frequency of the video image processing system according to the panel time sequence parameter, the frame rate parameter and the input pixel number of each clock supported by the video image processing system.
3. The method of claim 1, wherein determining an operating frequency adjustment policy for a video image processing system based on a pixel clock frequency of the video image processing system and a maximum operating frequency threshold for data processing comprises:
comparing the pixel clock frequency to the maximum operating frequency threshold;
if the pixel clock frequency is greater than the maximum working frequency threshold, selecting a corresponding working frequency adjustment strategy according to a preset strategy threshold so as to enable the pixel clock frequency to be less than or equal to the maximum working frequency threshold;
the preset strategy threshold value is at least one, and the working frequency adjusting strategy is at least one.
4. The method of claim 3, further comprising:
if the pixel clock frequency corresponding to the adjusted working parameter is greater than the maximum working frequency threshold, re-determining a working frequency adjustment strategy and adjusting the working parameter of the video image processing system according to the working frequency adjustment strategy until the pixel clock frequency corresponding to the working parameter is less than or equal to the maximum working frequency threshold, so as to obtain the adjusted working parameter.
5. The method of claim 1, wherein the operating frequency adjustment strategy comprises at least one of:
adjusting the number of input pixels of each clock;
adjusting the pixel number processed by each clock of the data bearing chip;
adjusting the caching quantity of the data stream;
adjusting the number of channels supported by the video image processing system;
the operating parameter default or current values are used.
6. The method of any one of claims 1-5, further comprising: generating a data allocation instruction, wherein the data allocation instruction comprises:
a maximum operating frequency threshold indication field for indicating a maximum operating frequency threshold for data processing;
a channel number indication field for indicating the number of channels supported by the video image processing system;
a frame rate indication field for indicating an actual frame rate of the panel;
and the data stream buffering quantity indication field is used for indicating the buffering and output format of the data.
7. The method of claim 6, wherein the data allocation instructions further comprise:
and the master-slave module definition field is used for indicating the signaling interaction relation between the integrated chip and the modules of the video image processing system in the data distribution process.
8. A data distribution apparatus, comprising:
the decision module is used for determining a working frequency adjusting strategy of the video image processing system according to the pixel clock frequency of the video image processing system and the maximum working frequency threshold value of data processing;
the adjusting module is used for adjusting the working parameters of the video image processing system according to the working frequency adjusting strategy;
and the distribution module is used for distributing the effective data to be processed to the data flow according to the working parameters.
9. An integrated chip, comprising:
one or more processors;
storage means for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement a data distribution method as claimed in any one of claims 1-7.
10. A video image processing system, comprising: an embedded control module, an external module and an integrated chip according to claim 9, the integrated chip being connected to the embedded control module and the external module, respectively;
the embedded control module is used for initiating a data distribution request to the integrated chip;
the external module is used for storing video data to be processed and providing a physical layer interface for displaying the video image data.
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