CN113535508B - RISC-V many-core processor-oriented power consumption monitoring circuit - Google Patents
RISC-V many-core processor-oriented power consumption monitoring circuit Download PDFInfo
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Abstract
The invention discloses a power consumption monitoring circuit for a RISC-V multi-core processor. The power consumption monitoring circuit comprises five modules of decoding, analyzing, controlling, monitoring and storing; the analysis module analyzes the circuit structure of the processor core and generates a required monitoring signal by using an original signal of the circuit structure, and the storage module sends monitoring data to the processor core for software processing after the monitoring is finished; when the many-core processor runs a training set, the power consumption monitoring circuit provides monitoring data and trains a dynamic power consumption model of the processor core; when the many-core processor runs the test set, the power consumption monitoring circuit carries out real-time monitoring and deduces the dynamic power consumption value of the processor core according to the dynamic power consumption model. The power consumption monitoring circuit is configured by RISC-V instructions, and estimates the dynamic power consumption of all processor cores of the many-core processor. The invention can be applied to dynamic voltage frequency regulation and power consumption management of an operating system, and further analyzes and optimizes the power consumption of the system.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a power consumption monitoring circuit for a RISC-V multi-core processor.
Background
Moore's law has slowed down and system designers have no longer relied simply on shrinking transistor sizes to achieve system performance gains, but have relied more on system architecture development and algorithm optimization to achieve performance gains. In terms of processor architecture development, multi-core processor architectures and many-core processor architectures have become an important trend in the development of computer architectures today. The RISC-V instruction set appearing in recent years has many advantages such as open source, simplicity, and convenience for expansion.
The power wall problem has become a critical issue for today's various types of computer systems, and therefore low power designs are necessary. Power consumption assessment (power consumption prediction) is required at various stages of circuit design in order to make reasonable power consumption allocation and thus reduce system power consumption. The more accurate the power consumption assessment, the more advantageous the system low power consumption design. The power consumption evaluation can be used for a dynamic voltage frequency adjustment technology of the system, and the energy efficiency ratio of the system is optimized. The power consumption evaluation can also be used for operating system power consumption management and developing a task scheduling mechanism with power consumption perception capability, so that the system power consumption is optimized in real time.
Common power consumption evaluation schemes include an adjusting method, a scheduling method, an integrating method and the like. In addition, researchers also often use performance counters in some processor systems for system performance monitoring, and power consumption prediction is performed by using these monitoring data, because some performance events of the processor have close correlation with dynamic power consumption of the processor. However, the existing research work is limited to the software aspect and the system power consumption modeling aspect, and only a performance counter of a processor system is used without designing a special monitoring module, so that a monitoring event set cannot be selected arbitrarily, and the accuracy of power consumption prediction is limited. Furthermore, since the initial design of these performance counters is for processor performance monitoring, the monitored data does not necessarily reflect the dynamic power consumption characteristics of the processor well.
Disclosure of Invention
The invention aims to provide a monitoring circuit capable of accurately monitoring the power consumption of a RISC-V many-core processor in real time.
The invention firstly selects a special monitoring event set for the RISC-V many-core processor so as to better reflect the power consumption characteristics of the many-core processor, and designs a power consumption monitoring circuit for monitoring the power consumption of the processor. The invention provides a power consumption monitoring circuit for a RISC-V many-core processor, which monitors each core of the many-core processor in real time, and the monitoring data are substituted into a dynamic power consumption model to calculate a dynamic power consumption estimated value. The power consumption monitoring circuit is configured by adopting RISC-V instructions and automatically sends monitoring information to a CSR module of a processor core after monitoring is finished so as to be processed by software.
The power consumption monitoring circuit for the RISC-V many-core processor provided by the invention monitors the dynamic power consumption of all processor cores of the many-core processor in real time according to the monitoring signals of the monitoring event set and sends the monitoring data to software so as to substitute a dynamic power consumption model of the processor cores to calculate the dynamic power consumption value of the many-core processor in real time; the power consumption monitoring circuit comprises a decoding module, an analysis module, a control module, a monitoring module and a storage module; wherein:
the decoding module decodes the instruction to generate a corresponding control signal and configuration information; when the command is a CSR command, the decoding module analyzes the CSR command and determines whether to reset the power consumption monitoring circuit or configure the power consumption monitoring circuit according to the specific value of the CSR command; when the power consumption monitoring circuit is configured, the decoding module is used for taking a CSR address contained in the analyzed CSR instruction as an address of each configuration register in the power consumption monitoring circuit and configuring the value of the corresponding power consumption monitoring circuit configuration register according to the corresponding address; the corresponding control signal generated by the decoding module is also used for controlling the jump of the state of the power consumption monitoring circuit;
the analysis module is used for taking out original signals from the inside of the processor core, generating each monitoring signal with corresponding event meaning in the monitoring event set by analyzing the circuit structure characteristics of the processor core, and transmitting the monitoring signals to the monitoring module for monitoring;
the monitoring event set comprises an event that a processor core does not stop, an event that an instruction is executed completely, a branch misprediction event, a multiply-divide-and-fetch instruction event, an instruction address jump event, an instruction cache non-busy event and a processor clock event;
generating each monitoring signal of the monitoring event set in a mode depending on the circuit structure of the selected processor core, and generating a monitoring signal with the meaning of the monitoring event according to the circuit structure of the processor core so as to reflect the dynamic power consumption characteristics of the processor;
the processor core does not stop events, reflects the working state of the processor core, and monitoring signals of the processor core are generated by carrying out NOR operation on id _ self _ stall "," id _ back _ stall "and" ica _ stall "signals of the processor core;
the instruction execution finishing event reflects the condition that the instruction is correctly executed and is not flushed by a pipeline, and the monitoring signal is generated by performing NOR operation on the wb _ bubble and wb _ stall signals of the processor core;
a branch misprediction event which reflects that a processor core performs branch prediction incorrectly and therefore a pipeline needs to be flushed so as to consume a large amount of dynamic power consumption, wherein monitoring signals of the branch misprediction event are generated by 'wrong _ jarr _ pc', 'front _ cache _ busy', 'mem _ bucket', 'mem _ stall', 'wrong _ branch _ pc' signals of the processor core together;
the multiply-divide-and-remainder event reflects the conditions of multiply-divide-and-remainder operation performed by the processor core, under the conditions, the processor core generates more dynamic power consumption, and a monitoring signal of the processor core is generated by an instruction signal and an instruction effective signal of the processor core;
the instruction address jump event reflects the condition that the processor core has an instruction branch, and a monitoring signal of the instruction address jump event is generated by an instruction address signal of the processor core at the current moment and historical information of the instruction address signal;
an instruction cache not-busy event reflecting an instruction cache not-busy condition, in which case the processor core can continue to fetch instructions from the instruction cache, the event monitoring signal being generated by inverting a "front _ cache _ busy" signal of the processor core;
a processor clock event reflecting a clock of the processor core;
the control module controls the skipping of the state according to the control signal generated by the decoding module; the states of the power consumption monitoring module comprise an idle state, a configuration state, a monitoring state and a storage state; the power consumption monitoring circuit in the idle state almost consumes no dynamic power consumption; when the power consumption monitoring circuit is configured by the instruction, the power consumption monitoring circuit enters a configuration state; the power consumption monitoring circuit does not monitor in a configuration state, and both a configuration register and a monitor in the power consumption monitoring circuit can write data; when the CSR instruction is adopted to configure the power consumption monitoring circuit, the power consumption monitoring circuit sends internal initial data to a general register of a processor core; after the instruction is configured with the power consumption monitoring circuit, the power consumption monitoring circuit jumps to a monitoring state; the power consumption monitoring circuit cannot be written with data in a monitoring state, and monitors and counts each event of the processor in a set monitoring clock interval; after the monitoring is finished, the power consumption monitoring circuit jumps to a storage state; in the storage state, the power consumption monitoring circuit stores the configuration information and the monitoring values of the monitors in the CSR module of the processor core in sequence;
the monitoring module mainly stores 12 monitors; wherein 7 monitors monitor the aforementioned 7 selected events; the other 2 monitors monitor other events; the rest 3 monitors are respectively used for monitoring the global clock and recording the set starting monitoring time and the set ending monitoring time; the monitors can identify the state of the power consumption monitoring circuit and monitor and count the monitoring signals generated by the analysis module in the monitoring state; the monitor can also identify the set monitoring clock interval so as to accurately monitor the target program;
the storage module sends monitoring information and configuration information to a CSR module of the processor core after monitoring is finished so as to be called and processed by software; the storage module adopts a storage address pointer, sequentially points to registers for storing monitoring information and configuration information in the power consumption monitoring circuit, and serially stores the data into the register of the CSR module;
the power consumption monitoring circuit provided by the invention can be configured by RISC-V instructions, and configure information such as starting monitoring time, finishing monitoring time and the like so as to accurately track the execution stage of a target program; when the instruction configures the power consumption monitoring circuit, the power consumption monitoring circuit transmits information to a general register file of the processor core; the power consumption monitoring circuit is integrated into each tile (the tile is generally composed of modules such as a first-level data cache, a first-level instruction cache and a processor core) of the many-core processor to interact with the processor core; here, tile is composed of a first level data cache, a first level instruction cache, and a processor core.
Compared with the prior art, the beneficial technical effects of the invention are as follows:
(1) the invention specially designs a power consumption monitoring circuit for the processor core of the RISC-V many-core processor, but the prior art does not design the power consumption monitoring circuit of the RISC-V many-core processor;
(2) the power consumption monitoring circuit designed by the invention can be configured by RISC-V instructions, and different functions of the power consumption monitoring circuit are integrated into different modules by adopting a modular design method, thereby being more beneficial to the expansion of the power consumption monitoring circuit. The power consumption monitoring circuit also selects a proper power consumption event set so as to improve the accuracy of power consumption estimation;
(3) the method is an important link of a real-time power consumption prediction technology, and the real-time power consumption prediction can be applied to aspects of dynamic voltage frequency adjustment, power consumption management of an operating system and the like, so that the system power consumption is monitored, analyzed and optimized.
Drawings
FIG. 1 is a diagram of power consumption monitoring circuitry interacting with a processor core.
FIG. 2 is a diagram of monitor signal generation for processor core unstalling events.
FIG. 3 is a diagram illustrating the generation of monitor signals for an instruction completion event.
FIG. 4 is a graph of monitor signal generation for branch misprediction events.
FIG. 5 is a graph of monitor signal generation for multiply-divide remainder events.
FIG. 6 is a diagram of a power consumption monitoring circuit integrated into a many-core processor.
Detailed Description
The circuit structure of the power consumption monitoring circuit and the interaction mode of the power consumption monitoring circuit and the processor core are shown in fig. 1. A power consumption monitoring circuit for a RISC-V many-core processor monitors the dynamic power consumption of all processor cores of the many-core processor in real time according to monitoring signals of a monitoring event set and sends monitoring data to software so as to substitute a dynamic power consumption model of the processor cores to calculate the dynamic power consumption value of the many-core processor in real time; the power consumption monitoring circuit comprises a decoding module, an analysis module, a control module, a monitoring module and a storage module; wherein:
the decoding module decodes the instruction to generate a corresponding control signal and configuration information; when the command is a CSR command, the decoding module analyzes the CSR command and determines whether to reset the power consumption monitoring circuit or configure the power consumption monitoring circuit according to the specific value of the CSR command; when the power consumption monitoring circuit is configured, the decoding module is used for taking a CSR address contained in the analyzed CSR instruction as an address of each configuration register in the power consumption monitoring circuit and configuring the value of the corresponding power consumption monitoring circuit configuration register according to the corresponding address; the corresponding control signal generated by the decoding module is also used for controlling the jump of the state of the power consumption monitoring circuit;
the analysis module takes out original signals from the inside of the processor core, generates each monitoring signal with corresponding event meaning in the monitoring event set by analyzing the circuit structure characteristics of the processor core, and then transmits the monitoring signals to the monitoring module for monitoring;
the monitoring event set comprises an event that a processor core does not stop, an event that an instruction is executed completely, a branch misprediction event, a multiply-divide-and-fetch instruction event, an instruction address jump event, an instruction cache non-busy event and a processor clock event;
generating each monitoring signal of the monitoring event set in a mode depending on the circuit structure of the selected processor core, and generating a monitoring signal with the meaning of the monitoring event according to the circuit structure of the processor core so as to reflect the dynamic power consumption characteristics of the processor;
the processor core non-stop event reflects the operating state of the processor core, and the monitoring signal generation thereof is as shown in fig. 2. The id _ self _ stall signal indicates a stall in the pipeline stage of the decoding stage. The id _ back _ stall signal indicates that a stall occurs in the pipeline stage following the decode stage. The two are phase-or-operated to indicate that the back-end module is in a pause state, which is named as a back _ stall signal. Here, the processor core includes two parts, a front end module and a back end module. The icache _ stall signal indicates that the instruction cache is stalled, which causes a stall in the processor core front-end module, since the processor core front-end module is used to fetch instructions from the instruction cache. If neither stall occurs, then the processor core will not stall. The two signals are then NOR-operated to generate a monitor signal for the processor core unstart event.
The finish instruction event reflects the condition that the instruction is executed correctly without being flushed by the pipeline, and the monitor signal is generated as shown in fig. 3. The write back stage is the last stage of the processor core pipeline, so that the instruction execution completion event can be determined at the stage. Where the wb _ bubble signal indicates that the write-back stage is bubbling and the wb _ stall signal indicates that the write-back stage is stalling. If the write back stage does not bubble and does not stall, then the instruction may be declared complete. Therefore, the signals of the two are negated, and then the AND operation is carried out to obtain a monitoring signal of the event that the instruction execution is finished.
A branch misprediction event reflects that the processor core mispredicted branch and therefore needs to flush the pipeline consuming a lot of dynamic power, with its monitor signal generation as shown in fig. 4. For the access stage pipeline stage, if the wrong PC value is fetched and the instruction cache is not busy at this time, the instruction cache sends the wrong instruction to the processor core. If the access stage is executing normally at this time, the processor core may generate a branch misprediction signal to flush the pipeline. The mem _ bubble signal indicates that the access level generates bubbles, and the mem _ stall signal indicates that the access level generates pauses, so that the condition that the access level normally executes can be indicated by taking the two signals to perform the AND operation no longer. And then the three conditions of normal execution of the access level, no busy instruction cache and wrong PC value fetching are subjected to AND operation, and the generation of the branch misprediction event can be represented.
The multiply-divide-and-remainder event reflects the situation where the processor core performs the multiply-and-divide-and-remainder operation, and in these cases, the processor core generates more dynamic power consumption, and the monitor signal thereof is generated as shown in fig. 5. If the current instruction conforms to the encoding of the multiply/divide/remainder instruction and the instruction valid signal of the current instruction is high, the processor core fetches the valid multiply/divide/remainder instruction, and thus generates a corresponding monitor signal in the manner of fig. 5.
The instruction address jump event reflects the condition that the processor core has an instruction branch, and a monitoring signal of the instruction address jump event is generated by an instruction address signal of the processor core at the current moment and historical information of the instruction address signal;
an instruction cache not-busy event reflects an instruction cache not-busy condition, in which case the processor core can continue fetching instructions from the instruction cache, the event monitor signal may be generated by inverting a "front _ cache _ busy" signal of the processor core;
the processor clock event reflects a clock of the processor core;
the control module controls the skipping of the state according to the control signal generated by the decoding module; the states of the power consumption monitoring circuit comprise an idle state, a configuration state, a monitoring state and a storage state; the power consumption monitoring circuit in the idle state almost consumes no dynamic power consumption; when the power consumption monitoring circuit is configured by the instruction, the power consumption monitoring circuit enters a configuration state; the power consumption monitoring circuit does not monitor in a configuration state, and both a configuration register and a monitor in the power consumption monitoring circuit can write data; when the CSR instruction is adopted to configure the power consumption monitoring circuit, the power consumption monitoring circuit sends internal initial data to a general register of a processor core; after the instruction is configured with the power consumption monitoring circuit, the power consumption monitoring circuit jumps to a monitoring state; the power consumption monitoring circuit cannot be written with data in a monitoring state, and monitors and counts each event of the processor in a set monitoring clock interval; after the monitoring is finished, the power consumption monitoring circuit jumps to a storage state; in the storage state, the power consumption monitoring circuit stores the configuration information and the monitoring values of the monitors in the CSR module of the processor core in sequence;
the monitoring module mainly stores 12 monitors; wherein 7 monitors monitor the aforementioned 7 selected events; the other 2 monitors monitor other events; the rest 3 monitors are respectively used for monitoring the global clock and recording the set starting monitoring time and the set ending monitoring time; the monitors can identify the state of the power consumption monitoring module and monitor and count the monitoring signals generated by the analysis module in the monitoring state; the monitor can also identify the set monitoring clock interval so as to accurately monitor the target program;
the storage module sends the monitoring information and the configuration information to a CSR module of the processor core after the monitoring is finished so as to be called and processed by software; the storage module adopts a storage address pointer, sequentially points to registers for storing monitoring information and configuration information in the power consumption monitoring circuit, and serially stores the data into the register of the CSR module;
the power consumption monitoring circuit is configured by an RISC-V instruction; the instruction cache sends an instruction to the processor core and the power consumption monitoring circuit to complete the configuration of the power consumption monitoring circuit, and the power consumption monitoring circuit performs data interaction with a general register of the processor core in the configuration process; the configuration instruction of the power consumption monitoring circuit is processed by the decoding module, a control signal is generated to control the state jump of the power consumption monitoring circuit, and the starting monitoring time and the ending monitoring time of the configuration information configuration monitoring module are generated; after configuration is completed, the power consumption monitoring circuit monitors the processor core and monitors each event in the processor core in real time; at the moment, an initial signal transmitted by the processor core is processed by an analysis module of the power consumption monitoring circuit to generate a monitoring signal with corresponding event meaning, and then the monitoring signal is transmitted to the monitoring module for monitoring; after the monitoring time is up, the control module controls the power consumption monitoring module to enter a storage state and sends a storage enabling signal to the storage module; the memory module of the power consumption monitoring circuit sequentially stores internal monitoring information and configuration information into a register of the CSR module according to the increment of the memory address pointer; the processor core may then read this information into a general purpose register via a CSR instruction, thereby making this information visible to software; each processor core of the many-core processor can also send the monitoring information of each core to a designated processor core, so that the processor core can summarize and process the monitoring data of all cores and generate a total dynamic power consumption estimation value.
The way the power consumption monitoring circuit is integrated into a many-core processor is shown in figure 6. Each power consumption monitoring circuit is integrated into a tile of a many-core processor. A tile includes two routers, a network on chip interface (NI), a level one instruction cache, a level one data cache, a processor core, and a power consumption monitoring circuit (pmu). 4 tiles form a cluster (cluster), and a cluster carries a second level cached fragment (slice). The 16 clusters constitute a 64-core many-core processor.
Claims (2)
1. A power consumption monitoring circuit facing a RISC-V many-core processor is characterized in that dynamic power consumption of all processor cores of the many-core processor is monitored in real time according to monitoring signals of a monitoring event set, monitoring data are sent to software, and the monitoring data are substituted into a dynamic power consumption model of the processor cores to calculate dynamic power consumption values of the many-core processor in real time; the power consumption monitoring circuit comprises a decoding module, an analysis module, a control module, a monitoring module and a storage module; wherein:
the decoding module decodes the instruction to generate a corresponding control signal and configuration information; when the command is a CSR command, the decoding module analyzes the CSR command and determines whether to reset the power consumption monitoring circuit or configure the power consumption monitoring circuit according to the specific value of the CSR command; when the power consumption monitoring circuit is configured, the decoding module is used for taking a CSR address contained in the analyzed CSR instruction as an address of each configuration register in the power consumption monitoring circuit and configuring the value of the corresponding power consumption monitoring circuit configuration register according to the corresponding address; the corresponding control signal generated by the decoding module is also used for controlling the jump of the state of the power consumption monitoring circuit;
the analysis module is used for taking out original signals from the inside of the processor core, generating each monitoring signal with corresponding event meaning in the monitoring event set by analyzing the circuit structure characteristics of the processor core, and transmitting the monitoring signals to the monitoring module for monitoring;
the monitoring event set comprises an event that a processor core does not stop, an event that an instruction is executed completely, a branch misprediction event, a multiply-divide-and-fetch instruction event, an instruction address jump event, an instruction cache non-busy event and a processor clock event;
generating each monitoring signal of the monitoring event set in a mode depending on the circuit structure of the selected processor core, and generating a monitoring signal with the meaning of the monitoring event according to the circuit structure of the processor core so as to reflect the dynamic power consumption characteristics of the processor;
the processor core does not stop events, reflects the working state of the processor core, and monitoring signals of the processor core are generated by carrying out NOR operation on id _ self _ stall "," id _ back _ stall "and" ica _ stall "signals of the processor core;
the instruction execution finishing event reflects the condition that the instruction is correctly executed and is not flushed by a pipeline, and the monitoring signal is generated by performing NOR operation on the wb _ bubble and wb _ stall signals of the processor core;
a branch misprediction event which reflects that a processor core performs branch prediction incorrectly and therefore a pipeline needs to be flushed so as to consume a large amount of dynamic power consumption, wherein monitoring signals of the branch misprediction event are generated by 'wrong _ jarr _ pc', 'front _ cache _ busy', 'mem _ bucket', 'mem _ stall', 'wrong _ branch _ pc' signals of the processor core together;
the multiply-divide-and-remainder event reflects the conditions of multiply-divide-and-remainder operation performed by the processor core, under the conditions, the processor core generates more dynamic power consumption, and a monitoring signal of the processor core is generated by an instruction signal and an instruction effective signal of the processor core;
the instruction address jump event reflects the condition that the processor core has an instruction branch, and a monitoring signal of the instruction address jump event is generated by an instruction address signal of the processor core at the current moment and historical information of the instruction address signal;
an instruction cache not-busy event reflecting an instruction cache not-busy condition, in which case the processor core can continue to fetch instructions from the instruction cache, the event monitoring signal being generated by inverting a "front _ cache _ busy" signal of the processor core;
a processor clock event reflecting a clock of the processor core;
the control module controls the skipping of the state according to the control signal generated by the decoding module; the states of the power consumption monitoring circuit comprise an idle state, a configuration state, a monitoring state and a storage state; the power consumption monitoring circuit in the idle state almost consumes no dynamic power consumption; when the power consumption monitoring circuit is configured by the instruction, the power consumption monitoring circuit enters a configuration state; the power consumption monitoring circuit does not monitor in a configuration state, and both a configuration register and a monitor in the power consumption monitoring circuit can write data; when the CSR instruction is adopted to configure the power consumption monitoring circuit, the power consumption monitoring circuit sends internal initial data to a general register of a processor core; after the instruction is configured with the power consumption monitoring circuit, the power consumption monitoring circuit jumps to a monitoring state; the power consumption monitoring circuit cannot be written with data in a monitoring state, and monitors and counts each event of the processor in a set monitoring clock interval; after the monitoring is finished, the power consumption monitoring circuit jumps to a storage state; in the storage state, the power consumption monitoring circuit stores the configuration information and the monitoring values of the monitors in the CSR module of the processor core in sequence;
the monitoring module mainly stores 12 monitors; with 7 monitors for the aforementioned 7 selected events: monitoring a processor core non-stop event, an instruction execution finishing event, a branch misprediction event, a multiply-divide-and-fetch instruction event, an instruction address jump event, an instruction cache non-busy event and a processor clock event; the other 2 monitors monitor other events; the rest 3 monitors are respectively used for monitoring the global clock and recording the set starting monitoring time and the set ending monitoring time; the monitors can identify the state of the power consumption monitoring circuit and monitor and count the monitoring signals generated by the analysis module in the monitoring state; the monitor can also identify the set monitoring clock interval so as to accurately monitor the target program;
the storage module sends monitoring information and configuration information to a CSR module of the processor core after monitoring is finished so as to be called and processed by software; the memory module adopts a memory address pointer to sequentially point to registers storing monitoring information and configuration information in the power consumption monitoring circuit, and serially stores the data into the register of the CSR module.
2. The RISC-V many-core processor-oriented power consumption monitoring circuit of claim 1, wherein a RISC-V instruction is used for configuration, and start monitoring time and end monitoring time information are configured for accurately tracking the execution stage of a target program; when the instruction configures the power consumption monitoring circuit, the power consumption monitoring circuit transmits information to a general register file of the processor core; the power consumption monitoring circuit is integrated into each tile of the many-core processor to interact with the processor core; here, tile is composed of a first level data cache, a first level instruction cache, a processor core, a router that transmits a packet, a router that receives a packet, and an on-chip network interface.
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| CN112486312A (en) * | 2020-11-19 | 2021-03-12 | 杭州电子科技大学 | Low-power-consumption processor |
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