CN117093065A - Power regulation and control method and device for multi-core processor, computer equipment and medium - Google Patents
Power regulation and control method and device for multi-core processor, computer equipment and medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/329—Power saving characterised by the action undertaken by task scheduling
Abstract
The invention relates to the technical field of processors, and discloses a power regulation and control method and device of a multi-core processor, computer equipment and medium, wherein the power regulation and control method comprises the following steps: a first power measurement module is arranged in the multi-core processor and is respectively connected with a plurality of sub-processors in the multi-core processor; the method comprises the following steps: measuring the power value of at least one sub-processor in real time through a first power measuring module; and carrying out power regulation and control on at least one sub-processor according to the power value. According to the invention, by measuring the power of any at least one sub-processor in the multi-core processor and regulating and controlling the power of the sub-processor according to the power value, the power consumption of the sub-processor can be saved, and the situation that the CPU is rapidly down-frequency due to overload of a certain sub-processor and even restarted directly in severe cases can be prevented.
Description
Technical Field
The present invention relates to the field of processor technologies, and in particular, to a power regulation method and apparatus for a multi-core processor, a computer device, and a medium.
Background
For power consumption measurements of multi-core processors (Central Processing Unit, CPUs), in practical applications, the tasks to be run on each CPU core are different due to the different actual traffic demands, resulting in different core (core) loads, some cores may run under full load, and some cores may run under light load compared. Therefore, the original power consumption measurement scheme cannot know the actual load condition of each core in the CPU, and can only be adjusted by taking a single chip as a unit, so that the following problems occur: because the power consumption condition of each core cannot be obtained in real time, corresponding power consumption adjustment cannot be carried out on each core, and the purpose of saving power consumption cannot be achieved; in some extreme cases, a core overload condition may occur, which may cause the CPU to rapidly down-frequency, and even restart directly in severe cases.
Therefore, a power regulation and control method of a multi-core processor is needed, which can measure and regulate the power of a plurality of sub-processors in the multi-core processor in real time, thereby achieving the purpose of saving power consumption and avoiding the occurrence of overload of the sub-processors.
Disclosure of Invention
In view of the above, the present invention provides a power regulation method, apparatus, computer device and medium for a multi-core processor, so as to solve the problems of power consumption waste and overload caused by the fact that the power of each sub-processor in the multi-core processor cannot be measured and regulated in real time in the related art.
In a first aspect, the present invention provides a power regulation method for a multi-core processor, which is characterized in that a first power measurement module is set in the multi-core processor, and the first power measurement module is respectively connected with a plurality of sub-processors in the multi-core processor; the method comprises the following steps:
measuring the power value of at least one sub-processor in real time through the first power measuring module;
and carrying out power regulation and control on the at least one sub-processor according to the power value.
According to the power regulation and control method of the multi-core processor, by carrying out power measurement on any one of the sub-processors in the multi-core processor and carrying out power regulation and control on the sub-processors, the purposes of saving the power consumption of the sub-processors and preventing the occurrence of the situation that the CPU is rapidly down-frequency due to overload of a certain sub-processor and even is restarted directly in severe cases can be achieved.
In an alternative embodiment, the first power measurement module includes:
the control unit is used for issuing a measurement instruction to the power measurement unit when receiving a power measurement request sent by an external user; the measurement instruction comprises at least one target sub-processor; the target sub-processor is a sub-processor needing power measurement;
the power measurement unit is used for conducting a power measurement path corresponding to the target sub-processor according to the received measurement instruction, and the power measurement path is used for carrying out power measurement on the target sub-processor;
the cache unit is used for setting a plurality of sub-processor numbers corresponding to the plurality of sub-processors one by one and setting a plurality of cache queues corresponding to the plurality of sub-processor numbers one by one; the buffer queue is used for storing real-time power measurement values of the corresponding sub-processors.
In an alternative embodiment, the power measurement path includes a voltage sampling circuit;
measuring, by the first power measurement module, a power value of at least one sub-processor in real time, including:
acquiring a voltage value of a target sub-processor by using the voltage sampling circuit;
determining a current value according to the voltage value and the resistance value of the target sub-processor;
and determining the power value of the target sub-processor according to the current value and the voltage value.
In an alternative embodiment, performing power regulation on the at least one sub-processor according to the power value includes:
determining a first sub-processor from a plurality of sub-processors according to the power values of the sub-processors, wherein the first sub-processor is a sub-processor with the power value larger than a first power threshold;
combining tasks on a preset number of first sub-processors into a second sub-processor according to the power values of the plurality of first sub-processors; the sum of the power values of the first sub-processors with the preset number is smaller than a second power threshold, the preset number is related to the sum of the power values, and the second sub-processor is any one of the first sub-processors with the preset number.
According to the power regulation and control method of the multi-core processor, the tasks on the first sub-processors with the preset number are combined into the second sub-processor with the task combination values according to the power values of the first sub-processors, so that the sub-processors can be combined into one sub-processor with lighter loads, and other sub-processors can be in a dormant state, and the purpose of saving power consumption is achieved.
In an alternative embodiment, performing power regulation on the at least one sub-processor according to the power value includes:
monitoring power values of the plurality of sub-processors in real time;
when a second sub-processor is monitored from the plurality of sub-processors, distributing tasks running on the second sub-processor to a third sub-processor;
the second sub-processor is a sub-processor with a power value larger than a second power threshold, and the third sub-processor is a sub-processor with an available power value larger than or equal to the power value of the second sub-processor, and the second power threshold is larger than the first power threshold.
According to the power regulation and control method of the multi-core processor, when the second sub-processor is monitored from the plurality of sub-processors, the tasks running on the second sub-processor are distributed to the third sub-processor, so that when the load on a certain sub-processor is overweight, the tasks running on the sub-processor with the overweight load can be distributed to other sub-processors with light loads, and the problem of frequency reduction or restarting is further avoided.
In an alternative embodiment, performing power regulation on the at least one sub-processor according to the power value includes:
when a performance improvement request sent by an external user is received, measuring a power value of a fourth sub-processor corresponding to the performance improvement request;
and if the power value of the fourth sub-processor is smaller than the third power threshold, increasing the voltage value or the frequency value of the fourth sub-processor until the performance improvement condition of the fourth sub-processor meets the requirement of the performance improvement request.
According to the power regulation and control method of the multi-core processor, when the power value of the fourth sub-processor is smaller than the third power threshold, the voltage value or the frequency value of the fourth sub-processor is increased until the performance improvement condition of the fourth sub-processor meets the requirement of the performance improvement request, so that the task processing performance of the fourth sub-processor can be improved, and further the task processing efficiency is improved.
In an alternative embodiment, the buffer unit has a plurality of register interfaces corresponding to the plurality of sub-processors one by one, and the register interfaces are used for an external program to read the power values of the corresponding sub-processors through the register interfaces.
In an alternative embodiment, the second power measurement module is disposed external to the multicore processor; the method further comprises the steps of:
when the first power measurement module fails, controlling the second power measurement module to measure the overall power of the multi-core processor;
and adjusting the working state of the multi-core processor according to the measured integral power value.
In a second aspect, the present invention provides a power regulation apparatus for a multicore processor, the apparatus comprising:
the first power measurement module is used for measuring the power value of at least one sub-processor in real time through the first power measurement module;
and the power regulation and control module is used for carrying out power regulation and control on the at least one sub-processor according to the power value.
In a third aspect, the present invention provides a computer device comprising: the power regulation method of the multi-core processor according to the first aspect or any one of the corresponding embodiments of the first aspect is implemented by the processor and the memory, the memory and the processor are in communication connection with each other, the memory stores computer instructions, and the processor executes the computer instructions.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a multi-core processor according to an embodiment of the invention;
FIG. 2 is a flow chart of a power regulation method of a multi-core processor according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a multi-core processor including a first power measurement module according to an embodiment of the invention;
fig. 4 is a schematic structural view of a first power measurement module according to an embodiment of the present invention;
FIG. 5 is a flow diagram of another method of power regulation of a multi-core processor according to an embodiment of the invention;
FIG. 6 is a flow diagram of another method of power regulation of a multi-core processor according to an embodiment of the invention;
FIG. 7 is a flow diagram of another method of power regulation of a multi-core processor according to an embodiment of the invention;
FIG. 8 is a flow diagram of another method for power regulation of a multi-core processor according to an embodiment of the invention;
FIG. 9 is a block diagram of a power regulating device of a multi-core processor according to an embodiment of the invention;
fig. 10 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the related art, a multi-core CPU (taking 24 cores in fig. 1 as an example) generally adopts a mode of uniformly sampling power consumption of the whole CPU, that is, directly using an external power consumption sampling module to sample the current of the total power supply line of the CPU, and then according to a physical formula: power = voltage x current, resulting in a relatively coarse total power consumption of the CPU. At the software level, some policy adjustments are made based on this power, such as adjusting the operating frequency of the CPU, etc.
However, in practical applications, the tasks to be run on each CPU core are different according to the actual traffic demands, which results in different sub-processor (core) loads, some sub-processor cores may run under full load, and some sub-processor cores may run under light load.
For this application, the original scheme cannot know the actual load condition of each core in the CPU, and can only be adjusted by taking a single chip as a unit, which has the following problems:
(1) Because the power consumption of each core cannot be obtained in real time, the power consumption of each core cannot be regulated at the software level, so that the purpose of saving the power consumption is achieved;
in some extreme cases, a core overload may occur, which may cause the CPU to rapidly down-frequency, and even restart directly in severe cases.
Aiming at the defect that the traditional scheme is inflexible, the scheme removes the original external power consumption sampling module, and adds an internal power consumption sampling module, and the internal sampling module can acquire power consumption data of any core in a chip and can also provide data of total power consumption.
According to an embodiment of the present invention, there is provided a power regulation method embodiment of a multi-core processor, it should be noted that the steps illustrated in the flowchart of the drawings may be performed in a computer system such as a set of computer executable instructions, and that although a logic sequence is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in a different order than that herein.
The embodiment provides a power regulation method of a multi-core processor, which can be used for the multi-core processor. FIG. 2 is a flow chart of a power regulation method of a multi-core processor according to an embodiment of the invention. As shown in fig. 2, the power regulation method includes the following steps:
step S101, measuring, by the first power measurement module, a power value of at least one sub-processor in real time.
Specifically, as shown in fig. 3, a first power measurement module (i.e., an internal power consumption sampling module) is provided inside the multi-core processor, and the first power measurement module is respectively connected with a plurality of sub-processors (i.e., core1, core2,..core 23) inside the multi-core processor; the number of sub-processors may be set according to the number of cores of the multi-core processor, which is not particularly limited herein. The first power measurement module may be for measuring at least one sub-processor in the multi-core processor.
Step S102, performing power regulation and control on the at least one sub-processor according to the power value.
Specifically, when a power measurement instruction sent by an external user and aimed at one or more sub-processors is received, the power measurement is carried out on the one or more sub-processors through a first power measurement module; if an external user sends a power regulation command for the sub-processor, after measuring the power of the one or more sub-processors, a corresponding regulation strategy is performed according to the measured power value, for example, when the tasks running on the sub-processor 1 are overloaded due to excessive tasks, all or a part of the tasks in the sub-processor 1 are transferred to another sub-processor 2 with a power value of 0 or a lower power value to run.
According to the power regulation and control method for the multi-core processor, by carrying out power measurement on any one of the sub-processors in the multi-core processor and carrying out power regulation and control on the sub-processors, the purposes of saving the power consumption of the sub-processors and preventing the occurrence of the situation that the CPU is rapidly down-frequency due to overload of a certain sub-processor and even is restarted directly in severe cases can be achieved.
The invention has the technical effects that: the original scheme adopts an external unified power consumption measurement mode, and is changed into a power consumption measurement mode taking a single sub-processor as a unit. Compared with the traditional scheme, the scheme is more flexible, and specific fine-granularity power consumption management strategy adjustment can be performed according to the power consumption condition of each core. The method can more meet the actual application scene.
In some preferred embodiments, as shown in FIG. 4: the first power measurement module includes:
and the control unit is used for issuing a measurement instruction to the power measurement unit when receiving a power measurement request sent by an external user.
Specifically, the measurement instruction includes at least one target sub-processor, which can be understood as that an external user wants to know the real-time power value of the at least one target sub-processor; the target sub-processor is a sub-processor of the plurality of sub-processors that needs to make power measurements.
And the power measurement unit is used for conducting a power measurement path corresponding to the target sub-processor according to the received measurement instruction, and the power measurement path is used for carrying out power measurement on the target sub-processor.
In particular, the power measurement path may be understood as a path in which each sub-processor provides current sampling, such as by using a general ADC sampling circuit, by which voltages corresponding to the operating current are sampled, and then according to ohm's law: current = voltage/resistance, resulting in the current; finally, according to the formula: power = voltage x current, resulting in real-time power for the corresponding sub-processor.
The cache unit is used for setting a plurality of sub-processor numbers corresponding to the plurality of sub-processors one by one and setting a plurality of cache queues corresponding to the plurality of sub-processor numbers one by one; the buffer queue is used for storing real-time power measurement values of the corresponding sub-processors.
Specifically, the cache unit may number each sub-processor, and record the number and the corresponding sub-processor in the unit; the unit may also store the samples in the form of queues to obtain power consumption values of the corresponding sub-processors (e.g. a buffer queue is set for each sub-processor, and the sampled power consumption values are placed therein), and provide a register interface for external use. A program running on the multi-core processor may read the power value of the corresponding sub-processor through a register.
In some preferred embodiments, the power measurement path includes a voltage sampling circuit; the step S101 further includes:
in step S1011, the voltage value of the target sub-processor is acquired by using the voltage sampling circuit.
Step S1012, determining a current value according to the voltage value and the resistance value of the target sub-processor.
Step S1013, determining a power value of the target sub-processor according to the current value and the voltage value.
In the steps S1011 to S1013, the specific circuit structure of the voltage sampling circuit is not particularly limited, and it is only necessary to implement voltage measurement on the word processor; firstly, acquiring a real-time voltage value U of a target sub-processor by a voltage sampling circuit, and then calculating a real-time current value I of the target sub-processor according to the real-time voltage value U, a resistance value R and ohm law (i.e. I=U/R) of the target sub-processor; finally, determining the real-time power value of the target sub-processor through a power calculation formula (i.e., p=ui).
In some preferred embodiments, as shown in FIG. 5: the step S102 further includes steps a1 to a2, which are specifically as follows:
and a step a1, determining a first sub-processor from a plurality of sub-processors according to the power values of the sub-processors, wherein the first sub-processor is a sub-processor with the power value larger than a first power threshold.
Specifically, the first power threshold herein may be 0; and respectively carrying out power measurement on all the sub-processors in the multi-core processor, and taking the sub-processor with the power value larger than 0 as a first processor.
Step a2, merging tasks on a preset number of first sub-processors into a second sub-processor according to the power values of the plurality of first sub-processors; the sum of the power values of the first sub-processors with the preset number is smaller than a second power threshold, the preset number is related to the sum of the power values, and the second sub-processor is any one of the first sub-processors with the preset number. In this embodiment, the second power threshold is the rated power value of the sub-processor.
Specifically, the above step a2 will be described with reference to the following examples:
when there are 3 first sub-processors in the multi-core processor, and the power value of the first sub-processor 1 is 10, the power value of the first sub-processor 2 is 10, the power value of the first sub-processor 3 is 20, and the rated power value of each sub-processor is 60, since the sum of the power values of the 3 first sub-processors is 10+10+20=40 less than the rated power value 60, tasks on the first sub-processor 1, the first sub-processor 2, and the first sub-processor 3 can be transferred to any one of the 3 first sub-processors for operation.
In some preferred embodiments, as shown in fig. 6, the step S102 further includes steps b1-b2, which are specifically as follows:
and b1, monitoring power values of the plurality of sub-processors in real time.
Step b2, when a second sub-processor is monitored from the plurality of sub-processors, distributing tasks running on the second sub-processor to a third sub-processor; the second sub-processor is a sub-processor with a power value larger than a second power threshold, and the third sub-processor is a sub-processor with an available power value larger than or equal to the power value of the second sub-processor, and the second power threshold is larger than the first power threshold.
Specifically, in the above steps b1-b2, the available power value refers to the difference between the rated power value and the real-time power value of the sub-processor, and the second sub-processor may be understood as a sub-processor with overload and a real-time power greater than the rated power. When the second sub-processor is detected, all or part of the tasks running on the second sub-processor may be transferred to the third sub-processor.
Wherein when transferring all tasks running on the second sub-processor to a third sub-processor, the third sub-processor needs to be a sub-processor with an available power value that is greater than or equal to the power value of the second sub-processor. For example: the real-time power of the second sub-processor is 30, and the rated power of the second sub-processor is 20; the real-time power of the third sub-processor is 50, the rated power thereof is 90, namely the available power value of the third sub-processor is 90-50=40; the available power 40 of the third sub-processor is greater than the real-time power 30 of the second sub-processor, then all tasks running on the second sub-processor may be transferred to the third sub-processor for execution.
When transferring part of the tasks running on the second sub-processor to the third sub-processor, the third sub-processor needs to be a sub-processor with an available power value greater than or equal to a fourth power threshold, and the fourth power threshold is a difference value between the real-time power and the rated power of the second sub-processor. For example: the real-time power of the second sub-processor is 30, the rated power is 20, and the fourth power threshold value is 30-20=10; the real-time power of the third sub-processor is 50, the rated power thereof is 70, namely the available power value of the third sub-processor is 70-50=20; the available power 20 of the third sub-processor is greater than the fourth power threshold 10, then some of the tasks running on the second sub-processor may be transferred to the third sub-processor for execution.
In some preferred embodiments, as shown in fig. 7, the step S102 further includes steps c1-c2, which are specifically as follows:
and step c1, when a performance improvement request sent by an external user is received, measuring a power value of a fourth sub-processor corresponding to the performance improvement request.
And c2, if the power value of the fourth sub-processor is smaller than a third power threshold value, increasing the voltage value or the frequency value of the fourth sub-processor until the performance improvement condition of the fourth sub-processor meets the requirement of the performance improvement request. The third power threshold may be user-defined, and when the real-time power of the fourth sub-processor is greater than or equal to the third power threshold, it may be determined that the performance of the fourth sub-processor meets the user requirement.
Specifically, in the above steps c1-c2, the fourth sub-processor may be understood as a sub-processor that needs to perform performance improvement; when the controller receives a performance improvement request of an external user for the fourth sub-processor, the power of the fourth sub-processor is measured in real time, and when the real-time power value of the fourth sub-processor is smaller than a third power threshold, the purpose of improving the power value of the fourth sub-processor can be achieved by improving the voltage or the current of the fourth sub-processor until the real-time power value of the fourth sub-processor is larger than or equal to the third power threshold.
In some preferred embodiments, the buffer unit has a plurality of register interfaces corresponding to the plurality of sub-processors one by one, and the register interfaces are used for an external program to read power values of the corresponding sub-processors through the register interfaces.
In some preferred embodiments, as shown in FIG. 3: the multi-core processor further includes an external power supply module for supplying power to the plurality of sub-processors and the first power measurement module in the multi-core processor.
In some preferred embodiments, the controller may perform balanced allocation when allocating tasks according to the power consumption operation condition of all the sub-processors, so that the amount of tasks running on each sub-processor is equivalent. Therefore, the running efficiency of the program can be greatly improved, and the phenomenon that a user sees that a certain application is blocked is greatly reduced.
In some preferred embodiments, a second power measurement module is disposed external to the multi-core processor; the method further comprises the steps of:
when the first power measurement module fails, controlling the second power measurement module to measure the overall power of the multi-core processor; and adjusting the working state of the multi-core processor according to the measured integral power value.
Specifically, the second power measurement module measures the current of the total power supply line of the multi-core processor, and then obtains the total power of a rough multi-core processor according to the relation between power and voltage and current, namely, power=voltage×current; and finally, adjusting the working state of the multi-core processor according to the total power, for example, adjusting the operating frequency of the multi-core processor and the like.
In some preferred embodiments, as shown in FIG. 8:
allocating a corresponding id (namely number information) for each core in the multi-core processor, storing the number information of the core in memory components such as efuse in the chip, reading the information of the core by software after the system is electrified, and writing the information into a register related to the core number of an internal power consumption sampling module, wherein the internal power consumption sampling module knows that the managed core is related to the software through the id;
the software can turn on the switch of the internal power consumption sampling module through the register interface, and then the module automatically turns on the power consumption collection.
After the software turns on the internal power consumption sampling module switch, the power consumption value of one or more cores can be read and sampled at regular time.
Because the internal power consumption sampling module can provide total power consumption data, software can directly read the total power consumption of all the cores through the register, so that the external power consumption sampling function in the traditional scheme is compatible, and the internal power consumption sampling module is naturally compatible in software strategy.
The internal power consumption sampling module can automatically measure the real-time power consumption data of each core, record the real-time power consumption data in a corresponding register, and can also obtain the power consumption value of a certain core or a plurality of cores by the specification of software. The software controls the control unit in the internal power consumption sample by writing the corresponding register to achieve this function. This flexible approach can solve the problems encountered in most practical scenarios. Such as:
the power consumption values of all the cores are obtained at one time, the software can combine the tasks on a plurality of light-load cores onto one core, and then the other cores are put into a dormant state, so that the purpose of saving power consumption is achieved;
the software can set a safe upper limit of power consumption for each core, and when the power consumption corresponding to the acquired core approaches the upper limit, the software knows that the load on the core is overweight, and can distribute the task running on the core to the cores with other light loads, thereby avoiding the problems of frequency reduction or restarting.
Many other strategies such as load balancing, etc. may also be implemented by the software. (the software can perform balanced allocation when allocating tasks according to the current power consumption running conditions of all the cores, so that the amount of tasks running on each core is equivalent as much as possible, the running efficiency of the program can be greatly improved, and the phenomenon that a user sees that a certain application is blocked is greatly reduced).
The acquired power consumption data of a certain core can be used for feeding back input to provide basis for adjusting the frequency or voltage of the core or the whole CPU. If the current power consumption of a core is low, then its voltage or frequency can be increased appropriately when performance needs to be improved.
The embodiment also provides a power regulation device of a multi-core processor, which is used for implementing the foregoing embodiments and preferred implementations, and the description is omitted herein. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The present embodiment provides a power regulation device of a multi-core processor, as shown in fig. 9, including:
the first power measurement module is used for measuring the power value of at least one sub-processor in real time through the first power measurement module;
and the power regulation and control module is used for carrying out power regulation and control on the at least one sub-processor according to the power value.
In some alternative embodiments, the first power measurement module includes:
the control unit is used for issuing a measurement instruction to the power measurement unit when receiving a power measurement request sent by an external user; the measurement instruction comprises at least one target sub-processor; the target sub-processor is a sub-processor needing power measurement;
the power measurement unit is used for conducting a power measurement path corresponding to the target sub-processor according to the received measurement instruction, and the power measurement path is used for carrying out power measurement on the target sub-processor;
the cache unit is used for setting a plurality of sub-processor numbers corresponding to the plurality of sub-processors one by one and setting a plurality of cache queues corresponding to the plurality of sub-processor numbers one by one; the buffer queue is used for storing real-time power measurement values of the corresponding sub-processors.
In some alternative embodiments, the power measurement path includes a voltage sampling circuit; a first power measurement module comprising:
a voltage acquisition unit for acquiring a voltage value of the target sub-processor by using the voltage sampling circuit;
a current determining unit for determining a current value according to the voltage value and the resistance value of the target sub-processor;
and the power value determining unit is used for determining the power value of the target sub-processor according to the current value and the voltage value.
In some alternative embodiments, a power regulation module includes:
the first sub-processor determining unit is used for determining a first sub-processor from the plurality of sub-processors according to the power values of the sub-processors, wherein the first sub-processor is a sub-processor with the power value larger than a first power threshold;
the task merging unit is used for merging tasks on the first sub-processors with preset numbers into second sub-processors according to the power values of the first sub-processors; the sum of the power values of the first sub-processors with the preset number is smaller than a second power threshold, the preset number is related to the sum of the power values, and the second sub-processor is any one of the first sub-processors with the preset number.
In some alternative embodiments, a power regulation module includes:
a second sub-processor monitoring unit, configured to monitor power values of the plurality of sub-processors in real time, and when the second sub-processor is monitored from the plurality of sub-processors, allocate a task running on the second sub-processor to a third sub-processor; the second sub-processor is a sub-processor with a power value larger than a second power threshold, and the third sub-processor is a sub-processor with an available power value larger than or equal to the power value of the second sub-processor, and the second power threshold is larger than the first power threshold.
In some alternative embodiments, a power regulation module includes:
a request receiving unit, configured to, when a performance improvement request sent by an external user is received, perform power value measurement on a fourth sub-processor corresponding to the performance improvement request;
and the performance improving unit is used for improving the voltage value or the frequency value of the fourth sub-processor if the power value of the fourth sub-processor is smaller than the third power threshold value until the performance improving condition of the fourth sub-processor meets the requirement of the performance improving request.
In some optional embodiments, the buffer unit has a plurality of register interfaces corresponding to the plurality of sub-processors one by one, and the register interfaces are used for an external program to read power values of the corresponding sub-processors through the register interfaces.
In some alternative embodiments, the second power measurement module is disposed external to the multi-core processor; the apparatus further comprises:
and the second power measurement module is used for controlling the second power measurement module to carry out overall power measurement on the multi-core processor when the first power measurement module fails.
And the second power regulation and control module is used for regulating the working state of the multi-core processor according to the measured integral power value.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The embodiment of the invention also provides computer equipment, which is provided with the power regulation device of the multi-core processor shown in the figure 9.
Referring to fig. 10, fig. 10 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 10, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 10.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in implementing the above embodiments.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (10)
1. The power regulation and control method of the multi-core processor is characterized in that a first power measurement module is arranged in the multi-core processor and is respectively connected with a plurality of sub-processors in the multi-core processor; the method comprises the following steps:
measuring the power value of at least one sub-processor in real time through the first power measuring module;
and carrying out power regulation and control on the at least one sub-processor according to the power value.
2. The method of claim 1, wherein the first power measurement module comprises:
the control unit is used for issuing a measurement instruction to the power measurement unit when receiving a power measurement request sent by an external user; the measurement instruction comprises at least one target sub-processor; the target sub-processor is a sub-processor needing power measurement;
the power measurement unit is used for conducting a power measurement path corresponding to the target sub-processor according to the received measurement instruction, and the power measurement path is used for carrying out power measurement on the target sub-processor;
the cache unit is used for setting a plurality of sub-processor numbers corresponding to the plurality of sub-processors one by one and setting a plurality of cache queues corresponding to the plurality of sub-processor numbers one by one; the buffer queue is used for storing real-time power measurement values of the corresponding sub-processors.
3. The method of claim 2, wherein the power measurement path comprises a voltage sampling circuit;
measuring, by the first power measurement module, a power value of at least one sub-processor in real time, including:
acquiring a voltage value of a target sub-processor by using the voltage sampling circuit;
determining a current value according to the voltage value and the resistance value of the target sub-processor;
and determining the power value of the target sub-processor according to the current value and the voltage value.
4. The method according to claim 1 or 2, wherein power regulating the at least one sub-processor according to the power value comprises:
determining a first sub-processor from a plurality of sub-processors according to the power values of the sub-processors, wherein the first sub-processor is a sub-processor with the power value larger than a first power threshold;
combining tasks on a preset number of first sub-processors into a second sub-processor according to the power values of the plurality of first sub-processors; the sum of the power values of the first sub-processors with the preset number is smaller than a second power threshold, the preset number is related to the sum of the power values, and the second sub-processor is any one of the first sub-processors with the preset number.
5. The method according to claim 1 or 2, wherein power regulating the at least one sub-processor according to the power value comprises:
monitoring power values of the plurality of sub-processors in real time;
when a second sub-processor is monitored from the plurality of sub-processors, distributing tasks running on the second sub-processor to a third sub-processor;
the second sub-processor is a sub-processor with a power value larger than a second power threshold, and the third sub-processor is a sub-processor with an available power value larger than or equal to the power value of the second sub-processor, and the second power threshold is larger than the first power threshold.
6. The method according to claim 1 or 2, wherein power regulating the at least one sub-processor according to the power value comprises:
when a performance improvement request sent by an external user is received, measuring a power value of a fourth sub-processor corresponding to the performance improvement request;
and if the power value of the fourth sub-processor is smaller than the third power threshold, increasing the voltage value or the frequency value of the fourth sub-processor until the performance improvement condition of the fourth sub-processor meets the requirement of the performance improvement request.
7. The method according to claim 2, wherein the buffer unit has a plurality of register interfaces corresponding to the plurality of sub-processors one by one, and the register interfaces are used for an external program to read power values of the corresponding sub-processors through the register interfaces.
8. The method according to claim 1 or 2, wherein a second power measurement module is provided outside the multicore processor;
the method further comprises the steps of:
when the first power measurement module fails, controlling the second power measurement module to measure the overall power of the multi-core processor;
and adjusting the working state of the multi-core processor according to the measured integral power value.
9. A power regulation apparatus of a multi-core processor, the apparatus being applied to the power regulation method of a multi-core processor according to any one of claims 1 to 8, the apparatus comprising:
the first power measurement module is used for measuring the power value of at least one sub-processor in real time through the first power measurement module;
and the power regulation and control module is used for carrying out power regulation and control on the at least one sub-processor according to the power value.
10. A computer device, comprising:
a memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the power regulation method of the multi-core processor of any one of claims 1 to 8.
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