CN113517810B - Switching converter control system and method - Google Patents

Switching converter control system and method Download PDF

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Publication number
CN113517810B
CN113517810B CN202110836002.4A CN202110836002A CN113517810B CN 113517810 B CN113517810 B CN 113517810B CN 202110836002 A CN202110836002 A CN 202110836002A CN 113517810 B CN113517810 B CN 113517810B
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signal
voltage
pulse signal
converter control
switching converter
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CN113517810A (en
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王发刚
罗强
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On Bright Electronics Shanghai Co Ltd
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On Bright Electronics Shanghai Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Dc-Dc Converters (AREA)
  • Communication Control (AREA)

Abstract

The embodiment of the invention provides a switching converter control system and a switching converter control method. The system may be configured to derive a voltage signal based on a feedback voltage characterizing an output voltage of the system and a first reference voltage; obtaining a first pulse signal at a high level based on the voltage signal and a second reference voltage, wherein the high level time of the first pulse signal is a first time; and obtaining a clamping threshold value for clamping the voltage signal based on the first pulse signal, so that the system enters a closed-loop modulation mode from a low differential pressure mode within a first preset time period. According to the scheme, the voltage signal is obtained based on the feedback voltage, the pulse signal is obtained based on the voltage signal, and the clamping threshold is changed from the preset threshold to V based on the pulse signal SUM So that the voltage signal can be clamped to V rapidly SUM Therefore, the system can quickly enter a closed-loop modulation mode from a low dropout mode, and the problem of large output voltage ripple is prevented.

Description

Switching converter control system and method
Technical Field
Embodiments of the present invention generally relate to the field of integrated circuits, and in particular, to a switching converter control system and method.
Background
In general, high power buck converters used in automotive applications typically use dual N-Metal-Oxide-Semiconductor (NMOS) switching tubes as power stages for increasing power density, while it is desirable to allow the output voltage V of the system to achieve a wider range of input and output voltages OUT Close to its input voltage V IN That is, it is desirable to enable operation at 100% duty cycle. However, since the upper transistor is an NMOS switch transistor, the lower transistor needs to be turned on periodically to provide bootstrap capacitor C for the upper transistor BST Charging to satisfy the driving voltage V for the upper NMOS BST The requirements of (2). However, due to the periodic opening of the down tube, a 100% duty cycle cannot be achieved.
In the prior art, in order to solve the above problem, two schemes are generally adopted, the first scheme is to set a maximum duty ratio (for example, about 97%) for the system every cycle so that the output voltage V is output OUT The maximum can reach 97% V IN . In this way, the peak current mode buck converter system may operate in an open loop state, which falsely occursOutput voltage V of difference amplifier COMP Will reach an internal upper clamp value when the input voltage V is IN At the time of rising, due to the voltage V COMP Recovery is slower, resulting in a larger output voltage ripple (i.e., overshoot). In addition, the system still has a switching action every cycle, which causes switching loss and conduction loss.
The second scheme is that when the output voltage V is output OUT Close to the input voltage V IN In this case, the switching frequency of the system is reduced to further increase the equivalent duty ratio. In this way, switching losses and conduction losses can be reduced to a certain extent, but still present due to the input voltage V IN The output voltage ripple (i.e., overshoot) problem due to the increase, and the electromagnetic interference (EMI) problem due to the frequency variation in the electronic system of the vehicle.
In summary, the switching converter provided by the prior art cannot provide an output voltage with better ripple characteristics, higher efficiency, better EMI capability, and the like while achieving a 100% duty cycle.
Disclosure of Invention
The embodiment of the invention provides a switching converter control system and method, which are based on a feedback voltage V for representing the output voltage of a system FB To obtain a voltage signal V COMP Based on the voltage signal V COMP To obtain a PULSE signal PULSE based on which the clamping threshold of the upper clamping circuit in the switching converter control system is set from a preset threshold V CLP1 Becomes V SUM So that V is COMP Can be clamped to V rapidly SUM Therefore, the system can quickly enter a closed-loop modulation mode from a low dropout mode, and the problem of large output voltage ripple is prevented.
In a first aspect, embodiments of the present invention provide a switching converter control system, which may be configured to: obtaining a voltage signal based on a feedback voltage representing an output voltage of the switching converter control system and a first reference voltage; obtaining a first pulse signal at a high level based on the voltage signal and a second reference voltage, wherein the high level time of the first pulse signal is first time; and obtaining a clamping threshold value for clamping the voltage signal based on the first pulse signal, so that the switching converter control system can enter a closed-loop modulation mode from a low differential pressure mode within a first preset time period.
In a second aspect, an embodiment of the present invention provides a switching converter control method, which is applied to a switching converter control system, and the method may include: obtaining a voltage signal based on a feedback voltage characterizing an output voltage of the switching converter control system and a first reference voltage; obtaining a first pulse signal at a high level based on the voltage signal and a second reference voltage, wherein the high level time of the first pulse signal is a first time; and obtaining a clamping threshold value for clamping the voltage signal based on the first pulse signal, so that the switching converter control system can enter a closed-loop modulation mode from a low differential pressure mode within a first preset time period.
The switching converter control system and method provided by the embodiment of the invention can be based on the output voltage V for characterizing the system OUT Feedback voltage V of FB To obtain a voltage signal V COMP Based on the voltage signal V COMP To obtain a PULSE signal PULSE based on which the clamping threshold of the upper clamping circuit in the switching converter control system is set from a preset threshold V CLP1 Becomes V SUM So that V is COMP Can be clamped to V rapidly SUM Therefore, the system can quickly enter a closed-loop modulation mode from a low dropout mode, and the problem of large output voltage ripple is prevented.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram illustrating a configuration of a switching converter control system according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a specific implementation manner of a switching converter control system according to an embodiment of the present invention;
FIG. 3 is a waveform diagram illustrating the control timing of a switching converter control system according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a charge pump circuit provided in an embodiment of the present invention;
FIG. 5 is a schematic diagram of a floating voltage source according to an embodiment of the present invention; and
fig. 6 shows a flow chart of a switching converter control method according to an embodiment of the present invention.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.
It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
To solve one or more of the problems of the prior art, embodiments of the present invention provide a switching converter control system and method. First, a switching converter control system according to an embodiment of the present invention will be described.
As an example, fig. 1 shows a schematic structural diagram of a switching converter control system according to an embodiment of the present invention. As shown in fig. 1, the switching converter control system may include: diode D BST High side power tube M HS Low side power transistor M LS Bootstrap capacitor C BST And a feedback resistor R FB1 And R FB2 Inductor L1 and inductor current sampling resistor R SENSE A summing resistor R SUM And a compensation capacitor C COMP Zero setting resistor R COMP An output capacitor C OUT Current sampling amplifier A CS 1101. Slope compensation current I SLOPE 1102. Inverter 1103, and gate 1104, summing unit 1105, error amplifier 1106, PWM comparator 1107, low-dropout controller 1108, logic circuit 1109, top-clamp 1110, inverter 1111, driver 1112, driver 1113, floating-voltage source 1114, and charge pump 1115.
Wherein, the diode D BST May be connected to V DD Terminal, diode D BST May be connected to a first terminal of a floating voltage source 1114 and a first terminal of a driver 1113, the second terminal of the floating voltage source 1114 may be connected to a charge pump 1115, a third terminal of the floating voltage source 1114 may be connected to a second terminal of the driver 1113, the third terminal of the driver 1113 may be used for receiving a signal CTRL, and a fourth terminal of the driver 1113 may be connected to a high-side power transistor M HS Grid of (3), high side power transistor M HS Can be used for receiving the input voltage V of the system IN High side power tube M HS May be connected to the second terminal of the driver 1113, bootstrap capacitor C BST May be connected to the first terminal and the third terminal of the floating voltage source 1114, respectively, and the CTRL signal may be passed throughIs connected to the low side power tube M by an inverter 1111 and a driver 1112 LS Grid of (2), low side power transistor M LS Can be connected to the high side power transistor M HS And low side power transistor M, and LS can be connected to ground, a low-side power tube M LS May also be via an inductor L1 and an inductor current sampling resistor R SENSE Is connected to the output of the system via an output capacitor C OUT Connected to a reference ground and via a feedback resistor R FB1 And R FB2 Is connected to a reference ground.
And, a current sampling amplifier A CS Two input ends of 1101 can be respectively connected to the inductive current sampling resistor R SENSE At both ends of (A), a current sampling amplifier A CS An output terminal of 1101 may be connected to a first input terminal of a summing unit 1105, the ramp compensation current I SLOPE 1102 may be connected to a second input of the summing unit 1105 via a switch S1, wherein the switch S1 is turned on and off based on an output signal from the and gate 1104, one input of the and gate 1104 may be connected to the output of the inverter 1103 to receive the inverted PASS _ THRU, the other input may be used to receive the pulse width modulation signal PWM, and the output of the summing unit 1105 may be connected via a summing resistor R SUM Is connected to a reference ground.
One input (e.g., a non-inverting input) of the error amplifier 1106 may be used to receive a reference voltage V REF The other input (e.g., negative phase input) may be used to receive a feedback voltage V FB One input terminal (e.g., a non-inverting input terminal) of the PWM comparator 1107 may be connected to the summing resistor R SUM One end away from ground to receive the sum voltage V SUM The other input terminal (e.g., negative phase input terminal) of the PWM comparator 1107 may be connected to the output terminal of the error amplifier 1106 to receive the voltage V COMP The output of the PWM comparator 1107 may be coupled to a first input of the logic 1109, and the low dropout controller 1108 may be configured to receive the output voltage V of the system OUT Input voltage V of the system IN Reference voltage V REF2 And from error amplifier 1106Voltage V COMP And three outputs of the low dropout controller 1108 may be respectively connected to three inputs of the logic circuit 1109 to respectively provide the logic circuit 1109 with the PULSE signals ENTER, EXIT, and PASS _ THRU, the logic circuit 1109 may be configured to provide the signal CTRL, and further, a fourth output of the low dropout controller 1108 may be connected to a first input of the upper clamp circuit 1110 to provide the signal PULSE thereto, to control the clamping threshold of the upper clamp circuit 1110 based on the signal PULSE, and second and third inputs of the upper clamp circuit 1110 may be respectively configured to receive the signal V CLP1 And V SUM And for applying the voltage V based on the clamping threshold COMP Clamping is carried out.
As an example, a switching converter control system provided by an embodiment of the present invention may be used to: feedback voltage V based on output voltage characterizing the system FB And a reference voltage V REF An error amplifier 1106 may be utilized to output a voltage signal V COMP Based on the voltage signal V COMP And a reference voltage V REF2 The PULSE signal PULSE at high level can be output by the low dropout regulator 1108 and the logic circuit 1109, wherein the high level of the PULSE signal PULSE has a duration t DLY2 (see fig. 3), based on the PULSE signal PULSE, the clamp threshold of the upper clamp circuit 1110 is controlled so that the voltage signal V can be clamped with the clamp threshold COMP Clamping is performed to enable the system to quickly enter a closed loop modulation mode from a low dropout mode, preventing the system from being damaged by V COMP The slow voltage recovery leads to a large output voltage ripple (overshoot) problem.
It can be seen that by basing the voltage signal V COMP And a reference voltage V REF2 The PULSE signal PULSE at a high level is obtained, and the clamping threshold of the upper clamping circuit 1110 is set from the default V based on the PULSE signal PULSE CLP1 Becomes V SUM Obtaining V COMP Can be quickly clamped to V SUM So that the system can quickly enter a closed-loop modulation mode from a low dropout mode, and the problem of large output voltage ripple is prevented.
As an example, the switching converter control system provided by the embodiment of the present invention may be further configured to: based on a voltage signal V COMP And a reference voltage V REF2 The pulse signal EXIT at high level may be output by the low dropout controller 1108, wherein the high level of the pulse signal EXIT has a duration t DLY1 (see fig. 3), based on the PULSE signal EXIT, the PULSE signal PASS _ THRU may be changed from a high level to a low level by the logic circuit 1109, and based on the PULSE signal PASS _ THRU, the PULSE signal PULSE may be changed from a low level to a high level by the low dropout controller 1108, and the duration of the high level is t DLY2 (see FIG. 3).
As an example, the switching converter control system provided by the embodiment of the present invention may be further configured to: input voltage V based on the system IN And an output voltage V OUT The low dropout controller 1108 may be utilized to output a pulse signal ENTER at a high level, wherein the high level of the pulse signal ENTER has a duration t DLY1 (see fig. 3), based on the pulse signal ENTER, the logic circuit 1109 may be utilized to output the pulse signal PASS _ THRU at a high level, where the duration of the high level of the pulse signal PASS _ THRU may be different from t DLY1 And t DLY2 Causing the system to enter a low pressure differential mode.
For better understanding of the switching converter control system provided by the embodiment of the present invention, the switching converter control system is described in detail below with reference to fig. 2, and with reference to fig. 2, fig. 2 shows a schematic structural diagram of a specific implementation manner of the switching converter control system provided by an embodiment of the present invention, and the circuit structure shown in fig. 2 is a specific implementation manner of the switching converter control system shown in fig. 1.
As one example, as shown in FIG. 2, the low dropout controller 1108 may include a first branch, a second branch, and a third branch, where the first branch may be used for a system-based input voltage V IN And an output voltage V OUT To generate a pulse signal ENTER, a second branch may be used for generating a reference voltage V REF2 And from errorsVoltage signal V of amplifier 1106 COMP To generate the PULSE signal EXIT, and the third branch may be used to generate the PULSE signal PULSE based on the PULSE signal PASS _ THRU generated using the flip-flop Q2 based on the PULSE signal EXIT, to adjust the clamping threshold of the upper clamping circuit 1110 based on the PULSE signal PULSE.
In particular, the first branch may be used for the input voltage V IN And a multiple of the output voltage (e.g., 1.05 x v) OUT ) The comparison is carried out, and a series of logic operations are carried out on the comparison result to obtain a pulse signal ENTER, and the second branch can be used for carrying out reference voltage V REF2 Sum voltage signal V COMP The comparison is performed and a series of logical operations are performed on the comparison result to obtain the PULSE signal EXIT, and the third branch may be used to perform a series of logical operations on the PULSE signal PASS _ THRU to obtain the PULSE signal PULSE.
As an example, the first branch may include a comparator CMP1, an inverter, a delay module DLY1, an and gate, etc., wherein a first input (e.g., a non-inverting input) of the comparator CMP1 may be used to receive a multiple of an output voltage (e.g., 1.05 × v) OUT ) The second input (e.g., negative phase input) may be for receiving an input voltage V IN The comparator CMP1 can be used for comparing a certain multiple of the output voltage and the input voltage V IN The comparison is performed to generate a first comparison result, the output of the comparator CMP1 may be connected to an input of an inverter, the inverter may be configured to invert the first comparison result, the output of the inverter may be connected to a first input of the and gate via a delay block DLY1, the delay block DLY1 may be configured to delay the inverted first comparison result by a preset time t DLY1 (see fig. 3), a second input terminal of the and gate may be connected to an output terminal of the comparator CMP1, and the and gate may be used to logically and the first comparison result and the inverted and delayed first comparison result to output the pulse signal ENTER.
As an example, the second branch may comprise a comparator CMP2, an inverter, a delay module DLY1, and an and gate, etc., whereinThe first input terminal (e.g., non-inverting input terminal) of the comparator CMP2 may be used for receiving the reference voltage V REF2 The second input (e.g., negative phase input) may be for receiving the voltage signal V from the error amplifier COMP The comparator CMP2 can be used for comparing the reference voltage V REF2 Sum voltage signal V COMP The comparison is performed to generate a second comparison result, the output of the comparator CMP2 may be connected to an input of an inverter, the inverter may be configured to invert the second comparison result, the output of the inverter may be connected to the first input of the and gate via a delay block DLY1, the delay block DLY1 may be configured to delay the inverted second comparison result by a preset time t DLY1 (see fig. 3), a second input terminal of the and gate may be connected to the output terminal of the comparator CMP2, and the and gate may be used to perform a logical and operation on the second comparison result and the inverted and delayed second comparison result to output the pulse signal EXIT.
As one example, a first input terminal (e.g., a set terminal) of the flip-flop Q2 may be used to receive the pulse signal ENTER, and a second input terminal (e.g., a reset terminal) may be used to receive the pulse signal EXIT to generate the pulse signal PASS _ THRU based on the pulse signals ENTER and EXIT.
As an example, the third branch may include a delay module DLY2, an inverter, an and gate, etc., wherein the output terminal of the flip-flop Q2 may be connected to the first input terminal of the and gate via the delay module DLY2, and the delay module DLY2 may be used to delay the pulse signal PASS _ THRU by the preset time t DLY2 To provide the delayed PULSE signal to the and gate, the output terminal of the flip-flop Q2 may be further connected to the second input terminal of the and gate via an inverter to provide the inverted PULSE signal to the and gate, so that the and gate may perform a logical and operation on the delayed PULSE signal and the inverted PULSE signal to generate the PULSE signal PULSE at a high level, and thus may set the clamping threshold of the upper clamping circuit 1110 from a preset V when the PULSE signal PULSE is at a high level CLP1 Becomes V SUM So that V is COMP Is rapidly clamped to V SUM The value of (c).
As an example, the current sampling resistor R SENSE And a current sampling amplifier A CS 1101 may be used to sample the current in inductor L1 and thereby convert it to a current I proportional to the inductor current SENSE 。
As an example, the summing resistor R SUM Can be used to compensate the current I for the slope SLOPE And a sampling current I SENSE Superpositioning and generating a ramp voltage V that can be used to characterize the inductor current signal SUM Wherein the ramp voltage V SUM Can be used as a clamping threshold for the upper clamp 1110 to keep the clamping threshold of the upper clamp 1110 from a preset threshold (e.g., V) when the system enters the closed-loop modulation mode from the low dropout mode CLP1 ) Is changed into a ramp voltage V SUM Using a threshold value V SUM To voltage signal V COMP Clamping is performed, and another clamping threshold of the upper clamping circuit 1110 is a preset threshold (e.g., V) CLP1 ) For using the threshold V when the system is in the low differential pressure mode and the closed loop modulation mode CLP1 To the voltage signal V COMP Clamping is performed so that the voltage signal V COMP Does not exceed a threshold value V CLP1 。
As an example, PWM comparator 1107 may be used to compare the ramp voltage V SUM Sum voltage signal V COMP The comparison is performed and a switching control signal CMP _ OUT having a duty ratio adjusting function is generated.
As an example, when the low side power transistor M LS Always turned off due to bootstrap capacitance C BST It cannot be charged, in which case the floating voltage source 1114 can be used to bootstrap the capacitor C BST Charging is carried out so as to generate a power tube M which can be used for high-side power HS Voltage V of the driving supply BST So that the high side power tube M HS Can be always on.
As one example, the charge pump circuit 1115 may be used to generate the voltage V CP To power the floating voltage source 1114, where the voltage V CP Usually higher than the input voltage V IN E.g. to the input voltage V IN About 5V higher.
As one example, the low dropout controller 1108 may be used to control the loop to enter and exit a low dropout mode, where after entering the low dropout mode, the pulse signal PASS _ THRU changes from a low level to a high level, and the signal CTRL changes to a high level, causing the high side power tube M to respond to the signal CTRL being at the high level HS Is always conducted and the low side power tube M LS Is always turned off, when the low dropout mode is exited, the PULSE signal PASS _ THRU changes from a high level to a low level, and generates a PULSE signal PULSE, the high level of the PULSE signal PULSE has the time t DLY2 The PULSE signal PULSE may be used to control the clamping threshold of the upper clamping circuit 1110, for example, when the PULSE signal PULSE is at a high level, the clamping threshold of the upper clamping circuit 1110 may be from a preset clamping threshold V CLP1 Becomes V SUM 。
As one example, upper clamp 1110 may be used to clamp the output voltage V from error amplifier 1106 COMP Clamping, e.g., using the clamping threshold V of the upper clamp 1110 when the switching converter control system is in the low dropout mode and the closed loop modulation mode CLP1 To the output voltage V of the error amplifier 1106 COMP Clamping is performed so that the voltage signal V COMP When the switching converter control system enters the closed-loop modulation mode from the low dropout mode, the clamping threshold of the upper clamping circuit 1110 is not exceeded VCLP1, and the clamping threshold is changed from V based on the PULSE signal PULSE CLP1 Becomes V SUM So that the clamping threshold V of the upper clamping circuit 1110 can be utilized SUM To the voltage signal V of the error amplifier 1106 COMP Clamping is performed so that the voltage signal V COMP Is rapidly clamped to a clamping threshold V SUM The value of (c).
The control principle of the switching converter control system is described in detail below by way of example with reference to fig. 2.
As an example, when the input voltage V IN Greater than 1.05 x V OUT When the system is operating in the closed loop modulation Mode (Regulation Mode), the pulse signal PASS _ THRU is at a low level, and the signal CTRL can be setControlled by a pulse width modulation signal PWM. At each rising edge of CLK, the PWM signal is high, the high side power transistor M HS Starts to conduct to make the resistor R SUM Voltage V on SUM Begins to rise when the PWM comparator 1107 detects a ramp voltage V SUM Greater than voltage signal V COMP When the voltage signal CMP _ OUT is at high level, the trigger Q1 receives the voltage signal CMP _ OUT and outputs the pulse width modulation signal PWM at low level, and the high-side power tube M HS Starting to turn off, low side power transistor M LS Conduction is started. In this way, the output voltage V OUT The set stable voltage value is reached.
As an example, with input voltage V IN Gradually decreasing (or Soft Start) output voltage V during the system OUT Gradually increasing) when the input voltage V is applied IN Output voltage less than a multiple (e.g., 1.05 x V) OUT ) When the system enters a low dropout mode, the pulse signal PASS _ THRU changes from a low level to a high level, and the signal CTRL changes to a high level, so that the high-side power tube M HS Can be always conducted, and the low-side power tube M LS It may be turned off all the time. However, due to the low side power transistor M LS Is always turned off, resulting in a bootstrap capacitor C BST Charging is not possible, in which case embodiments of the invention may employ, for example, floating voltage source 1114 to bootstrap capacitor C BST Charging is carried out so as to generate a power tube M which can be used for high-side power HS Voltage V of the driving supply BST So that the high side power tube M HS Can be always on. In addition, embodiments of the invention may employ a charge pump circuit 1115 to generate the voltage V CP To power the floating voltage source 1114. After the system enters the low dropout mode, the output voltage V of the error amplifier 1106 COMP Will gradually go high, in which case embodiments of the present invention may employ upper clamp 1110 to clamp voltage signal V COMP Clamping at a default clamping threshold V CLP1 In the vicinity of (a).
As one example, in the low dropout mode, the ramp compensation current signal is turned off based on the pulse signal PASS _ THRU, specifically, at the pulseWhen the signal PASS _ THRU becomes high, the switch S may be adopted in the embodiment of the present invention 1 To turn off the slope compensation current to prevent the resistor R SUM Voltage V above SUM At the high side power tube M HS And continuously rises when conducting. Wherein the inverter 1103 may be used to invert the pulse signal PASS _ THRU, and the and gate 1104 may be used to logically and the inverted pulse signal and the pulse width modulation signal PWM, and control the switch S based on an output signal from the and gate 1104 1 Can be switched on and off, for example by switching off the switch S 1 To turn off the slope compensation current I SLOPE Or by closing switch S 1 The ramp compensation current is turned on.
As an example, when the input voltage V IN When gradually increasing, the output voltage V is still in the low-voltage-difference mode because the control system of the switching converter works OUT With input voltage V IN Is increased due to the feedback voltage V FB Is used to characterize the output voltage V OUT So that the feedback voltage V FB With output voltage V OUT Is increased when the error amplifier 1106 detects the feedback voltage V FB Begins to be greater than V REF The output voltage V of the error amplifier 1106 COMP Will gradually decrease when the comparator CMP2 detects the voltage signal V COMP Less than reference voltage V REF2 When the system exits the low dropout mode, the pulse signal PASS _ THRU changes from high level to low level, and the control signal CTRL is controlled by the pulse width modulation signal PWM.
Next, the system returns to the closed-loop modulation mode, and generates a PULSE signal PULSE at a high level for a duration t when the PULSE signal PASS _ THRU changes from a high level to a low level DLY2 The signal PULSE may be used to control the clamping threshold of the upper clamping circuit 1110, for example, when the PULSE signal PULSE is at a high level, so that the clamping threshold of the upper clamping circuit 1110 is from a preset threshold V CLP1 Becomes V SUM So that the voltage signal V COMP Can be quickly clamped to the threshold value V SUM In this way, the system can be operated in a sufficiently short timeThe internal voltage is quickly switched from the low-dropout mode to the closed-loop modulation mode, so that the ripple of the output voltage of the system caused by mode switching can be reduced.
For further understanding of the switching converter control system provided by the embodiment of the present invention, the operation mode of the switching converter control system is described below with reference to fig. 2 and fig. 3, for example, fig. 3 is a waveform diagram illustrating the control timing of the switching converter control system provided by the embodiment of the present invention.
Referring to fig. 3, as an example, a waveform diagram of a corresponding signal of the system during switching from a soft start (modulation mode) to a low dropout mode and back to a modulation mode is shown.
At time t1, when the comparator CMP1 detects the input voltage V IN Greater than 1.05 x V OUT When the comparator CMP1 outputs a low level, the system starts a soft start, and the output voltage V is set OUT Is modulated by the system to rise with a preset slope.
With the rise of the output voltage, at time t2, when the comparator CMP1 detects the input voltage V IN Less than 1.05V OUT When the output of the comparator CMP1 changes from low level to high level, the pulse width t is generated by performing a series of logical operations (for example, logical operations using logic cells in the first branch) on the comparison result from the comparator CMP1 DLY1 And the pulse signal ENTER is input to one end (e.g., a set end) of the RS flip-flop Q2, the pulse signal PASS _ THRU is changed from a low level to a high level by the RS flip-flop Q2, and the system ENTERs a low dropout mode.
At time t3, the input voltage V IN Begins to increase gradually because the high side power tube M HS Is always in the on state, so that the output voltage V OUT With input voltage V IN Due to the feedback voltage V FB Is to the output voltage V OUT Obtained by sampling, so that the feedback voltage V FB With the output voltage V OUT Is increased when the error amplifier 1106 detects the feedback voltage V FB Starts to be greater than a reference voltage V REF Time, output voltage signal V COMP And begins to fall.
At time t4, when the comparator CMP2 detects the voltage signal V COMP Down to a reference voltage V REF2 When the output of the comparator CMP2 is made high, the pulse width t is generated by performing a series of logical operations (for example, logical operations using a logic cell in the second branch) on the comparison result from the comparator CMP2 DLY1 And inputs the pulse signal EXIT to the other end (e.g., reset end) of the RS flip-flop Q2, the pulse signal PASS _ THRU is changed from high level to low level by the RS flip-flop Q2, so that the system EXITs the low dropout mode and enters the closed loop modulation mode. After the PULSE signal PASS _ THRU changes to the low level, the PULSE signal PULSE is caused to change from the low level to the high level and has a PULSE width t DLY2 When the PULSE signal PULSE is at a high level, the clamping threshold of the upper clamping circuit 1110 is made to be from the preset threshold V CLP1 Becomes V SUM So that V is COMP Is rapidly clamped to V SUM The value of (c).
At time t5, the PULSE signal PULSE changes from high level to low level, and when the PULSE signal PULSE is at low level, the clamping threshold of the upper clamping circuit 1110 is made to change from V SUM Is restored to the preset threshold value V CLP1 To use a preset threshold value V CLP1 To the voltage signal V COMP Is clamped such that the voltage signal V COMP Does not exceed a threshold value V CLP1 Wherein the voltage signal V COMP Can be controlled by the load of the system and the input voltage V IN And an output voltage V OUT To be determined.
As an example, fig. 4 shows a schematic structural diagram of a charge pump circuit provided in an embodiment of the present invention. As shown in FIG. 4, the charge pump circuit may include a transistor M 1 -M 5 Capacitors C1-C2, resistor R 1 -R 2 And non-overlapping logic, etc.
Wherein, the transistor M 1 Can be used to receive a voltage V DD ，M 1 May be connected to its source, M 1 May also be connected to the transistor M 2 Drain electrode of (D), M 2 Can be connected to its source, M 2 May be connected to a reference ground via a capacitor C2, and an end of the capacitor C2 remote from ground may be used as an output terminal of the charge pump circuit, M 3 May be connected to a reference ground, M 3 May be connected to an output of the non-overlap logic to receive signals CLK _ a, M therefrom 3 May be connected to M 4 Drain electrode of, M 4 Can be connected via a resistor R 1 A drain connected to M5, M 4 Can be used for receiving a voltage V IN Resistance R 2 Is connected at M 4 Between the gate and the source of (C), M 5 May be connected to a reference ground, M 5 May be connected to another output terminal of the non-overlap logic to receive a signal CLK _ b therefrom, and one terminal of the capacitor C1 may be connected to M 3 The other end of the capacitor C1 may be connected to M 1 Source and M 2 Of the substrate.
As an example, the charge pump circuit may be configured to generate signals CLK _ a and CLK _ b inverted with respect to each other by Non-overlapping logic (Non-overlapping logic), and may charge the capacitor C1 when the signal CLK _ a is at a high level and set a lower plate voltage of the capacitor C1 to an input voltage V when the signal CLK _ b is at a high level IN And charges the capacitor C2 through the capacitor C1 to generate a voltage V CP To supply a floating voltage source, the voltage V CP Can be compared with input voltage V IN E.g., about 5V high.
In particular, non-overlap logic may be used to generate mutually inverted signals CLK _ a and CLK _ b based on the clock signal CLK _ cp, such that M is asserted when the signal CLK _ a is high 3 Conducting, at this time, using voltage V DD By M 1 To charge the capacitor C1; when the signal CLK _ b is high, M is asserted 5 Is turned on due to M 5 So that M is turned on 4 Is also conducted through M 4 And M 5 Is conducted to set the lower plate voltage of the capacitor C1 to V IN Since the voltage difference between the two ends of the capacitor can not be suddenly changed, the capacitor C1 can be utilized to pass through M 2 The body diode of (1) charges the capacitor C2, and the voltage V on the capacitor C2 is enabled to pass through a plurality of clock cycles CP Becomes V IN +V DD -2V DIO Wherein V is DIO Is the voltage of the body diode.
As an example, fig. 5 shows a schematic structural diagram of a floating voltage source provided by an embodiment of the present invention. As shown in FIG. 5, the floating voltage source may include an operational amplifier OP, a transistor M 5 -M 9 Resistance R REF1 -R REF2 And R 3 And a Zener tube Z1.
Wherein M is 5 And M 6 Constituting a current mirror circuit, one input (e.g., a non-inverting input) of the operational amplifier OP may be used for receiving the reference voltage V REF3 The other input (e.g., negative phase input) may be connected to M 9 The output terminal of the operational amplifier OP may be connected to M 9 Grid electrode of (M) 9 Via a resistor R REF1 Connected to reference ground, M 9 May be connected to a first terminal of the current mirror circuit, and a second terminal of the current mirror circuit may be connected to M 7 Drain electrode of, M 7 May also be connected to M 7 Of the grid electrode, M 7 Can be connected via a resistor R REF2 Is connected to a zener tube Z 1 One end of, M 8 Can be connected via a resistor R 3 Connected to a third terminal of the current mirror circuit, M 8 May be connected to M 7 Grid electrode of (M) 8 May be connected to the zener diode Z 1 And the other end of the zener diode Z1 may be used as an output terminal of the floating voltage source.
As an example, when the low side power transistor M LS Always off due to bootstrap capacitance C BST It cannot be charged, in which case the floating voltage source 1114 can be used to bootstrap the capacitor C BST Charging is carried out, which can be generated for the high-side power tube M HS Voltage V of the driving supply BST So that the high side power tube M HS Can be always on.
In particular, by means of operational amplifiers OP and M 9 And M 5 Based on a reference voltage V REF3 Can produce a size V REF3 /R REF1 Current of (I) 1 If M is 6 And M 5 Is equal to the width-to-length ratio of 2 Is equal to I 1 ，M 7 Can be used to generate a target for M 8 Such that the output voltage V of the floating voltage source is BST -V SW Is approximately equal to V REF3 /R REF1* R REF2 Z is a Zener pipe 1 Can be used for the pair V BST -V SW Voltage clamping is performed.
Referring to fig. 6, fig. 6 shows a flowchart of a switching converter control method provided by an embodiment of the present invention, where the method is applied to a switching converter control system, and the method may include the following steps: s610, based on a feedback voltage (e.g., V) characterizing an output voltage of a switching converter control system FB ) And a first reference voltage (e.g., V) REF ) Obtaining a voltage signal (e.g., V) COMP ) (ii) a S620, based on the voltage signal and a second reference voltage (e.g., V) REF2 ) Obtaining a first PULSE signal (e.g., PULSE) at a high level, wherein the high level time of the first PULSE signal is a first time; and S630, obtaining a clamping threshold value for clamping the voltage signal based on the first pulse signal, so that the switching converter control system can enter a closed-loop modulation mode from a low differential pressure mode within a first preset time period.
As an example, deriving the first pulse signal at the high level based on the voltage signal and the second reference voltage may further include: obtaining a second pulse signal (e.g., EXIT) at a high level based on the voltage signal and a second reference voltage, wherein a high level time of the second pulse signal is a second time; obtaining a third pulse signal (e.g., PASS _ THRU) at a low level based on the second pulse signal; and deriving a first PULSE signal (e.g., PULSE) at a high level based on the third PULSE signal.
As an example, deriving the second pulse signal at the high level based on the voltage signal and the second reference voltage may further include: comparing the voltage signal with a second reference voltage to obtain a first comparison signal; inverting the first comparison signal to obtain an inverted first comparison signal; delaying the inverted first comparison signal by a first preset time to obtain an inverted and delayed first comparison signal; and performing logical AND operation on the first comparison signal and the inverted and delayed first comparison signal to obtain a second pulse signal at a high level.
As an example, deriving the first pulse signal at the high level based on the third pulse signal may further include: delaying the third pulse signal for a second preset time to obtain a delayed third pulse signal; inverting the third pulse signal to obtain an inverted third pulse signal; and performing logical AND operation on the delayed third pulse signal and the inverted third pulse signal to obtain a first pulse signal at a high level.
As an example, the method may further comprise: obtaining a fourth pulse signal (e.g., ENTER) at a high level based on the input voltage and the output voltage of the switching converter control system, wherein the high level time of the fourth pulse signal is a second time; and deriving a third pulse signal (e.g., PASS _ THRU) at a high level based on the fourth pulse signal, wherein a high level time of the third pulse signal is a third time, so that the switching converter control system enters a low dropout mode.
As an example, the clamping threshold may include a first threshold and a second threshold, the first threshold is a preset threshold, and the method may further include obtaining the second threshold by: sampling current flowing through an inductor in a switch converter control system to obtain a current characterization signal for characterizing the inductor current; receiving a slope compensation current signal; and obtaining a second threshold value based on the current characterization signal and the slope compensation current signal.
As an example, the method may further comprise: in the low dropout mode, the slope compensation current signal is turned off based on the third pulse signal, and the second threshold value is prevented from continuously rising when a high-side power tube in the switching converter control system is conducted.
As an example, the method may further comprise: when the switching converter control system is in a low-dropout mode and a closed-loop modulation mode, enabling the clamping threshold value to be a first threshold value so that the voltage signal does not exceed the first threshold value; and when the switching converter control system enters the closed-loop modulation mode from the low dropout mode, enabling the clamping threshold value to be a second threshold value, so that the voltage signal is clamped to the second threshold value within a second preset time period.
As one example, the switching converter control system includes a floating voltage source, and the method may include: when a low-side power tube in the switch converter control system is always in an off state, the floating voltage source is utilized to charge a bootstrap capacitor in the switch converter control system so as to generate a driving voltage aiming at a high-side power tube in the switch converter control system, so that the high-side power tube can be always in an on state.
As one example, the switching converter control system may further include a charge pump circuit, and the method may include: generating a first clock signal and a second clock signal that are inverted with respect to each other by non-overlapping logic in a charge pump circuit; when the first clock signal is at a high level, charging a first capacitor in the charge pump circuit; when the second clock signal is at a high level, setting the voltage of the lower plate of the first capacitor as the input voltage of the switching converter control system; and charging a second capacitor in the charge pump circuit by using the first capacitor to generate a supply voltage for the floating voltage source.
It should be noted that the details of the switching converter control method provided by the embodiment of the present invention are similar to those described above with reference to fig. 1 to 5, and for simplifying the description, the details are not repeated herein.
It is to be understood that the invention is not limited to the specific arrangements and instrumentality described above and shown in the drawings. A detailed description of known methods is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present invention are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications and additions or change the order between the steps after comprehending the spirit of the present invention.
The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the invention are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranet, etc.
It should also be noted that the exemplary embodiments mentioned in this patent describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed at the same time.
As described above, only the specific embodiments of the present invention are provided, and it can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present invention, and these modifications or substitutions should be covered within the scope of the present invention.

Claims (13)

1. A switching converter control system, characterized in that the switching converter control system is configured to:
obtaining a voltage signal based on a feedback voltage characterizing an output voltage of the switching converter control system and a first reference voltage;
obtaining a first pulse signal at a high level based on the voltage signal and a second reference voltage, wherein the high level time of the first pulse signal is a first time; and
obtaining a clamping threshold value for clamping the voltage signal based on the first pulse signal, so that the switching converter control system can enter a closed-loop modulation mode from a low differential pressure mode within a first preset time period; wherein the clamping threshold comprises a first threshold and a second threshold, the first threshold is a preset threshold, and the switching converter control system is further configured to:
sampling current flowing through an inductor in the switch converter control system to obtain a current characterization signal for characterizing the inductor current;
receiving a slope compensation current signal; and
obtaining the second threshold value based on the current characterization signal and the slope compensation current signal;
when the switching converter control system enters the closed-loop modulation mode from the low dropout mode, the clamping threshold is made to be the second threshold, so that the voltage signal is clamped to the second threshold within a second preset time period.
2. The switching converter control system of claim 1, further configured to:
obtaining a second pulse signal at a high level based on the voltage signal and the second reference voltage, wherein the high level time of the second pulse signal is a second time;
obtaining a third pulse signal at a low level based on the second pulse signal; and
and obtaining the first pulse signal at a high level based on the third pulse signal.
3. The switching converter control system of claim 2, further configured to:
comparing the voltage signal with the second reference voltage to obtain a first comparison signal;
inverting the first comparison signal to obtain an inverted first comparison signal;
delaying the inverted first comparison signal for a first preset time to obtain an inverted and delayed first comparison signal; and
and performing logical AND operation on the first comparison signal and the inverted and delayed first comparison signal to obtain the second pulse signal at a high level.
4. The switching converter control system of claim 2, further configured to:
delaying the third pulse signal for a second preset time to obtain a delayed third pulse signal;
inverting the third pulse signal to obtain an inverted third pulse signal; and
and performing logical AND operation on the delayed third pulse signal and the inverted third pulse signal to obtain the first pulse signal at a high level.
5. The switching converter control system of claim 2, further configured to:
obtaining a fourth pulse signal at a high level based on the input voltage and the output voltage of the switching converter control system, wherein the high level time of the fourth pulse signal is the second time; and
and obtaining the third pulse signal at a high level based on the fourth pulse signal, wherein the high level time of the third pulse signal is a third time, so that the switching converter control system enters the low dropout mode.
6. The switching converter control system of claim 2, further configured to:
in the low dropout mode, the slope compensation current signal is turned off based on the third pulse signal, and the second threshold is prevented from continuously rising when a high-side power tube in the switching converter control system is turned on.
7. The switching converter control system of claim 1, further configured to:
when the switching converter control system is in the low-dropout mode and the closed-loop modulation mode, the clamping threshold is made the first threshold so that the voltage signal does not exceed the first threshold.
8. The switching converter control system of claim 1, comprising a floating voltage source to:
when a low-side power tube in the switching converter control system is always in an off state, a bootstrap capacitor in the switching converter control system is charged to generate a driving voltage for a high-side power tube in the switching converter control system, so that the high-side power tube can be always in an on state.
9. The switching converter control system of claim 8, further comprising a charge pump circuit to:
generating, by non-overlapping logic in the charge pump circuit, a first clock signal and a second clock signal that are inverted with respect to each other;
charging a first capacitor in the charge pump circuit when the first clock signal is at a high level;
when the second clock signal is at a high level, setting the lower plate voltage of the first capacitor as the input voltage of the switching converter control system; and
and charging a second capacitor in the charge pump circuit by using the first capacitor so as to generate a supply voltage for the floating voltage source.
10. A switching converter control method is applied to a switching converter control system, and is characterized by comprising the following steps:
obtaining a voltage signal based on a feedback voltage representing an output voltage of the switching converter control system and a first reference voltage;
obtaining a first pulse signal at a high level based on the voltage signal and a second reference voltage, wherein the high level time of the first pulse signal is first time; and
obtaining a clamping threshold value for clamping the voltage signal based on the first pulse signal, so that the switching converter control system can enter a closed-loop modulation mode from a low differential pressure mode within a first preset time period; wherein the clamping threshold comprises a first threshold and a second threshold, the first threshold is a preset threshold, and the switching converter control method further comprises:
sampling current flowing through an inductor in the switch converter control system to obtain a current characterization signal for characterizing the inductor current;
receiving a slope compensation current signal; and
obtaining the second threshold value based on the current characterization signal and the slope compensation current signal;
when the switching converter control system enters the closed-loop modulation mode from the low dropout mode, the clamping threshold is set to the second threshold, so that the voltage signal is clamped to the second threshold within a second preset time period.
11. The switching converter control method according to claim 10, further comprising:
obtaining a second pulse signal at a high level based on the voltage signal and the second reference voltage, wherein the high level time of the second pulse signal is a second time;
obtaining a third pulse signal at a low level based on the second pulse signal; and
and obtaining the first pulse signal at a high level based on the third pulse signal.
12. The switching converter control method according to claim 11, further comprising:
obtaining a fourth pulse signal at a high level based on the input voltage and the output voltage of the switching converter control system, wherein the high-level time of the fourth pulse signal is the second time; and
and obtaining the third pulse signal at a high level based on the fourth pulse signal, wherein the high-level time of the third pulse signal is a third time, so that the switching converter control system enters the low dropout mode.
13. The switching converter control method according to claim 11, further comprising:
in the low dropout mode, turning off the slope compensation current signal based on the third pulse signal prevents the second threshold from continuously increasing when a high-side power tube in the switching converter control system is turned on.
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