CN113517227A - Semiconductor device and method of forming a semiconductor transistor device - Google Patents

Semiconductor device and method of forming a semiconductor transistor device Download PDF

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Publication number
CN113517227A
CN113517227A CN202110296192.5A CN202110296192A CN113517227A CN 113517227 A CN113517227 A CN 113517227A CN 202110296192 A CN202110296192 A CN 202110296192A CN 113517227 A CN113517227 A CN 113517227A
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source
drain
drain epitaxial
backside
forming
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CN202110296192.5A
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CN113517227B (en
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苏焕杰
庄正吉
王志豪
林志昌
游力蓁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US17/068,037 external-priority patent/US11581224B2/en
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

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Abstract

A method of forming a semiconductor transistor device. The method includes forming a fin-shaped channel structure over a substrate, and forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite ends of the fin structure. The method also includes forming a metal gate structure surrounding the fin structure. The method also includes flipping and partially removing the substrate to form a backside capped trench while leaving a lower portion of the substrate as a protective spacer along upper sidewalls of the first and second source/drain epitaxial structures. The method also includes forming a backside dielectric cap in the backside cap trench. Embodiments of the present application also relate to semiconductor devices.

Description

Semiconductor device and method of forming a semiconductor transistor device
Technical Field
Embodiments of the present application relate to semiconductor devices and methods of forming semiconductor transistor devices.
Background
The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in multiple generations of ICs, each of which has smaller and more complex circuits than the previous generation. In the course of IC development, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component (or line) that can be fabricated using the fabrication process) has decreased. Such a scale-down process generally results in benefits by improving production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing the IC.
Disclosure of Invention
Some embodiments of the present application provide a method of forming a semiconductor transistor device, the method comprising: forming a fin-shaped channel structure above a substrate; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite ends of the fin-shaped channel structure; forming a metal gate structure around the fin-shaped channel structure; partially removing the substrate from a backside of the substrate to form a backside cap trench while leaving a lower portion of the substrate as a protective spacer along upper sidewalls of the first and second source/drain epitaxial structures; and forming a backside dielectric cap in the backside cap trench.
Further embodiments of the present application provide a method of forming a semiconductor transistor device, the method comprising: forming a fin-shaped channel structure above a substrate; forming a sacrificial source/drain contact in the substrate on one side of the fin-shaped channel structure; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite ends of the fin-shaped channel structure, the first source/drain epitaxial structure being located over the sacrificial source/drain contact; forming a metal gate structure around the fin-shaped channel structure; turning over and thinning the substrate; forming a protective spacer along upper sidewalls of the first and second source/drain epitaxial structures; forming a backside cap trench to expose a bottom surface of the metal gate structure and a bottom surface of the second source/drain epitaxial structure, wherein the bottom surface of the second source/drain epitaxial structure is recessed; and forming a backside dielectric cap in the backside cap trench.
Still further embodiments of the present application provide a semiconductor device including: a channel structure; the grid structure wraps the channel structure; a first source/drain epitaxial structure and a second source/drain epitaxial structure disposed on opposite ends of the channel structure; a gate contact disposed on the gate structure; a backside source/drain contact disposed below and in contact with the first source/drain epitaxial structure; and a backside dielectric cap disposed below and extending along the second source/drain epitaxial structure and the gate structure; wherein a bottom surface of the first source/drain epitaxial structure has a concave shape.
Drawings
Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 illustrates a perspective view of some embodiments of a semiconductor transistor device having recessed source/drain regions.
Fig. 2 illustrates a cross-sectional view of some additional embodiments of the semiconductor transistor device taken along line a-a' of fig. 1.
Fig. 3 is a cross-sectional view of some embodiments of a semiconductor transistor device taken along line B-B' of fig. 1.
Fig. 4 is a cross-sectional view of some embodiments of a semiconductor transistor device taken along line C-C of fig. 1.
Fig. 5 is a cross-sectional view of some embodiments of a semiconductor transistor device taken along line D-D' of fig. 1.
Fig. 6-33B illustrate various views of some embodiments of a method of forming a semiconductor transistor device having recessed source/drain regions at different stages.
Fig. 34 illustrates a flow diagram corresponding to some embodiments of the method of fig. 6-33B.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting of the invention. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first feature is in direct contact with the second feature, as well as embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, "about," "approximately," or "substantially" generally refers to within 20%, or within 10%, or within 5% of a given value or range. The numerical values set forth herein are approximations that may vary depending upon the particular circumstances involved, i.e., the terms "about," "approximately," or "substantially" are intended to be inferred if not expressly stated.
The Gate All Around (GAA) transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine lithography with self-aligned processes, allowing for the creation of patterns with, for example, pitches smaller than would otherwise be obtained using a single direct lithography. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers can then be used to pattern the GAA crystal pole structure. After forming the GAA transistor structure, an interconnect structure may be formed thereon, including a power rail and a signal line disposed within an interlayer dielectric (ILD) layer.
As semiconductor processing continues to scale, e.g., beyond 3 nanometers, current power rail designs suffer from complex metal layer routing in back end of line (BEOL). Due to the complex metal layer routing, more masks are required, and the voltage drop (also called IR-drop) is affected when the metal lines are thinned.
In view of the foregoing, the present invention relates to a semiconductor transistor device having a backside power rail and a method of manufacturing the same. By moving the power supply rails from the front side to the back side of the semiconductor transistor device, the metal layer wiring in the BEOL is released. Thus, the number of masks required is reduced, the IR drop is improved, and both the power rail area and the active area can be enlarged.
More particularly, the present invention relates to semiconductor transistor devices having backside power rails and recessed source/drain regions and methods of fabricating the same. In some embodiments, a semiconductor transistor device includes a channel structure, a gate structure surrounding the channel structure, first and second source/drain epitaxial structures disposed at opposite ends of the channel structure, and a gate contact disposed on the gate structure. The semiconductor transistor device also includes a backside source/drain contact bonded on the recessed bottom surface of the first source/drain epitaxial structure, and a backside power rail disposed below and connected to the backside source/drain contact. The backside source/drain contacts and the backside power rail may, for example, comprise a metallic material. In some embodiments, a bottom surface of the first source/drain epitaxial structure may be recessed to a position vertically deeper than a bottom surface of the gate structure or the channel structure.
In some embodiments, the bottom surface of the second source/drain epitaxial structure may also be recessed to a position vertically deeper than the bottom surface of the gate structure or the channel structure. The recess of the second source/drain epitaxial structure is lower and therefore farther from the backside power rail. Thus, time dependent dielectric breakdown between the second source/drain epitaxial structure and the backside power rail may be eliminated. In addition, the backside dielectric cap may also replace the original semiconductor body material and contact the bottom surfaces of the gate structure and the second source/drain epitaxial structure. The backside dielectric cap may comprise an oxide, nitride, carbon nitride, or low-k dielectric material. Thus, cell capacitance can be reduced and current problems, such as leakage between the gate structure and the backside source/drain contacts, can be eliminated.
In some other embodiments, methods of forming semiconductor transistor devices involve utilizing protective spacers when recessing the bottom surface of the second source/drain epitaxial structure. When devices of different sizes need to be formed simultaneously, there is a loading effect between the short channel transistor device and the long channel transistor device. As a result of the loading effect, the source/drain regions and/or other epitaxial structures may be formed to different depths. This depth difference would make it difficult to remove the substrate, recess the bottom surfaces of the source/drain regions, and then cover the backside dielectric caps for the short channel transistor devices and the long channel transistor devices: leaving substrate residue can lead to leakage and complete removal can damage the epitaxial structure of the long channel transistor device. The protective spacer may cover the trench by partially removing the substrate to form a backside while leaving a lower portion of the substrate along upper sidewalls of the first source/drain epitaxial structure and the second source/drain epitaxial structure. The protective spacer may then be removed when recessing the first source/drain epitaxial structure and forming the backside source/drain contacts. These components are also described below in connection with the figures as some exemplary embodiments.
The semiconductor transistor devices presented herein may include p-type GAA devices or n-type GAA devices. Further, the semiconductor transistor device may have one or more channel regions, such as semiconductor fins, nanosheets, nanowires, nanodots, etc., associated with a single, continuous gate structure or multiple gate structures. One of ordinary skill may recognize other examples of semiconductor transistor devices that may benefit from aspects of the present invention. The semiconductor transistor devices may be part of an Integrated Circuit (IC), and may include Static Random Access Memory (SRAM), logic circuits, passive components such as resistors, capacitors, and inductors, and/or active components such as p-type field effect transistors (PFET), n-type FETs (nfet), multi-gate FETs, Metal Oxide Semiconductor Field Effect Transistors (MOSFET), Complementary Metal Oxide Semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof.
Fig. 1 illustrates a perspective view of a semiconductor transistor device 100 according to some embodiments. Fig. 2 illustrates a cross-sectional view taken along line a-a' in the x-direction of fig. 1, in accordance with some embodiments. Fig. 3-5 illustrate cross-sectional views of the first, gate, and second source/drain regions of fig. 1 taken along lines B-B ', C-C ', and D-D ' respectively in the y-direction, according to some embodiments. Alternatively, fig. 2 to 5 and also the other sectional views thereafter can also show different embodiments separately. In addition, some elements are removed for ease of illustration, shown as transparent, or only border lines are shown. Additionally, components discussed with respect to one figure may be omitted from another figure, but may be incorporated into the embodiments shown in that figure where applicable. Fig. 2 shows a short-channel transistor device on the left and a long-channel transistor device on the right, which may be integrated on one substrate. Except for device dimensions, the components of the short channel transistor device and the long channel transistor device may be similar unless otherwise noted.
As shown in fig. 1, 2 and 5, the semiconductor transistor device 100 includes a channel structure 102 and a gate structure 104 encasing the channel structure 102. The channel structure 102 may include semiconductor layers separated and surrounded by a stack of metal elements of the gate structure 104. A first source/drain epitaxial structure 106 and a second source/drain epitaxial structure 108 are disposed on opposite ends of the channel structure 102. As one example, the channel structure 102 may be a pure silicon layer that is not doped with p-type and n-type impurities. The thickness of the channel structure 102 may be in a range between about 3nm and about 15 nm. The width of the channel structure 102 may be in a range between about 6nm and about 40 nm. As one example, the gate structure 104 may include a gate dielectric material, such as a high-k material (k greater than 7), a work function metal material, and a fill metal material, such as tungsten or aluminum. The thickness of the gate structure 104 may be in a range between about 2nm and about 10 nm. In some embodiments, the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 comprise a semiconductor material, such as silicon, germanium, or silicon germanium. The first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 may be hexagonal or diamond shaped. The first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 may be a source region and a drain region, respectively, of the semiconductor transistor device 100.
As shown in fig. 2, on the front side of the semiconductor transistor device 100, a front-side interconnect structure 114 may be arranged over the gate structure 104 and the first and second source/drain epitaxial structures 106, 108. The frontside interconnect structure 114 may include a plurality of frontside metal layers 116 disposed within and surrounded by the frontside interlayer dielectric 112. The front-side metal layer 116 includes vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The front-side interconnect structure 114 electrically connects various components or structures of the semiconductor transistor device. For example, the gate contact 110 may be disposed on the gate structure 104 and connected to an external circuit through the front side metal layer 116.
In some embodiments, on the back side of the semiconductor transistor device 100, a back side source/drain contact 120 is disposed below the first source/drain epitaxial structure 106 and connects the first source/drain epitaxial structure 106 to a back side power rail 122 disposed below the back side source/drain contact 120. A backside interconnect structure 124 can be formed to electrically connect to the backside source/drain contacts 120. Backside interconnect structure 124 may include a plurality of backside metal lines 216 and metal vias 218 disposed within and surrounded by backside interlayer dielectric layer 212. The backside interconnect structure 124 electrically connects various components or structures of the semiconductor transistor device. For example, the backside interconnect structure 124 may include a backside power rail 122 that connects external circuitry to the backside source/drain contacts 120. The backside source/drain contacts 120 and the backside power rail 122 may, for example, comprise a metallic material. For example, the backside source/drain contacts 120 may comprise a metal, such as tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), copper (Cu), or other suitable materials. As one example, the backside source/drain contacts 120 may have a thickness in a range between about 5nm and about 50nm and a width in a range between about 20nm and about 40 nm. Thus, the first source/drain epitaxial structure 106 may be connected to external circuitry from the back side of the semiconductor transistor device 100 through the back side source/drain contacts 120. Thus, more metal routing flexibility is provided and battery capacitance can be reduced. In some embodiments, the first dielectric liner 118 is disposed along sidewalls of the backside source/drain contact 120. As one example, the thickness of the first dielectric liner 118 may be less than about 5 nm.
As shown in fig. 1-3, the backside source/drain contact 120 may be located on the recessed bottom surface 106b of the first source/drain epitaxial structure 106. In some embodiments, the bottom surface 106b of the first source/drain epitaxial structure 106 may be recessed in a convex shape to a position vertically deeper than the bottom surface 104b of the gate structure 104. In some embodiments, as shown in fig. 2, the bottom surface 106b of the first source/drain epitaxial structure 106 may have a convex shape in the x-direction from the first source/drain epitaxial structure 106 to the second source/drain epitaxial structure 108, and may also have a convex shape in the y-direction as shown in fig. 3. The y-direction may be perpendicular to the x-direction. In some embodiments, the bottom surface 106b of the first source/drain epitaxial structure 106 may be vertically higher than the bottom surface 104b of the gate structure 104 by about 5nm to about 20nm deep. In some embodiments, a low temperature epitaxial layer 119 may be disposed between the recessed bottom surface 106b of the first source/drain epitaxial structure 106 and the backside source/drain contact 120, and a metal alloy layer 121 may be disposed on the low temperature epitaxial layer 119. The doping concentration of the low temperature epitaxial layer 119 may be greater than the doping concentration of the first source/drain epitaxial structure 106 so that a better metal alloy layer 121 may be subsequently formed for performance. As one example, the thickness of low temperature epitaxial layer 119 may be less than about 20 nm. A metal alloy layer 121 may be formed on the first source/drain epitaxial structure 106 for contact bonding. The metal alloy layer 121 may be a silicide layer formed by a self-aligned salification process. The metal alloy layer 121 may include a material selected from titanium silicide, cobalt silicide, nickel silicide, platinum silicide, nickel platinum silicide, erbium silicide, palladium silicide, combinations thereof, or other suitable materials. In some embodiments, the metal alloy layer 121 may include germanium.
As shown in fig. 1, 2, and 4, the bottom surface 108b of the second source/drain epitaxial structure 108 may be recessed to a position that is perpendicular to and even deeper than the bottom surface 104b of the gate structure 104. The bottom surface 108b of the second source/drain epitaxial structure 108 may be recessed deeper to a position vertically beyond the bottom surface 102b of the channel structure 102. In some embodiments, as shown in fig. 2, the bottom surface 108b of the second source/drain epitaxial structure 108 may have a convex shape in the x-direction from the first source/drain epitaxial structure 106 to the second source/drain epitaxial structure 108, and may also have a convex shape in the y-direction as shown in fig. 4. The y-direction may be perpendicular to the x-direction. In some embodiments, the bottom surface 108b of the second source/drain epitaxial structure 108 may be about 15nm higher to about 30nm deeper in the vertical direction than the bottom surface 104b of the gate structure 104. The recessed bottom surface 108b of the second source/drain epitaxial structure 108 may be lower in short channel transistor devices than long channel transistor devices. The bottom surface 108b may be recessed into the long channel transistor device to a shallower position than the short channel transistor device. The cell capacitance is further reduced compared to embodiments where the bottom surface 108b of the second source/drain epitaxial structure 108 is lower than the bottommost portion of the channel structure 102.
As shown in fig. 1-2 and 4-5, in some embodiments, on the backside of the semiconductor transistor device 100, a backside dielectric cap 126 is disposed below the gate structure 104. The backside dielectric cap 126 may also extend under the second source/drain epitaxial structure 108. The backside dielectric cap 126 may be surrounded by a lower isolation structure 160. The backside dielectric cap 126, instead of the original semiconductor body material, helps to separate and insulate the gate structure 104 from the backside source/drain contacts 120, thereby reducing cell capacitance and eliminating current problems, such as leakage, between the gate structure 104 and the backside source/drain contacts 120. The backside dielectric cap 126 may comprise an oxide, nitride, carbon nitride, or low-k dielectric material. In some embodiments, the second dielectric liner 127 lines the inner sidewalls of the backside dielectric cap 126. The second dielectric liner 127 may protect the second source/drain epitaxial structure 108 from oxidation and may also prevent metal gate threshold shift during fabrication. The second dielectric liner 127 may comprise a dielectric material.
As shown in fig. 1-2, in some embodiments, the backside source/drain contacts 120 may include a ledge 236 that extends directly below the gate structure 104. If the second dielectric liner 127 is omitted, the backside source/drain contacts 120 may contact the second dielectric liner 127 or the backside dielectric cap 126. In some embodiments, the liner 236 may be the result of forming and removing a protective spacer as described above or below in connection with fig. 23-32B. As one example, the ledge 236 may be less than 5nm wide and less than 20nm high. Additionally, inner spacers 128 may be disposed on opposite ends of the metal element of the gate structure 104 to isolate the gate structure 104 from the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108. The ledge 236 may also contact the inner spacers 128 and/or the gate structure 104. In some embodiments, gate spacers 134 are disposed along opposing sidewalls of an upper portion of gate structure 104. The outer surfaces of the inner spacers 128 may be substantially coplanar with the outer surfaces of the channel structure 102 and/or the gate spacers 134. In some embodiments, the upper isolation structures 220 are disposed in the trenches between the gate spacers 134. The upper isolation structures 220 provide electrical isolation between the gate structures 104.
As shown in fig. 5, in some embodiments, the gate structure 104 includes a gate dielectric layer 232 and a gate electrode 230. The gate electrode 230 includes one or more work function metal layers and a fill metal. A gate dielectric layer 232 may be conformally formed to line the outer surface of the gate electrode 230. The gate dielectric layer 232 may be in contact with the lower isolation structure 160 and the channel structure 102. In some embodiments, the gate dielectric layer 232 includes a high- κ material (κ greater than 7), such as hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Lanthanum oxide (La)2O3) Hafnium aluminum oxide (HfAlO)2) Hafnium silicon oxide (HfSiO)2) Alumina (Al)2O3) Or other suitable material.
As shown in fig. 1 and 3-5, in some embodiments, the lower isolation structure 160, the intermediate isolation structure 132, and the hard mask 136 may collectively act as an insulating structure separating the two semiconductor transistor devices 100a, 100b along the y-direction. In some embodiments, the air gap 192 may be formed around the lower portions of the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108.
Fig. 6-33B illustrate methods of fabricating semiconductor transistor devices at different stages according to some embodiments of the invention. In some embodiments, the semiconductor transistor devices illustrated in fig. 6-33B may be intermediate devices fabricated during processing of an Integrated Circuit (IC) or a portion thereof, which may include Static Random Access Memory (SRAM), logic circuits, passive elements such as resistors, capacitors, and inductors, and/or active elements such as p-type field effect transistors (PFET), n-type FETs (nfet), multi-gate FETs, Metal Oxide Semiconductor Field Effect Transistors (MOSFET), Complementary Metal Oxide Semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof.
As shown in the perspective view of fig. 6, a substrate 140 is provided. In some embodiments, the substrate 140 may be part of a wafer and may comprise silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or other suitable semiconductor materials. In some embodiments, the substrate 140 is a semiconductor-on-insulator (SOI) structure including a bulk substrate 142, an insulator substrate layer 144 on the bulk substrate 142, and a semiconductor substrate layer 146 on the insulator substrate layer 144. In various embodiments, the substrate 140 may comprise any of a variety of substrate structures and materials.
As shown in the perspective view of fig. 7, in some embodiments, an etch stop layer 148 is formed over the substrate 140 and a stack 150 is formed over the etch stop layer 148. As shown in fig. 22B, the etch stop layer 148 may serve as an etch stop layer for a subsequent substrate removal process. The etch stop layer 148 is made of a material having an etch rate different from that of the semiconductor substrate layer 146, and may be made of Si, a Si compound, SiGe, Ge, or a Ge compound. The stack structure 150 includes first and second semiconductor layers 152 and 154 alternately stacked. The first semiconductor layer 152 will serve as a channel region for the semiconductor transistor device. The second semiconductor layer 154 is a sacrificial layer that will be subsequently removed and replaced by the gate material. The first and second semiconductor layers 152 and 154 are made of materials having different lattice constants and may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP. In some embodiments, the first semiconductor layer 152 and the second semiconductor layer 154 are made of Si, Si compound, SiGe, Ge, or Ge compound. The stack structure 150 may be formed on the substrate 140 by epitaxy such that the stack structure 150 forms a crystalline layer. Although fig. 7 shows 4 layers of the first semiconductor layer 152 and 3 layers of the second semiconductor layer 154, the number of layers is not so limited, and each layer may be as small as 1 layer. In some embodiments, each of the first semiconductor layer and the second semiconductor layer form 2 to 10 layers. By adjusting the number of stacked layers, the drive current of the semiconductor transistor device can be adjusted.
In some embodiments, the first semiconductor layer 152 may be a pure silicon layer without germanium. The first semiconductor layer 152 may also be a substantially pure silicon layer, for example, having an atomic percent of germanium below about 1%. In addition, the first semiconductor layer 152 may be intrinsic, which is not doped with p-type and n-type impurities. In some embodiments, the thickness of the first semiconductor layer 152 is in a range between about 3nm and about 15 nm.
In some embodiments, the second semiconductor layer 154 may be a SiGe layer having an atomic percent of germanium greater than zero. In some embodiments, the germanium percentage of the second semiconductor layer 154 is in a range between about 10% and about 50%. In some embodiments, the thickness of the second semiconductor layer 154 is between about 2nm and about 10 nm.
As shown in the perspective view of fig. 8, in some embodiments, stacked structure 150 (see fig. 7) is patterned to form fin structures 156 and trenches 158 that extend in the X-direction. In some embodiments, the stacked structure 150 is patterned by an etching process using the patterned mask layer 157 as an etching mask, thereby removing portions of the stacked structure 150 not covered by the mask layer 157. In this process, the semiconductor substrate layer 146 and the etch stop layer 148 not covered by the mask layer 157 may also be partially or completely removed. The mask layer 157 may include a first mask layer and a second mask layer. The first mask layer may be a pad oxide layer made of silicon oxide, which may be formed through a thermal oxidation process. The second mask layer may be made of silicon nitride (SiN) formed by Chemical Vapor Deposition (CVD), including low pressure CVD (lpcvd) and plasma enhanced CVD (pecvd), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or other suitable processes. The mask layer 157 may be patterned using various patterning techniques, such as self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and the like. Fig. 8 shows two fin structures 156 arranged in the Y direction and parallel to each other, but the number of fin structures is not limited thereto and may be as small as one and three or more. In some embodiments, one or more dummy fin structures are formed on both sides of fin structure 156 to improve pattern fidelity in the patterning operation.
As shown in the perspective view of fig. 9, in some embodiments, a lower isolation structure 160, also referred to as a Shallow Trench Isolation (STI) structure, is formed above the insulator substrate layer 144 in a lower portion of the trench 158. An upper portion of fin structure 156 is exposed from lower isolation structure 160. The lower isolation structure 160 may be formed by forming an insulating material over the insulator substrate layer 144, followed by a planarization operation. The insulating material is then recessed to form lower isolation structures 160, exposing upper portions of fin structures 156. The insulating material may include a dielectric material, such as a nitride (e.g., silicon nitride, silicon oxynitride, silicon oxycarbide, silicon nitride), carbide (e.g., silicon carbide oxide), oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a kappa dielectric material having a dielectric constant of less than 7 (e.g., carbon-doped oxide, SiCOH), and the like. In some embodiments, the lower isolation structure 160 is formed by various steps including thermal oxidation or deposition processes (e.g., Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), sputtering, etc.) and removal processes (e.g., wet etching, dry etching, Chemical Mechanical Planarization (CMP), etc.).
As shown in the perspective view of fig. 10, in some embodiments, a cladding semiconductor layer 161 is formed over the outer surface of fin structure 156. In some embodiments, cladding semiconductor layer 161 comprises a semiconductor material, such as germanium, silicon germanium, or the like. In some embodiments, cladding semiconductor layer 161 comprises the same material as second semiconductor layer 154. Further, in some embodiments, the cladding semiconductor layer 161 may be formed by an epitaxial growth process or a deposition process (e.g., PVD, CVD, PECVD, ALD, sputtering, etc.).
As shown in the perspective view of fig. 11, in some embodiments, intermediate isolation structures 132 are formed over lower isolation structures 160 between fin structures 156. A dielectric liner 130 may be formed between the intermediate isolation structure 132 and the lower isolation structure 160 along sidewalls of the cladding semiconductor layer 161 and the lower isolation structure 160. A hard mask 136 may then be formed on top of the intermediate isolation structures 132 and the dielectric liner 130. Intermediate isolation structures 132 and dielectric liner 130 provide electrical isolation between fin structures 156, and hard mask 136 prevents intermediate isolation structures 132 from being lost in future patterning steps.
In some embodiments, the dielectric liner 130, the intermediate isolation structure 132, and the hard mask 136 are formed by deposition (e.g., PVD, CVD, PECVD, ALD, sputtering, etc.) and removal (e.g., etching, Chemical Mechanical Planarization (CMP), etc.) processes. Intermediate isolation structures 132 may have a top surface that is lower than fin structures 156. In some embodiments not shown in fig. 11, the planarization process of the hard mask 136 may also remove the cladding semiconductor layer 161 from over the fin structure 156. The top surface of hard mask 136 may be coplanar with the top surface of fin structure 156. In some embodiments, the middle isolation structure 132 and the lower isolation structure 160 may each comprise a low- κ dielectric material, wherein the dielectric constant is less than 7, such as, for example, silicon oxynitride, silicon carbo-nitride, silicon oxycarbonitride, silicon nitride, or some other suitable low- κ dielectric material. The dielectric liner 130 may be composed of a different material than the intermediate isolation structure 132 for the selective removal process. Hard mask 136 may comprise a high-k dielectric material, wherein the dielectric constant is greater than 7, such as, for example, hafnium oxide, zirconium oxide, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide, or some other suitable high-k dielectric material.
As shown in the perspective view of fig. 12, in some embodiments, cladding semiconductor layer 161 and mask layer 157 are etched from the top of fin structure 156. The top surfaces of the first semiconductor layer 152 and the cladding semiconductor layer 161 may be exposed by a removal process. In some embodiments, the hard mask 136 is selectively etched, for example, by a dry etch process and/or a wet etch process.
As shown in the perspective view of fig. 13, in some embodiments, dummy gate structures 170 spaced apart from each other in the x-direction are formed over the fin structures 156 along the y-direction. In some embodiments, the dummy gate structure 170 may include a sacrificial gate dielectric layer 162, a sacrificial gate electrode layer 164, a pad layer 166, and a mask layer 168 sequentially stacked on one another. Although two dummy gate structures 170 are illustrated in fig. 13, the number of dummy gate structures 170 is not limited thereto and may be more or less than two. In some embodiments, the sacrificial gate dielectric layer 162 may comprise, for example, a dielectric material such as a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), or some other suitable material. Sacrificial gate electrode layer 164 may comprise, for example, polysilicon. The pad layer 166 and the mask layer 168 may be comprised of thermal oxide, nitride, and/or other hard mask material and formed by way of a photolithographic process.
Subsequently, gate spacers 134 may be formed along opposing sidewalls of the dummy gate structure 170. A blanket layer of insulating material for the sidewall spacers is conformally formed to cover the dummy gate structures 170, for example, by using Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), or the like. The capping layer is deposited in a conformal manner such that it is formed to have substantially equal thickness on vertical surfaces, such as sidewalls, horizontal surfaces, and the top of the dummy gate structure 170. In some embodiments, the insulating material of the capping layer may comprise a silicon nitride based material. The capping layer is then etched using an anisotropic process to form gate spacers 134 on opposing sidewalls of the dummy gate structure 170.
As shown in the perspective view of fig. 14A in the gate region, the x-direction cross-sectional view of fig. 14B, the y-direction cross-sectional view of the gate region of fig. 14C, and the y-direction cross-sectional view of fig. 14D in the source or drain region, in some embodiments, a removal process is performed to remove the fin structure 156 from the first and second source/ drain regions 176, 178 in accordance with the dummy gate structure 170. Accordingly, the first semiconductor layer 152 and the second semiconductor layer 154 are shortened in the x direction, and may be vertically aligned with the gate spacer 134 (see fig. 14B). As one example, the exposed portions of fin structure 156 are removed by using a strained source/drain (SSD) etch process. The SSD etching process can be performed in a variety of ways. In some embodiments, the SSD etching process may be performed by dry chemical etching with a plasma source and a reactive gas. The plasma source may be an inductively coupled plasma (ICR) etch, a Transformer Coupled Plasma (TCP) etch, an Electron Cyclotron Resonance (ECR) etch, a Reactive Ion Etch (RIE), etc., and the reaction gas may be a fluorine-based gas, chloride (Cl2), hydrogen bromide (HBr), oxygen (O) gas2) And the like or combinations thereof. In some other embodiments, the SSD etching process may be by wet chemistryEtching is performed, such as Ammonium Peroxide Mixture (APM), ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), combinations thereof, and the like. In some other embodiments, the SSD etching step may be performed by a combination of dry chemical etching and wet chemical etching. Furthermore, in some embodiments, the removal process may partially or completely remove the bottommost first semiconductor layer 152 between the dummy gate structures 170. The bottommost first semiconductor layer 152 may have a concave top surface in the x-direction in the first and second source/drain regions 176 and 178 (see fig. 14B). In some embodiments, the top surface of the bottommost first semiconductor layer 152 may be recessed between the lower isolation structures 160 and lower than the top surface of the lower isolation structures 160.
In addition, the removal process may also include an isotropic etchant to further remove the end portions of the second semiconductor layer 154 under the gate spacers 134 and/or the dummy gate structures 170. Therefore, after the removal process, the first semiconductor layer 152 is wider than the second semiconductor layer 154 in the x-direction. The first semiconductor layer 152 may be formed after the removal process as a channel structure of the transistor device. It will be appreciated that the channel structures may take the form of stacked rectangles, as shown in the cross-sectional view of fig. 14B and other figures, while in other embodiments the channel structures may take other shapes, such as circles, octagons, ovals, diamonds, or the like.
As shown in the perspective view of fig. 15A and the cross-sectional view of fig. 15B in the x-direction, in some embodiments, the inner spacers 128 are formed on the end portions of the second semiconductor layer 154 in the x-direction. The outer surfaces of the inner spacers 128 may be substantially coplanar with the outer surfaces of the channel structures 152 and/or the gate spacers 134. In some embodiments, the inner spacers 128 are formed by a deposition process (e.g., CVD, PVD, PECVD, ALD, sputtering, etc.) followed by a selective removal process. For example, in some embodiments, a continuous layer may first be formed along the sidewalls and over the dummy gate structures 170. A vertical etch process may then be performed to remove portions of the continuous layer not vertically covered by the gate spacers 134 to form the inner spacers 128. Furthermore, in some embodiments, the inner spacers 128 comprise a dielectric material, such as, for example, silicon oxynitride, silicon carbon nitride, silicon carbide, silicon carbon oxide nitride, silicon nitride, or some other suitable material.
As shown in the perspective view of fig. 16A, the cross-sectional view in the x-direction of fig. 16B, and the cross-sectional view in the y-direction of fig. 16C in the first source/drain region, in some embodiments, a sacrificial source/drain contact 180 is formed below the first source/drain region 176, and a hard mask layer 182 covers the second source/drain region 178. In some embodiments, the sacrificial source/drain contacts 180 are formed through the etch stop layer 148 and extend deep into the semiconductor substrate layer 146. As an example, the sacrificial source/drain contacts 180 may be about 50nm thick. In some embodiments, the trench is first formed by etching at least a portion of the lowermost first semiconductor layer 152, the etch stop layer 148, and/or the semiconductor substrate layer 146 directly below the first source/drain region 176. The trenches are then filled with a sacrificial material to form sacrificial source/drain contacts 180. In some embodiments, the sacrificial source/drain contacts 180 may comprise intrinsic SiGe material having an atomic percent of germanium greater than zero. In some embodiments, the germanium percentage of the sacrificial source/drain contacts 180 is in a range between about 10% to about 50%. In some embodiments, the sacrificial source/drain contacts 180 comprise the same material as the second semiconductor layer 154. Furthermore, in some embodiments, the sacrificial source/drain contacts 180 may be formed by an epitaxial growth process or a deposition process (e.g., PVD, CVD, PECVD, ALD, sputtering, etc.). By forming the trenches and sacrificial source/drain contacts 180 therein, the source/drain contacts can be later formed self-aligned by replacing the sacrificial source/drain contacts 180, eliminating the overlapping movement of the contact joints.
As shown in the perspective view of fig. 17A in the first source/drain region, the x-direction cross-sectional view of fig. 17B, the y-direction cross-sectional view of fig. 17C, and the y-direction cross-sectional view of fig. 17D in the second source/drain region, in some embodiments, first source/drain epitaxial structure 106 and second source/drain epitaxial structure 108 are formed in first source/drain region 176 and second source/drain region 178, respectively, on opposite sides of dummy gate structure 170. In some embodiments, the first source/drain epitaxial structure 106 may be formed on the sacrificial source/drain contact 180. The second source/drain epitaxial structure 108 may be formed on the bottommost first semiconductor layer 152 or the semiconductor substrate layer 146. The first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 may be a source and a drain, respectively, of a semiconductor transistor device. In some embodiments, the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 comprise a semiconductor material. For example, the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 may include doped silicon, germanium, or silicon germanium, such as boron doped silicon germanium (SiGeB). In some embodiments, the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 are formed by an epitaxial growth process. The first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 may be hexagonal or diamond shaped. An air gap 192 may be formed around the lower portions of the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108. In some embodiments, an intermediate source/drain layer 107 is formed under the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 prior to forming the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108. The intermediate source/drain layer 107 may comprise boron doped silicon germanium (SiGeB). As an example, the thickness of the intermediate source/drain layer 107 may be about 20 nm.
In some embodiments, the depth of the epitaxially grown layer is affected by a loading effect. Devices with larger dimensions may form thicker epitaxial layers than devices with smaller dimensions. Fig. 17B to 17D and some of the following figures show short-channel transistors on the left side and long-channel transistors on the right side to illustrate the problem side by side. As shown in fig. 17B to 17D, the intermediate source/drain layer 107 and the first and second source/drain epitaxial structures 106 and 108 are formed deeper in a long-channel transistor than in a short-channel transistor. In some embodiments, the intermediate source/drain layer 107 is formed with a bottom surface that exceeds the etch stop layer 148 under the first and second source/ drain regions 176 and 178 in the long channel transistor. In some embodiments, the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 are formed such that edges of their bottom surfaces exceed the bottom surface 104b of the gate structure 104 in the long-channel transistor. For example, the depth of the intermediate source/drain layer 107 and the first and second source/drain epitaxial structures 106 and 108 may be about 5nm to 10nm deeper in a long channel transistor than in a short channel transistor. Thus, the bottom portions of the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 contact the bottommost first semiconductor layer 152. The bottom-most first semiconductor layer 152 will be removed during subsequent processing (see, e.g., fig. 28A-28D), and thus the bottom portions of the first and second source/drain epitaxial structures 106 and 108 may be exposed to an undesired etch process and may be damaged and pitted, which may affect performance or even cause long channel transistors to fail. Accordingly, some embodiments of methods of forming protective spacers to protect long channel transistors from such damage are illustrated below in association with fig. 22A-28D.
As shown in the perspective view of fig. 18A in the first source/drain region, the x-direction cross-sectional view of fig. 18B, the y-direction cross-sectional view of fig. 18C, and the y-direction cross-sectional view of fig. 18D in the second source/drain region, in some embodiments, an upper isolation structure 220 is formed over the previously formed structure overlying the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108. A planarization process is then performed to lower the gate spacers 134 and expose the sacrificial gate dielectric layer 162 and the sacrificial gate electrode layer 164 at the same level. In some embodiments, the etch stop liner 210 may be conformally formed to line previously formed structures prior to forming the upper isolation structures 220. In some embodiments, the etch stop liner 210 may comprise silicon nitride. In some other embodiments, the etch stop liner 210 may comprise other dielectric materials, such as silicon dioxide, silicon oxynitride, and the like. The etch stop liner 210 may be formed using plasma enhanced cvd (pecvd), however, other suitable methods may be used, such as low pressure cvd (lpcvd), Atomic Layer Deposition (ALD), and the like. The upper isolation structure 220 may be formed by Chemical Vapor Deposition (CVD), high density plasma CVD, spin coating, sputtering, or other suitable methods. In some embodiments, the upper isolation structure 220 may comprise silicon dioxide. In some other embodiments, the upper isolation structure 220 may comprise other dielectric materials, such as carbon doped oxide dielectrics including Si, O, C, and/or H (SiCOH or SiOC), low-k materials, or organic materials (e.g., polymers). The planarization operation may include a Chemical Mechanical Process (CMP).
As shown in the perspective view of fig. 19A, the cross-sectional view of fig. 19B in the x-direction, and the cross-sectional view of fig. 19C in the y-direction in the gate region, in some embodiments, a replacement gate process is performed to form the gate structure 104. In some embodiments, the gate structure 104 is formed by first removing the sacrificial gate dielectric layer 162 and the sacrificial gate electrode layer 164, thereby exposing the first semiconductor layer 152 and the second semiconductor layer 154 (see fig. 18B). The upper isolation structure 220 protects the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 during removal of the sacrificial gate dielectric layer 162 and the sacrificial gate electrode layer 164. A plasma dry etch and/or a wet etch may be used to remove sacrificial gate electrode layer 164. When sacrificial gate electrode layer 164 is polysilicon and upper isolation structure 220 is silicon oxide, a wet etchant such as a TMAH solution may be used to selectively remove sacrificial gate electrode layer 164. A plasma dry etch and/or a wet etch may be used to remove sacrificial gate electrode layer 164. Subsequently, the sacrificial gate dielectric layer 162 is also removed. As such, the first semiconductor layer 152 and the second semiconductor layer 154 are exposed.
Then, the second semiconductor layer 154 and the cladding semiconductor layer 161 are removed or etched using an etchant capable of selectively etching the second semiconductor layer 154 and the cladding semiconductor layer 161 at a faster etching rate than the first semiconductor layer 152 (see fig. 14C). The inner spacers 128 protect the first source/drain epitaxial structure 106 and the second source/drain epitaxial structure 108 from an etchant for etching the second semiconductor layer 154 and the cladding semiconductor layer 161 because the inner spacers 128 are made of a material having an etching selectivity to the second semiconductor layer 154 and the cladding semiconductor layer 161.
Gate structure 104 is then formed and/or filled between gate spacers 134 and inner spacers 128. That is, the gate structure 104 surrounds (or surrounds or wraps around) the first semiconductor layer 152, wherein the first semiconductor layer 152 is referred to as a channel of the semiconductor transistor device. Gate spacers 134 are disposed on opposite sides of the gate structure 104. The gate structure 104 includes a gate dielectric layer 232 and a gate electrode 230. The gate electrode 230 includes one or more work function metal layers and a fill metal. The gate dielectric layer 232 may be conformally formed. That is, the gate dielectric layer 232 is in contact with the lower isolation structure 160 and the first semiconductor layer 152 (see fig. 19C). In some embodiments, the gate dielectric layer 232 includes a high- κ material (κ greater than 7), such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), hafnium aluminum oxide (HfAlO2), hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), or other suitable materials. In some embodiments, the gate dielectric layer 232 may be formed by performing an ALD process or other suitable process.
The work function metal layer of the gate electrode 230 is formed on the gate dielectric layer 232 and, in some embodiments, surrounds the first semiconductor layer 152. The work function metal layer may comprise a material such as titanium nitride (TiN), tantalum (TaN), titanium aluminum silicon (TiAlSi), titanium silicon nitride (TiSiN), titanium aluminum (TiAl), tantalum aluminum (TaAl), or other suitable materials. In some embodiments, the work function metal layer may be formed by performing an ALD process or other suitable process. The fill metal of the gate electrode 230 fills the remaining space between the gate spacers 134 and between the inner spacers 128. That is, the work function metal layer is in contact with and between the gate dielectric layer 232 and the fill metal. The fill metal may comprise a material such as tungsten or aluminum. After depositing the gate dielectric layer 232 and the gate electrode 230, a planarization process, such as a CMP process, may then be performed to remove excess portions of the gate dielectric layer 232 and the gate electrode 230 to form the gate structure 104.
In some embodiments, an interfacial layer (not shown) is optionally formed before forming the gate structure 104 to surround the exposed surface of the first semiconductor layer 152 and the exposed surface of the semiconductor substrate layer 146 (see fig. 19B, 19C). In various embodiments, the interfacial layer may comprise, for example, silicon oxide (SiO)2) Or silicon oxynitride (SiON), and can be formed by chemical oxidation, thermal oxidation, atomic layer depositionBy volume (ALD), Chemical Vapor Deposition (CVD), and/or other suitable methods.
As shown in the perspective view of fig. 20, in some embodiments, a front-side interconnect structure 114 is formed over the gate structure 104 and the first and second source/drain epitaxial structures 106 and 108 (see fig. 22B). The frontside interconnect structure 114 may include a plurality of frontside metal layers 116 disposed within and surrounded by the frontside interlayer dielectric 112. The front-side interconnect structure 114 electrically connects various components or structures (e.g., the gate contact 110 and/or other contacts) of the semiconductor transistor device. The front-side metal layer 116 includes vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. Various interconnect features may implement various conductive materials including copper, tungsten, and silicide. In some examples, a damascene process is used to form a copper multilayer interconnect structure. Subsequently, a carrier substrate 240 is formed over the front-side interconnect structure 114. For example, the carrier substrate 240 is bonded to the frontside interconnect structure 114. In some embodiments, carrier substrate 240 is sapphire. In some other embodiments, the carrier substrate 240 is silicon, a thermoplastic polymer, an oxide, a carbide, or other suitable material.
As shown in the perspective view of fig. 21A and the x-direction cross-sectional view of fig. 21B, in some embodiments, the workpiece is "flipped" upside down and thinned from the back side. The bulk substrate 142, the insulator substrate layer 144, and the upper portion of the semiconductor substrate layer 146 and the lower isolation structure 160 are removed. Sacrificial source/drain contacts 180 are further etched under semiconductor substrate layer 146 and a mask layer 242 is formed on sacrificial source/drain contacts 180 and between semiconductor substrate layer 146. The bulk substrate 142, the insulator substrate layer 144, the semiconductor substrate layer 146, and the lower isolation structures 160 may be removed in a number of process operations using, for example, CMP and/or TMAH etching. In some embodiments, the mask layer 242 may be made of a polymer. Alternatively, the mask layer 242 may be made of a dielectric material.
As shown in the perspective view of fig. 22A and the x-direction cross-sectional view of fig. 22B, in some embodiments, the semiconductor substrate layer 146 is removed to form a backside cap trench 238 over the second source/drain epitaxial structure 108 and the gate structure 104. The semiconductor substrate layer 146 may be removed by an isotropic etch process and the etch stop layer 148 may serve as a stop layer for the etch process.
As shown in the x-direction cross-sectional view of fig. 23, in some embodiments, the etch stop layer 148 is removed to expose the bottommost first semiconductor layer 152. In some embodiments, the mask layer 242 may be removed from the top of the sacrificial source/drain contacts 180. A sidewall layer 244 is then formed along the top surface and/or sidewall surfaces of the sacrificial source/drain contacts 180. In some embodiments, the sidewall layer 244 is formed by a deposition process of a dielectric material, such as alumina, followed by a selective removal process. The thickness of the sidewall layer 244 may be, for example, about 5nm to 6 nm. The sidewall layer 244 covers a portion of the bottommost first semiconductor layer 152 proximate to the sacrificial source/drain contact 180 and the first source/drain epitaxial structure 106, thereby protecting the first source/drain epitaxial structure 106 from damage during subsequent removal of the bottommost first semiconductor layer 152 and recessing of the second source/drain epitaxial structure 108 (see fig. 26-27). Fig. 24-25D illustrate an alternative embodiment of forming protective spacers to protect the first source/drain epitaxial structure 106. The manufacturing steps of fig. 23 continue from fig. 26.
As shown in the x-direction cross-sectional view of fig. 24, in some embodiments in lieu of fig. 23, the etch stop layer 148 is removed and the bottommost first semiconductor layer 152 is partially removed while corner portions of the bottommost first semiconductor layer 152 remain as protective spacers 246 along the upper sidewalls of the first source/drain epitaxial structure 106, the second source/drain epitaxial structure 108, and/or the intermediate source/drain layer 107. In some embodiments, the bottommost first semiconductor layer 152 is partially removed by an isotropic wet etch process. The etching process may expose the top surface and/or sidewall surfaces of the sacrificial source/drain contacts 180.
As shown in the x-direction cross-sectional view of fig. 25A, the y-direction cross-sectional view of fig. 25B, and the y-direction cross-sectional view of fig. 25C in the first source/drain region, in some embodiments, sidewall spacers 248 are formed along the sacrificial source/drain contacts 180. The sidewall spacers 248 may be formed by depositing a conformal dielectric liner along the exposed surfaces of the workpiece, followed by an anisotropic etch process. The sidewall spacer 248 may be, for example, about 2nm to 3nm thick.
As shown in the x-direction cross-sectional views of fig. 26, 27 and 28B, the perspective view of fig. 28A, the y-direction cross-sectional view of fig. 28C, and the y-direction cross-sectional view of fig. 28D in the gate region in the second source/drain region, in some embodiments, the second source/drain epitaxial structure 108 is recessed from the top. As shown in fig. 26, the intermediate source/drain layer 107 is first removed. The sidewall layer 244 and underlying portions of the bottommost first semiconductor layer 152 (as shown in fig. 23) or sidewall spacers 248 and protective spacers 246 (as shown in fig. 25A) protect the first source/drain epitaxial structure 106 from damage during removal of the intermediate source/drain layer 107. Then, as shown in fig. 27, the second source/drain epitaxial structure 108 is recessed. Then, as shown in FIG. 28B, either the sidewall layer 244 (as shown in FIG. 23) or the sidewall spacer 248 (as shown in FIG. 25A) is removed. When recessing the second source/drain epitaxial structure 108 and removing the sidewall layer 244 or sidewall spacer 248 and the corner residue 152' of the bottommost first semiconductor layer 152, the bottommost first semiconductor layer 152 or protective spacer 246 may be partially removed, or the protective spacer 246 may remain along the upper sidewalls of the second source/drain epitaxial structure 108. In some embodiments, the second source/drain epitaxial structure 108 is recessed by isotropic etching or a combination of isotropic and anisotropic etching. The recessed bottom surface 108b of the second source/drain epitaxial structure 108 may be lower in short channel transistor devices than long channel transistor devices. The bottom surface 108B of the second source/drain epitaxial structure 108 may be recessed as a convex shape in both directions along the x-direction (to a position vertically deeper than the bottom surface 104B of the gate structure 104) (see fig. 28B) and along the y-direction (see fig. 28D) in the channel transistor device. In some embodiments, the bottom surface 108b of the second source/drain epitaxial structure 108 is about 10nm to 20nm deeper in the vertical direction than the bottom surface 104b of the gate structure 104 in the short channel transistor device. In a long channel transistor device, bottom surface 108b may be recessed to a position vertically equal to or deeper than bottom surface 104b of gate structure 104.
As in the gate region, fig. 29A, fig. 2As shown in the x-direction cross-sectional view of fig. 9B, the y-direction cross-sectional view of fig. 29C, and the y-direction cross-sectional view of fig. 29D in the second source/drain region, in some embodiments, a second dielectric liner 127 and a backside dielectric cap 126 are formed in the backside cap trench 238 (see fig. 28A). A second dielectric liner 127 and a backside dielectric cap 126 may be formed directly over the second source/drain epitaxial structure 108 and the gate structure 104. The second dielectric liner 127 may protect the second source/drain epitaxial structure 108 from oxidation and may also prevent metal gate threshold shift during subsequent fabrication processes. The second dielectric liner 127 may be formed by, for example, a conformal deposition process to deposit a dielectric material in the backside cap trench 238, and the back dielectric cap 126 may be formed by, for example, a deposition process to deposit a dielectric material on the second dielectric liner 127, followed by a CMP process to remove excess dielectric material outside the backside cap trench 238. As an example, the second dielectric liner 127 may be made of, for example, SiO2、Si3N4Low- κ material (κ) such as silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), and the like<7) Or such as HfO2、ZrO2High- κ materials (κ) such as ZrAlOx, HfAlOx, HfSiOx, AlOx, etc>7) And (4) preparing. In some embodiments, the backside dielectric cap 126 has a convex top surface 126s in contact with the second source/drain epitaxial structure 108. As an example, after the CMP process, the backside dielectric cap 126 may be formed, wherein the thickness T from the bottom surface 108b to the top surface of the backside dielectric cap 126 is about 40 nm. As one example, the thickness of the second dielectric liner 127 may be less than about 5 nm.
As shown in the perspective view of fig. 30A, the cross-sectional view in the x-direction of fig. 30B, and the cross-sectional view in the y-direction of fig. 30C in the source/drain regions, in some embodiments, the sacrificial source/drain contact 180 is removed and the underlying first source/drain epitaxial structure 106 is recessed from its backside to form a backside source/drain contact trench 234 recessed into an upper portion of the first source/drain epitaxial structure 106. The first source/drain epitaxial structure 106 may be recessed or etched using an etchant that is capable of selectively etching the first source/drain epitaxial structure 106 at a faster etch rate than the surrounding dielectric material. In some embodiments, the etching process is or includes an isotropic etching process, and the bottom surface 106B of the first source/drain epitaxial structure 106 may be recessed into a convex shape in both the x-direction (see fig. 30B) and in the x-direction (see fig. 30C) to reach a position vertically deeper than the bottom surface 104B of the gate structure 104 (see fig. 30B). In some embodiments, the bottom surface 106b of the first source/drain epitaxial structure 106 is about 10nm to 20nm deeper in the vertical direction than the bottom surface 104b of the gate structure 104. In some embodiments, when sacrificial source/drain contact 180 is removed and first source/drain epitaxial structure 106 is recessed, corner residue 152' is removed, leaving a void in backside source/drain contact trench 234.
As shown in the perspective view of fig. 31A, the x-direction cross-sectional view of fig. 31B, and the y-direction cross-sectional view of fig. 31C in the first source/drain region, in some embodiments, the backside source/drain contact trenches 234 are enlarged and rounded for better filling in subsequent processing steps. A low temperature epitaxial layer 119 may be formed on the recessed bottom surface 106b of the first source/drain epitaxial structure 106 in the enlarged backside source/drain contact trench 234. The doping concentration of the low temperature epitaxial layer 119 is greater than the doping concentration of the first source/drain epitaxial structure 106 so that a better metal alloy layer can be subsequently formed for performance. As an example, the low temperature epitaxial layer 119 may be formed to have a thickness of about 5 nm. In some embodiments, if the low temperature epitaxial layer 119 is not formed, a metal alloy layer 121 may be formed on the low temperature epitaxial layer 119 or the first source/drain epitaxial structure 106. The metal alloy layer 121 may be a silicide layer formed by a self-aligned salification process. The metal alloy layer 121 may include a material selected from titanium silicide, cobalt silicide, nickel silicide, platinum silicide, nickel platinum silicide, erbium silicide, palladium silicide, combinations thereof, or other suitable materials. In some embodiments, the metal alloy layer 121 may include germanium. The first dielectric liner 118 may be formed along sidewalls of the backside source/drain contact trenches 234 and may contact the second dielectric liner 127.
As shown in the perspective view of fig. 32A, the cross-sectional view in the x-direction of fig. 32B, and the cross-sectional view in the y-direction of fig. 32C in the first source/drain region, in some embodiments, the backside source/drain contact 120 is formed on the low temperature epitaxial layer 119 in the enlarged backside source/drain contact trench 234. In some embodiments, the backside source/drain contacts 120 may be formed with ledges 236 in the locations of the corner residues 152' of fig. 29B. The backside source/drain contacts 120 may have sidewalls that contact the inner sidewalls of the first dielectric liner 118. In some embodiments, the ledges 236 of the backside source/drain contacts 120 may extend directly over the inner spacers 128 or the gate structure 104. In some embodiments, the backside source/drain contacts 120 may be made of a metal, such as W, Co, Ru, Al, Cu, or other suitable material. As an example, the metal alloy layer 121 may be formed to have a thickness of about 5 nm. After depositing the backside source/drain contacts 120, a planarization process, such as a Chemical Mechanical Planarization (CMP) process, may then be performed.
As shown in the perspective view of fig. 33A and the x-direction cross-sectional view of fig. 33B, in some embodiments, a backside power rail 122 and a backside interconnect structure 124 are formed to be electrically coupled to the backside source/drain contacts 120. Backside interconnect structure 124 may include a plurality of backside metal lines 216 and metal vias 218 disposed within and surrounded by backside interlayer dielectric layer 212. The backside interconnect structure 124 electrically connects various components or structures of the semiconductor transistor device. For example, a backside interconnect structure 124 may be disposed on the backside power rail 122 and connect external circuitry to the backside source/drain contacts 120.
Fig. 34 illustrates a flow diagram of some embodiments of a method 3400 of forming an integrated chip having a plurality of transistor devices having a high device density due to an air spacer structure and a high-k dielectric spacer structure.
While the method 3400 is shown and described below as a series of steps or events, it should be understood that the illustrated ordering of such steps or events should not be interpreted in a limiting sense. For example, some steps may occur in different orders and/or concurrently with other steps or events apart from those illustrated and/or described herein. Moreover, not all illustrated acts may be required to implement one or more aspects of the described embodiments. Further, one or more of the steps described herein may be performed in one or more separate steps and/or stages.
At step 3402, a plurality of fin structures of a first semiconductor layer and a second semiconductor layer stacked on a substrate are formed. Isolation structures may be formed between the fin structures. Fig. 6-12 show perspective views of some embodiments corresponding to step 3402.
At step 3404, a plurality of dummy gate structures are formed over the fin structures. Figure 13 illustrates a perspective view of some embodiments corresponding to step 3404.
In step 3406, portions of the fin structure not covered by the dummy gate structure are etched and removed from opposite sides of the dummy gate structure. The second semiconductor layer may be horizontally recessed from the first semiconductor layer, and inner spacers may be formed on opposite ends of the second semiconductor layer. Fig. 14A-15B illustrate various views of some embodiments corresponding to step 3406.
At step 3408, a first dummy backside contact is formed in the substrate. Fig. 16A-16C illustrate various views of some embodiments corresponding to step 3408.
At step 3410, a first source/drain epitaxial structure and a second source/drain epitaxial structure are formed on opposite sides of the recessed fin structure. Fig. 17A-17D illustrate various views of some embodiments corresponding to step 3410.
At step 3412, the second semiconductor layer is replaced with a metal gate structure. Then, a gate contact and a front-side interconnect structure are formed. Fig. 18A-20 show various views of some embodiments corresponding to step 3412.
At step 3414, the substrate is thinned from the backside and a mask layer may be formed on the sacrificial source/drain contacts. Fig. 21A-21B illustrate various views of some embodiments corresponding to step 3414.
At step 3416, the substrate is further lowered to a position below the top surface of the sacrificial source/drain contacts and a backside cap trench is formed over the gate structure and the second source/drain epitaxial structure. The substrate may be lowered by an etch process that stops on the etch stop layer. Fig. 22A-22B illustrate various views of some embodiments corresponding to step 3416.
At step 3417, the etch stop layer is removed to expose the bottommost first semiconductor layer and a thick sidewall layer is formed along the sacrificial source/drain contacts. The thick sidewall layer covers a portion of the bottommost first semiconductor layer proximate to the sacrificial source/drain contact and the first source/drain epitaxial structure, thereby protecting the first source/drain epitaxial structure from damage during subsequent removal of the bottommost first semiconductor layer and recessing of the second source/drain epitaxial structure. Fig. 23 illustrates a cross-sectional view of some embodiments corresponding to step 3417.
At step 3418 and step 3420, in some embodiments of the alternative to step 3417, at step 3418 protective spacers are formed at the corners of the S/D epitaxial structure and at step 3420 sidewall spacers are formed along the sacrificial source/drain contacts. The protective spacers and sidewall spacers protect the first source/drain epitaxial structure from damage during subsequent removal of the bottommost first semiconductor layer and recessing of the second source/drain epitaxial structure. Fig. 24 illustrates a cross-sectional view of some embodiments corresponding to step 3418. Fig. 25A-25D illustrate various views of some embodiments corresponding to step 3420.
At step 3422, the bottom surface of the second source/drain epitaxial structure is recessed, wherein the lower portion of the bottommost first semiconductor layer or the protective spacers protect the sidewalls of the first source/drain epitaxial structure. Fig. 26-28D illustrate various views of some embodiments corresponding to step 3422.
At step 3424, a backside dielectric cap is formed on the bottom surface of the second source/drain epitaxial structure. Fig. 29A-29D illustrate various views of some embodiments corresponding to step 3424.
At step 3426, a contact trench is formed and the bottom surface of the first source/drain epitaxial structure is recessed. Fig. 30A-31C illustrate various views of some embodiments corresponding to step 3426.
At step 3428, backside source/drain contacts are formed to the bottom surface of the first source/drain epitaxial structure. Fig. 28A-28C illustrate various views of some embodiments corresponding to step 3428.
At step 3430, backside power rails and backside interconnect structures are formed. Fig. 29A-29B illustrate various views of some embodiments corresponding to step 3430.
Accordingly, in some embodiments, the present invention relates to a method of forming a semiconductor transistor device. The method includes forming a fin-shaped channel structure over a substrate, and forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite ends of the fin structure. The method also includes forming a metal gate structure surrounding the fin structure. The method also includes flipping and partially removing the substrate to form a backside capped trench while leaving a lower portion of the substrate as a protective spacer along upper sidewalls of the first and second source/drain epitaxial structures. The method also includes forming a backside dielectric cap in the backside cap trench.
In some embodiments, the backside cap trench is formed to expose a bottom surface of the metal gate structure and a bottom surface of the second source/drain epitaxial structure, wherein the bottom surface of the second source/drain epitaxial structure is recessed. In some embodiments, the method further comprises forming an etch stop layer on the substrate prior to forming the fin-shaped channel structure. In some embodiments, the method further comprises forming a sacrificial source/drain contact through the etch stop layer in the substrate on one side of the fin-shaped channel structure prior to forming the first source/drain epitaxial structure and the second source/drain epitaxial structure. In some embodiments, the protective spacer is formed to cover a lower sidewall of the first source/drain epitaxial structure connecting the sacrificial source/drain contacts. In some embodiments, the method further comprises: removing the sacrificial source/drain contacts from backside contact trenches and recessing first source/drain epitaxial structures exposed to the backside contact trenches after forming the backside dielectric caps; and filling a backside source/drain contact in the backside contact trench in contact with the first source/drain epitaxial structure; wherein the protective spacer is removed when the first source/drain epitaxial structure is recessed. In some embodiments, the method further comprises: forming a hard mask covering a top surface of the sacrificial source/drain contacts after flipping the substrate; wherein the substrate is partially removed with the hard mask in place. In some embodiments, the method further comprises: forming sidewall spacers along sidewalls of the sacrificial source/drain contacts; wherein the bottom surface of the second source/drain epitaxial structure is recessed with the sidewall spacers and the protective spacers in place. In some embodiments, the protective spacer is formed to extend along a bottom surface of the metal gate structure. In some embodiments, forming the fin-shaped channel structure comprises: forming a fin structure by alternately stacking a first semiconductor layer and a second semiconductor layer over the substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure not covered by the dummy gate structure; and replacing the dummy gate structure and the first semiconductor layer with the metal gate structure.
In other embodiments, the invention relates to a method of fabricating a semiconductor transistor device. The method also includes forming a fin-shaped channel structure over the substrate; and forming a sacrificial source/drain contact in the substrate on one side of the fin-shaped channel structure. The method also includes forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite ends of the fin structure. The first source/drain epitaxial structure is located over the sacrificial source/drain contact. The method also includes forming a metal gate structure surrounding the fin structure and flipping and thinning the substrate. The method also includes forming a protective spacer along upper sidewalls of the first and second source/drain epitaxial structures and forming a backside cap trench to expose a bottom surface of the metal gate structure and a bottom surface of the second source/drain epitaxial structure. The bottom surface of the second source/drain epitaxial structure is recessed. The method also includes forming a backside dielectric cap in the backside cap trench.
In some embodiments, the protective spacer is formed by: partially removing the substrate to expose top surfaces and sidewall surfaces of the sacrificial source/drain contacts while leaving a lower portion of the substrate as a protective spacer along upper sidewalls of the first and second source/drain epitaxial structures. In some embodiments, the substrate is removed by an isotropic etch process that exposes the bottom surface of the metal gate structure while leaving the protective spacers at the corners of the first source/drain epitaxial structure. In some embodiments, the method further comprises: forming a sidewall liner covering the sidewall surfaces of the sacrificial source/drain contacts; wherein the backside cap trench is formed with the sidewall liner in place. In some embodiments, the method further comprises: replacing the sacrificial source/drain contact with a backside source/drain contact underlying and in contact with the first source/drain epitaxial structure after forming the backside dielectric cap. In some embodiments, forming the fin-shaped channel structure comprises: forming a fin structure by alternately stacking a first semiconductor layer and a second semiconductor layer over the substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure not covered by the dummy gate structure; forming inner spacers on opposite sides of a remaining portion of the first semiconductor layer; and replacing the dummy gate structure and the first semiconductor layer with the metal gate structure.
In yet another embodiment, the present invention relates to a semiconductor device. The semiconductor device comprises a channel structure and a grid structure wrapping the channel structure. The semiconductor device further includes: first and second source/drain epitaxial structures disposed on opposite ends of the channel structure and a backside source/drain contact disposed below and in contact with the first source/drain epitaxial structure. The semiconductor device also includes a gate contact disposed on the gate structure and a backside source/drain contact disposed below and in contact with the first source/drain epitaxial structure. The semiconductor device further includes a backside dielectric cap disposed below and extending along the second source/drain epitaxial structure and the gate structure. The bottom surface of the first source/drain epitaxial structure has a concave shape.
In some embodiments, the backside source/drain contact comprises a flange extending under the gate structure. In some embodiments, a bottom surface of the second source/drain epitaxial structure has a concave shape. In some embodiments, a top surface of the backside source/drain contact is located higher than a bottom surface of the gate structure.
The foregoing has outlined the components of several embodiments in order that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A method of forming a semiconductor transistor device, the method comprising:
forming a fin-shaped channel structure above a substrate;
forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite ends of the fin-shaped channel structure;
forming a metal gate structure around the fin-shaped channel structure;
partially removing the substrate from a backside of the substrate to form a backside cap trench while leaving a lower portion of the substrate as a protective spacer along upper sidewalls of the first and second source/drain epitaxial structures; and
a backside dielectric cap is formed in the backside cap trench.
2. The method of claim 1, wherein the backside cap trench is formed to expose a bottom surface of the metal gate structure and a bottom surface of the second source/drain epitaxial structure, wherein the bottom surface of the second source/drain epitaxial structure is recessed.
3. The method of claim 2, further comprising forming an etch stop layer on the substrate prior to forming the fin-shaped channel structure.
4. The method of claim 3, further comprising forming a sacrificial source/drain contact through the etch stop layer in the substrate on one side of the fin-shaped channel structure prior to forming the first source/drain epitaxial structure and the second source/drain epitaxial structure.
5. The method of claim 4, wherein the protective spacer is formed to cover a lower sidewall of the first source/drain epitaxial structure connecting the sacrificial source/drain contacts.
6. The method of claim 4, further comprising:
removing the sacrificial source/drain contacts from backside contact trenches and recessing first source/drain epitaxial structures exposed to the backside contact trenches after forming the backside dielectric caps; and
filling a backside source/drain contact in the backside contact trench in contact with the first source/drain epitaxial structure;
wherein the protective spacer is removed when the first source/drain epitaxial structure is recessed.
7. The method of claim 4, further comprising:
forming a hard mask covering a top surface of the sacrificial source/drain contacts after flipping the substrate;
wherein the substrate is partially removed with the hard mask in place.
8. The method of claim 7, further comprising:
forming sidewall spacers along sidewalls of the sacrificial source/drain contacts;
wherein the bottom surface of the second source/drain epitaxial structure is recessed with the sidewall spacers and the protective spacers in place.
9. A method of forming a semiconductor transistor device, the method comprising:
forming a fin-shaped channel structure above a substrate;
forming a sacrificial source/drain contact in the substrate on one side of the fin-shaped channel structure;
forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite ends of the fin-shaped channel structure, the first source/drain epitaxial structure being located over the sacrificial source/drain contact;
forming a metal gate structure around the fin-shaped channel structure;
turning over and thinning the substrate;
forming a protective spacer along upper sidewalls of the first and second source/drain epitaxial structures;
forming a backside cap trench to expose a bottom surface of the metal gate structure and a bottom surface of the second source/drain epitaxial structure, wherein the bottom surface of the second source/drain epitaxial structure is recessed; and
a backside dielectric cap is formed in the backside cap trench.
10. A semiconductor device, comprising:
a channel structure;
the grid structure wraps the channel structure;
a first source/drain epitaxial structure and a second source/drain epitaxial structure disposed on opposite ends of the channel structure;
a gate contact disposed on the gate structure;
a backside source/drain contact disposed below and in contact with the first source/drain epitaxial structure; and
a backside dielectric cap disposed below and extending along the second source/drain epitaxial structure and the gate structure;
wherein a bottom surface of the first source/drain epitaxial structure has a concave shape.
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