CN113517169A - Matcher output power debugging method and system - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32174—Circuits specially adapted for controlling the RF discharge
- H01J37/32183—Matching circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/332—Coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
Abstract
The invention provides a method and a system for debugging output power of a matcher. The debugging method specifically comprises the following steps: when the radio frequency power supply is started, detecting an input power value of an input end of the matcher and an output power value of an output end of the matcher; calculating an actual efficiency value of the matcher, wherein the actual efficiency value is equal to the ratio of the output power value and the input power value of the matcher; judging whether the actual efficiency value is within a preset efficiency range, if not, calculating an efficiency compensation value, wherein the efficiency compensation value is equal to the ratio of the preset efficiency value to the actual efficiency value, and adjusting the input power of the matcher according to the efficiency compensation value. The invention provides a matcher output power debugging method and a debugging system, which can obtain the required output power by carrying out less debugging times, thereby reducing the resource consumption for debugging and shortening the debugging time.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a matcher output power debugging method and a matcher output power debugging system.
Background
Currently, plasma surface treatment techniques are widely used in the field of semiconductor manufacturing. Plasma surface treatment processes are generally performed by exciting a plasma in a process chamber and applying a certain rf power to a wafer to attract a designated plasma to deposit or bombard the surface of the wafer, thereby coating or etching the wafer. The radio frequency power participating in the process is generated by a radio frequency power supply and is matched into the chamber through the matcher, but the radio frequency power actually matched into the chamber cannot be known because the matcher has power loss. Moreover, different matchers have different efficiencies, so that the input power of the plasma processing equipment needs to be debugged before the equipment is put into use in order to ensure the consistency of the product quality, so as to avoid unknown influence on the product caused by the inconsistency between the input power and the actual power of the chamber.
The existing debugging method comprises the following steps: firstly, the chamber is subjected to linearity calibration of a radio frequency power supply, then the test wafer is used for etching rate test, the linearity of the radio frequency power supply is adjusted according to the test result, then the output power of the radio frequency power supply is adjusted, and then the etching rate test of a new test wafer is restarted until the etching rate of the equipment reaches the value required by a user. However, this method usually cannot be adjusted to a desired value at one time, and it needs to perform tens of adjustments to obtain the desired etching rate and the desired rf power output, which results in a waste of resources and time in the whole debugging process.
Disclosure of Invention
The present invention is directed to solve at least one of the technical problems of the prior art, and provides a method for debugging output power of a matcher, which can obtain required output power through a small number of times of debugging, thereby reducing resource consumption for debugging and shortening debugging time.
In order to achieve the object of the present invention, an output power debugging method for a matcher is provided, wherein an input terminal of the matcher is electrically connected to an output terminal of a radio frequency power supply, and an output terminal of the matcher is electrically connected to a radio frequency power receiving terminal of a process chamber, the method comprising: when a radio frequency power supply is started, detecting an input power value of an input end of the matcher and an output power value of an output end of the matcher;
calculating an actual efficiency value of the matcher, wherein the actual efficiency value is equal to the ratio of an input power value and an output power value of the matcher;
judging whether the actual efficiency value is within a preset efficiency range, if not, calculating an efficiency compensation value which is equal to the ratio of the preset efficiency value to the actual efficiency value, and adjusting the input power of the matcher according to the efficiency compensation value.
Optionally, the adjusting the input power of the input end of the matcher according to the efficiency compensation value specifically includes:
calculating a target input power value equal to a product of the efficiency compensation value and an input power value of the matcher;
and adjusting the output power of the radio frequency power supply to the target input power value.
Optionally, after determining that the actual efficiency value is not within the preset efficiency range, the method further includes:
judging whether the adjustment times exceed a preset maximum adjustment time, and if so, sending prompt information indicating that the matcher is calibrated;
and if not, adding 1 to the adjusting times.
Optionally, the method further comprises the following steps:
and setting the initial value of the debugging times to be 0 when the radio frequency power supply is started.
Optionally, after the step of detecting the input power value at the input end of the matcher and the output power value at the output end of the matcher and before the step of calculating the actual efficiency value of the matcher, the method further includes:
judging whether the input power value of the matcher is within a preset power range or not, and if so, calculating the actual efficiency value of the matcher; if not, sending prompt information indicating that the output power of the radio frequency power supply is calibrated.
As another scheme, the present invention further provides a debugging system for debugging the output power of the matcher, which is characterized by comprising: the radio frequency power supply comprises a power detection unit and a control unit, wherein the power detection unit is used for detecting an input power value of an input end of a matcher and an output power value of an output end of the matcher when a radio frequency power supply is started, and sending the input power value and the output power value to the control unit;
the control unit is used for calculating the actual efficiency value of the matcher, wherein the actual efficiency value of the matcher is equal to the ratio of the input power value and the output power value of the matcher;
the control unit is further used for judging whether the actual efficiency value is within a preset efficiency range, if not, calculating an efficiency compensation value, wherein the efficiency compensation value is equal to the ratio of the preset efficiency value to the actual efficiency value, and controlling the radio frequency power supply to adjust the input power of the matcher according to the efficiency compensation value.
Optionally, the control unit is further configured to calculate a target input power value, where the target input power value is equal to a product of the efficiency compensation value and the input power value of the matcher;
the control unit is further configured to control the radio frequency power supply to adjust the input power of the matcher to the target input power value.
Optionally, the power detection unit includes an input power detector and an output power detector, where the input power detector is configured to detect input power at an input end of the matcher, and the output power detector is configured to detect output power at an output end of the matcher.
Optionally, the control unit is further configured to determine whether the adjustment times exceed a preset maximum debugging time, and if so, stop debugging and send a prompt message indicating that the matcher is calibrated; and if not, adding 1 to the adjusting times.
Optionally, the control unit is further configured to determine whether an input power value of the matcher is within a preset power range, and if so, calculate an actual efficiency value of the matcher; if not, sending prompt information indicating that the output power of the radio frequency power supply is calibrated.
The invention has the following beneficial effects:
according to the output power debugging method of the matcher, the input power and the output power of the matcher are directly detected, the efficiency compensation value is calculated according to the preset efficiency value, the input power of the matcher is adjusted according to the efficiency compensation value, so that the input power of the matcher can be accurately adjusted, the debugging times can be reduced, the resources for debugging can be reduced, the debugging time is shortened, and the debugging cost is reduced.
According to the debugging system provided by the invention, the power detection unit is used for detecting the output power and the input power of the output end and the input end of the matcher, the control unit is used for calculating the efficiency compensation value according to the output power and the input power of the matcher, and controlling the radio frequency power supply to adjust the input power of the matcher according to the efficiency compensation value, so that the input power of the matcher can be accurately adjusted, the debugging times can be reduced, the resources for debugging can be further reduced, the debugging time is shortened, and the debugging cost is reduced.
Drawings
Fig. 1 is a flowchart of a matcher output power debugging method provided in embodiment 1 of the present invention;
fig. 2 is a flowchart of step S05 of the matcher output power debugging method in embodiment 1 of the present invention;
fig. 3 is a flowchart of steps S06 to S07 of the matcher output power debugging method in embodiment 1 of the present invention;
fig. 4 is a flowchart of steps S01 to S02 of another debugging method according to embodiment 1 of the present invention;
FIG. 5 is a flow chart of a software algorithm flow provided in embodiment 1 of the present invention;
fig. 6 is a schematic structural diagram of a debugging system provided in embodiment 2 of the present invention;
fig. 7 is a schematic structural diagram of a debugging system provided in embodiment 2 of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the following describes the matcher output power debugging method and debugging system provided by the present invention in detail with reference to the accompanying drawings.
Example 1
The invention provides a matcher output power debugging method for achieving the aim of the invention. Specifically, the input end of the matcher is electrically connected with the output end of the radio frequency power supply, and the output end of the matcher is electrically connected with a radio frequency power receiving end (such as an upper electrode coil or a lower electrode of a process chamber) of the process chamber; the matcher is used for feeding the radio frequency power output by the radio frequency power supply into the reaction chamber. However, since the matching devices have a certain loss, the power fed into the reaction chamber through the matching devices is far from the actual output power of the rf power source, and the loss of the matching devices is different from each other, so that the quality uniformity of the manufactured wafer cannot be guaranteed if the matching devices are directly put into use. To solve the above technical problem, as shown in fig. 1, the debugging method provided in this embodiment includes the following steps:
step S01: when the radio frequency power supply is started, detecting an input power value of an input end of the matcher and an output power value of an output end of the matcher;
step S02: calculating an actual efficiency value of the matcher, wherein the actual efficiency value is equal to the ratio of the output power value and the input power value of the matcher;
step S03: judging whether the actual efficiency value is within a preset efficiency range, and if so, completing debugging; if not, go to step S04;
specifically, the preset efficiency value may be selected according to the actual processing requirement, for example, 95%; the preset efficiency range may be a value around the preset efficiency value, for example, 95% ± 1%.
Step S04: calculating an efficiency compensation value, wherein the efficiency compensation value is equal to the ratio of a preset efficiency value to an actual efficiency value;
step S05: and adjusting the input power of the matcher according to the efficiency compensation value.
The input power of the matcher is adjusted according to the efficiency compensation value, namely the output power of the radio frequency power supply is adjusted, so that the input power of the matcher can be accurately adjusted, the input power of the matcher (or the output power of the radio frequency power supply) is adjusted to be high or low in a non-blind manner, the input power of the matcher can be quickly adjusted to a value corresponding to the output power value of the actually required matcher, the adjustment times can be reduced, the resources for debugging can be reduced, the debugging time is shortened, and therefore the debugging cost can be reduced.
Specifically, after the step S05 is finished, the steps S01-S03 may be executed again to test the adjusted output power of the matcher, and whether the adjusted output power of the matcher is successfully debugged is determined by determining whether the actual efficiency value is within the preset efficiency range; if not successful, the process proceeds to step S04 and step S05. And continuously and circularly carrying out the steps until debugging is successful to obtain the actually required output power value of the matcher, so that the actually required radio frequency power is accurately fed into the reaction chamber to ensure the quality of the wafer.
In some implementations, the aforementioned step S05, that is, the step of adjusting the input power of the matcher according to the efficiency compensation value, as shown in fig. 2, specifically includes the following steps:
step S051: calculating a target input power value, specifically, the target input power value is equal to the product of the efficiency compensation value and the input power value of the matcher;
step S052: and adjusting the output power of the radio frequency power supply to a target input power value so as to adjust the input power of the matcher to the target input power value.
Specifically, the target input power value calculated in steps S051 and S052 is equal to the original input power × the preset efficiency value/(output power/preset output power) of the matcher, so that it is easy to understand that the adjustment accuracy of the power value can be improved to a certain extent by introducing a plurality of parameters, and thus the input power of the matcher can be adjusted more accurately, and further the adjustment times can be reduced, and the debugging cost can be reduced. However, the calculation manner of the target input power value is not limited to this, and in some embodiments, the target input power value may also be equal to the original input power/(output power/preset output power) of the matcher.
In some implementations, as shown in fig. 3, after performing step S03, that is, after determining whether the actual efficiency value is within the preset efficiency range, the debugging method further includes:
step S06: judging whether the adjustment times exceed a preset maximum adjustment time, and if so, sending prompt information indicating a calibration matcher; if not, continue to step S07;
specifically, the preset maximum number of times of adjustment may be set according to the results of multiple experiments, for example, 3 times. However, it should be noted that, in an ideal state, the maximum adjustment number may be 1 at the minimum, that is, the output power of the actually required matcher may be obtained after one debugging.
Step S07: the number of times of adjustment is increased by 1 to count the number of times of adjustment.
In some embodiments, the initial value of the adjustment times is set to 0 when the radio frequency power supply is turned on, so that 1 is added to the original adjustment times every time the adjustment is performed in the subsequent adjustment process.
Since the matching unit for feeding power to the process chamber is generally formed of a reactance element such as a capacitor or an inductor, input power of the matching unit is generally power-lost due to impedance mismatch, and output power of the matching unit is generally lower than input power of the matching unit. As is clear from step S052, the debugging method described above is highly accurate in adjusting the input power, but the actual adjustment amount is small, so the debugging method proposed in the above embodiment can only be used for fine adjustment. Therefore, when the impedance of the matcher is not matched, the difference between the input power and the output power of the matcher is too large, and accordingly, the actually required output power can be reached only by performing debugging for too many times (even the actually required output power cannot be obtained), which may cause a problem of too long debugging time. Therefore, the step of counting the adjusting times is added in the debugging process, and an operator is prompted to check and calibrate the matcher in time while the adjusting times are limited, so that the problem of excessive adjusting times caused by mismatching of the impedance of the matcher can be avoided, resources for debugging can be reduced, and the debugging time is shortened.
In some embodiments, as shown in fig. 4, between step S01 and step S02, i.e., after the step of detecting the input power value of the input terminal of the matcher and the output power value of the output terminal of the matcher, and before the step of calculating the actual efficiency value of the matcher, the following steps are further included:
step S011: judging whether the input power value of the matcher is within a preset power range, if so, performing step S02; if not, go to step S012;
step S012: and sending prompt information indicating the output power of the calibration radio frequency power supply to prompt an operator to adjust the output power value of the radio frequency power supply to be within a preset power range.
The reason why steps S011 and S012 are added between step S01 and step S02 is that the method for debugging the output power of the matcher provided in this embodiment aims to precisely and slightly adjust the input power of the matcher, so that if the input power of the matcher exceeds the preset input power range, it is difficult to obtain the actually required output power even if the input power of the matcher is debugged for an extremely large number of times; therefore, before the start of debugging the matcher, the radio frequency power supply needs to be power calibrated, so that the problem of debugging failure caused by too large difference between the input power and the preset input power of the matcher due to too large difference between the input power and the preset input power of the matcher can be avoided before calculating the input power and the output power of the matcher. Specifically, the predetermined power range should include and be close to the actually required output power of the matcher.
Preferably, this embodiment further provides a software algorithm flow integrating the debugging steps, as shown in fig. 5, which includes the following steps:
step S11: setting a preset efficiency value, a preset power value, an initial adjustment frequency, a first tolerance and a second tolerance;
wherein the preset efficiency value is 95% for example; the preset power value is 500W for example; the number of initial adjustments was 0.
Step S12: adjusting the output power of the radio frequency power supply to a preset power value, namely adjusting the input power of the matcher to the preset power value;
step S13: judging whether the detected input power of the matcher is within a preset power range, if so, performing step S14; if not, sending prompt information indicating the output power of the radio frequency power supply to be calibrated so as to prompt an operator to adjust the output power value of the radio frequency power supply to be within a preset power range; specifically, the preset power range is a preset power value plus or minus a first tolerance;
step S14: delaying for a certain time;
step S15: calculating the ratio of the output power value and the input power value of the matcher, and taking the ratio as the actual efficiency value of the matcher, wherein the detected output power value and the detected input power value of the matcher can be abstracted into double-precision type data which can be read in real time, so that the precision of a calculation result is improved;
step S16: judging whether the actual efficiency value is within a preset efficiency range, and if so, completing debugging; if not, go to step S17; specifically, the preset efficiency range is the preset efficiency plus or minus a second tolerance;
step S17: judging whether the adjustment times exceed a preset maximum adjustment time, if so, sending prompt information representing calibration of the matcher so as to prompt debugging personnel to debug the matcher; if not, continue to step S18; specifically, the preset maximum adjustment times may be 3 times;
step S18: adding 1 to the adjusting times;
step S19: calculating the ratio of the preset efficiency value to the actual efficiency value as an efficiency compensation value; calculating the product of the efficiency compensation value and the input power value of the matcher as a target input power value;
step S20: the target input power is taken as the target power value, and the process proceeds to step S12.
According to the matcher output power debugging method provided by the embodiment, the input power and the output power of the matcher are directly detected, the efficiency compensation value is calculated according to the preset efficiency value, the input power of the matcher is adjusted according to the efficiency compensation value, the input power of the matcher can be accurately adjusted, the debugging times can be reduced, the resources for debugging can be reduced, the debugging time is shortened, and the debugging cost can be reduced.
Example 2
The present embodiment provides a debugging system for debugging the output power of a matcher, as shown in fig. 6, which includes a power detection unit 2 and a control unit 1.
The power detection unit 2 is configured to detect an input power value of an input end of the matcher 4 and an output power value of an output end of the matcher 4 when the radio frequency power supply 3 is turned on, and send the input power value and the output power value of the matcher 4 to the control unit 1. In some embodiments, when the matcher 4 is applied to the field of semiconductor processing, the input end of the matcher 4 is electrically connected to the output end of the radio frequency power supply 3, and at this time, the input power value of the input end of the matcher 4 is the output power value of the radio frequency power supply 3; the output terminal of the matching unit 4 is electrically connected to a component (e.g., a lower electrode) in the process chamber 5, so as to match the output power of the matching unit 4 into the process chamber 5.
The control unit 1 is configured to calculate an actual efficiency value of the matcher 4, where the actual efficiency value is equal to a ratio of an input power value and an output power value of the matcher 4, and specifically, the ratio may be used as the actual efficiency value of the matcher 4.
The control unit 1 is further used for judging whether the actual efficiency value is within a preset efficiency range or not, if not, calculating an efficiency compensation value, wherein the efficiency compensation value is equal to the ratio of the preset efficiency value to the actual efficiency value, and controlling the radio frequency power supply 3 to adjust the input power of the input end of the matcher 4 according to the efficiency compensation value, so that the input power of the matcher 4 can be accurately adjusted, thereby the actually required output power of the matcher 4 can be obtained after the adjustment for a few times is carried out, the times of debugging can be reduced, further, resources for debugging can be reduced, the debugging time is shortened, and the debugging cost is reduced. In some embodiments, the control unit 1 may employ a controller capable of performing logic operations, such as an upper computer (PC), or the control unit 1 may be integrated with the detection unit 2 on a controller capable of performing logic operations, such as a lower computer (PLC).
In some embodiments, the control unit 1 is further configured to calculate a target input power value, specifically, the target input power value is equal to a product of the efficiency compensation value and the input power value; after the target input power value is obtained, the control unit 1 is further configured to control the radio frequency power supply 3 to adjust the input power of the input end of the matcher 4 to the target input power value, and specifically, the radio frequency power supply 3 adjusts the input power of the matcher 4 by adjusting its output power.
In some embodiments, as shown in fig. 7, the power detection unit 2 includes an input power detector 21 and an output power detector 22, wherein the input power detector 21 is used for detecting the input power of the matcher 4, and the output power detector 22 is used for detecting the output power of the matcher 4. Specifically, the input power detector 21 should be connected to the input terminal of the matching unit 4, and the output power detector 22 should be connected to the power output terminal of the matching unit 4.
In some embodiments, the control unit 1 is further configured to determine whether the adjustment number exceeds a preset maximum debugging number, and if not, add 1 to the adjustment number; if so, stopping debugging and sending prompt information indicating calibration of the matcher so as to limit the debugging times and prompt an operator to debug the matcher 4, thereby avoiding the problem of excessive adjusting times due to the fact that the matcher 4 has large debugging errors, and further shortening the debugging time.
In some embodiments, the control unit 1 is further configured to determine whether the input power value of the matcher 4 is within a preset power range, and if so, calculate an actual efficiency value of the matcher 4; if not, prompt information indicating the output power of the radio frequency power supply 3 is sent out to prompt an operator to adjust the output power of the radio frequency power supply 3 (namely, the input power of the matcher 4), so that the problem that the output power of the matcher 4 is in a large difference with the actually required output power due to a large error in the output power of the radio frequency power supply 3 is solved, and the debugging success rate can be improved.
The debugging system that this embodiment provided, through utilizing the output power and the input power of power detecting element detection matcher's output and input, utilize the control unit according to the output power and the input power calculation efficiency compensation value of matcher, and control radio frequency power supply and adjust the matcher input power according to efficiency compensation value, adjust the input power that adjusts the matcher with can comparatively accurately, thereby can reduce the debugging number of times, and then can reduce the resource that is used for the debugging, and shorten the debugging time, reduce the debugging cost.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (10)
1. A matcher output power debugging method, the input of the matcher and the output of the radio frequency power supply are electrically connected, the output of the matcher and the radio frequency power receiving end of a process chamber are electrically connected, characterized by comprising:
when a radio frequency power supply is started, detecting an input power value of an input end of the matcher and an output power value of an output end of the matcher;
calculating an actual efficiency value of the matcher, wherein the actual efficiency value is equal to the ratio of an output power value and an input power value of the matcher;
judging whether the actual efficiency value is within a preset efficiency range, if not, calculating an efficiency compensation value which is equal to the ratio of the preset efficiency value to the actual efficiency value, and adjusting the input power of the matcher according to the efficiency compensation value.
2. The method for debugging output power of a matcher according to claim 1, wherein the adjusting input power of the matcher according to the efficiency compensation value specifically comprises:
calculating a target input power value equal to a product of the efficiency compensation value and an input power value of the matcher;
and adjusting the output power of the radio frequency power supply to the target input power value.
3. The method for debugging matcher output power according to claim 1, further comprising, after determining whether the actual efficiency value is within a preset efficiency range:
judging whether the adjustment times exceed a preset maximum adjustment time, and if so, sending prompt information indicating that the matcher is calibrated;
and if not, adding 1 to the adjusting times.
4. The matcher output power debugging method as claimed in claim 3, further comprising the steps of:
and setting the initial value of the debugging times to be 0 when the radio frequency power supply is started.
5. The method for debugging matcher output power according to claim 1, further comprising, after the step of detecting the input power value at the input end of the matcher and the output power value at the output end of the matcher and before the step of calculating the actual efficiency value of the matcher:
judging whether the input power value of the matcher is within a preset power range or not, and if so, calculating the actual efficiency value of the matcher; if not, sending prompt information indicating that the output power of the radio frequency power supply is calibrated.
6. A debugging system for debugging the output power of a matcher, comprising: a power detection unit and a control unit, wherein,
the power detection unit is used for detecting an input power value of an input end of the matcher and an output power value of an output end of the matcher when the radio frequency power supply is started, and sending the input power value of the matcher and the output power value of the matcher to the control unit;
the control unit is used for calculating the actual efficiency value of the matcher, wherein the actual efficiency value of the matcher is equal to the ratio of the input power value and the output power value of the matcher;
the control unit is further used for judging whether the actual efficiency value is within a preset efficiency range, if not, calculating an efficiency compensation value, wherein the efficiency compensation value is equal to the ratio of the preset efficiency value to the actual efficiency value, and controlling the radio frequency power supply to adjust the input power of the matcher according to the efficiency compensation value.
7. The commissioning system of claim 6, wherein the control unit is further configured to calculate a target input power value, the target input power value being equal to a product of the efficiency compensation value and an input power value of the matcher;
the control unit is further configured to control the radio frequency power supply to adjust the input power of the matcher to the target input power value.
8. The debugging system of claim 6, wherein the power detection unit comprises an input power detector and an output power detector, wherein the input power detector is configured to detect input power at an input of the matcher, and the output power detector is configured to detect output power at an output of the matcher.
9. The debugging system of claim 6, wherein the control unit is further configured to determine whether the adjustment times exceed a preset maximum debugging time, and if so, stop debugging and send a prompt indicating to calibrate the matcher; and if not, adding 1 to the adjusting times.
10. The debugging system of claim 6, wherein the control unit is further configured to determine whether an input power value of the matcher is within a preset power range, and if so, calculate an actual efficiency value of the matcher; if not, sending prompt information indicating that the output power of the radio frequency power supply is calibrated.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5543689A (en) * | 1993-12-27 | 1996-08-06 | Fujitsu Limited | High frequency power source having corrected power output |
| JP2003032064A (en) * | 2001-07-11 | 2003-01-31 | Adtec Plasma Technology Co Ltd | Impedance matching unit with transmission efficiency control function |
| EP1976347A2 (en) * | 2007-03-30 | 2008-10-01 | Tokyo Electron Limited | Plasma processing apparatus, radio frequency generator and correction method therefor |
| CN102820198A (en) * | 2011-06-10 | 2012-12-12 | 东京毅力科创株式会社 | High frequency power distribution device and substrate processing apparatus using same |
| JP2017123214A (en) * | 2016-01-04 | 2017-07-13 | 株式会社日立ハイテクノロジーズ | Plasma processing apparatus |
| WO2020083340A1 (en) * | 2018-10-25 | 2020-04-30 | 北京北方华创微电子装备有限公司 | Power transmission method for radio frequency power supply |
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2021
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|---|---|---|---|---|
| US5543689A (en) * | 1993-12-27 | 1996-08-06 | Fujitsu Limited | High frequency power source having corrected power output |
| JP2003032064A (en) * | 2001-07-11 | 2003-01-31 | Adtec Plasma Technology Co Ltd | Impedance matching unit with transmission efficiency control function |
| EP1976347A2 (en) * | 2007-03-30 | 2008-10-01 | Tokyo Electron Limited | Plasma processing apparatus, radio frequency generator and correction method therefor |
| CN102820198A (en) * | 2011-06-10 | 2012-12-12 | 东京毅力科创株式会社 | High frequency power distribution device and substrate processing apparatus using same |
| JP2017123214A (en) * | 2016-01-04 | 2017-07-13 | 株式会社日立ハイテクノロジーズ | Plasma processing apparatus |
| WO2020083340A1 (en) * | 2018-10-25 | 2020-04-30 | 北京北方华创微电子装备有限公司 | Power transmission method for radio frequency power supply |
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