CN113516234B - Method and device for relieving non-ideal factors of memristor accelerator - Google Patents
Method and device for relieving non-ideal factors of memristor accelerator Download PDFInfo
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Abstract
The application provides a method and a device for relieving non-ideal factors of a memristor accelerator, and belongs to the technical field of electronic information. The method comprises the following steps: acquiring an original weight represented by a floating point value of a convolution layer and/or a full connection layer in the trained neural network, a quantized bit width for mapping weights of all layers and memristor representation precision; quantizing the original weight according to the quantized bit width and the memristor representation precision to obtain a first ideal hardware level weight; mapping the first ideal hardware level weight into the memristor unit to obtain a first non-ideal factor hardware level weight; reconstructing a first non-ideal factor weight represented by a floating point value according to the first non-ideal factor hardware level weight; processing the first non-ideal factor weight to obtain a non-ideal factor weight represented by a floating point value; and obtaining a second ideal hardware level weight according to the non-ideal factor resistant weight, and remapping the second ideal hardware level weight into the memristor unit.
Description
Technical Field
The application belongs to the technical field of electronic information, and particularly relates to a method and a device for relieving non-ideal factors of a memristor accelerator.
Background
Neural network algorithms have achieved breakthrough success in many fields, helping to build the foundation of technologies such as image recognition, target detection, voice recognition, etc. With further increase of the size of the neural network model and gradual sinking to the edge equipment with deployment of the neural network model, the hardware implementation scheme of the neural network calculation simultaneously provides requirements for high calculation power and low power consumption. The memory bottleneck of a conventional von neumann architecture processor places a limit on the computation speed, and the frequent memory required to handle such large-data-scale tasks of the neural network also brings about greater power consumption. The memory pressure can be effectively relieved by considering the low power consumption and high storage density characteristics of the memristors and the in-memory calculation characteristics of the memristor cross array, and the voltage-current relationship of the memristor cross array is highly matched with vector matrix multiplication operation which is used in a large amount by the calculation of the neural network, so that the accelerator constructed by using the memristor cross array replaces a traditional processor to accelerate the calculation of the neural network, and the method is a very competitive scheme.
However, non-ideal factors of such analog circuits as the memristor cross array may seriously affect the reliability of storage and calculation, for example, device Variation (Device Variation) of the memristor, that is, in the manufacturing process of the memristor, due to differences of the Device length and width, oxide thickness and surface roughness, actual resistance values of different resistance states of different memristors deviate from a certain range of standard resistance values of the resistance states correspondingly; for example, a fixed Fault (SAF) of the memristor, namely, the memristor unit is always in a high-resistance state due to factors such as permanent damage of a unit or damage of a selector wire, or is always in a low-resistance state due to defects such as short circuit, so that the memristor cannot be programmed to write a required resistance value; for example, in the memristor resistance drift (Memristance Drift) memristor resistance accelerator calculation process, an input signal may interfere with the memristor resistance state, so that the weight saved by the memristor unit deviates from the target value, and the drift of the memristor resistance may accumulate along with the passage of time. Although neural networks have some fault tolerance, if the weight parameters are simply quantized and mapped directly into memristor cells with non-idealities without any processing, these non-idealities may lead to reduced or even unusable final computation results.
Disclosure of Invention
In view of the foregoing, embodiments of the present invention provide a method and apparatus for mitigating memristive accelerator non-idealities, so as to overcome or at least partially solve the foregoing problems.
In a first aspect of an embodiment of the present invention, a method for mitigating memristor non-idealities is provided, the method including:
acquiring an original weight represented by a floating point value of a convolution layer and/or a full connection layer in the trained neural network, a quantized bit width for mapping weights of all layers and memristor representation precision;
quantizing the original weight according to the quantized bit width and the memristor representation precision to obtain a first ideal hardware level weight; the hardware-level weight characterizes the numerical value and the bit weight of the numerical value which are respectively stored by a single memristor unit or a plurality of memristor units by the integer value after the quantization of the weight parameter;
mapping the first ideal hardware level weight into the memristor unit to obtain a first non-ideal factor hardware level weight;
reconstructing a first non-ideal factor weight represented by a floating point value according to the first non-ideal factor hardware level weight;
processing the first non-ideal factor weight to obtain a non-ideal factor weight represented by a floating point value;
And obtaining a second ideal hardware level weight according to the non-ideal factor resistant weight, and remapping the second ideal hardware level weight into the memristor unit.
Optionally, the method further comprises:
and remapping the second ideal hardware level weight into the memristor unit every preset time and/or every preset calculation times in the operation process of the memristor accelerator.
Optionally, processing the first non-ideal factor weight to obtain a non-ideal factor weight represented by a floating point value, including:
retraining with the first non-ideal factor weight as an initial value of the neural network weight;
and when the first training weight obtained by retraining converges, taking the first training weight as a first non-ideal factor resisting weight.
Optionally, processing the first non-ideal factor weight to obtain a non-ideal factor weight represented by a floating point value, including:
taking the first non-ideal factor weight as an initial value of the neural network weight, and performing back propagation training to obtain a second training weight;
calculating a first offset added in the back propagation training, wherein the first offset is a difference value between the second training weight and the first non-ideal factor weight;
And taking the sum of the original weight and the first offset as a second anti-non-ideal factor weight.
Optionally, processing the first non-ideal factor weight to obtain a non-ideal factor weight represented by a floating point value, including:
retraining with the first non-ideal factor weight as an initial value of the neural network weight;
when the third training weight obtained by retraining converges, obtaining a third ideal hardware level weight according to the third training weight;
mapping the third ideal hardware level weight into the memristor unit to obtain a second non-ideal factor hardware level weight;
reconstructing a second non-ideal factor weight represented by the floating point value according to the second non-ideal factor hardware level weight;
taking the second non-ideal factor weight as an initial value of the neural network weight, and performing back propagation training to obtain a fourth training weight;
calculating a second offset added in the back propagation training, wherein the second offset is a difference value between the fourth training weight and the second non-ideal factor weight;
and taking the sum of the third training weight and the second offset as a third anti-non-ideal factor weight.
Optionally, the quantization processing for the weights includes:
obtaining the maximum value max_abs of the absolute value of the weight represented by the floating point value of the layer;
based on the quantized bit width of the layer, a maximum integer max_int representable by a bit representing the absolute value of the weight is obtained, wherein:
max_int＝2 qbits-1 -1
in the formula, qbits represents the quantization bit width;
obtaining a minimum quantization unit delta, wherein:
quantizing the weight parameter x represented by each floating point value in the layer to a corresponding integer value Q (x), wherein:
in this formula, round () is a rounding function used to convert floating point numbers to integers nearest to it; clip (-) is a truncation function for limiting the range of quantized integers, wherein:
in the T 1 ＝max_int，T 2 ＝-max_int。
Optionally, deriving ideal hardware-level weights from the weight quantization results includes:
for each weight parameter, calculating the number n of memristor units required to map the integer value quantized by the weight parameter, wherein:
in the formula, cbits is the expression precision of the memristor unit; qbits represents the quantization bit width;
calculating a value bitvalue of an ith memristor cell map representing the integer value Q (x) after the quantization of the absolute value of the weight parameter i And the bit weight of the mapped value i Wherein:
bitweight i ＝2 (i-1)*cbits
in this formula, mod is a remainder function, the first parameter p of mod (p, q) is a dividend, and the second parameter q is a divisor, i=1, 2.
Optionally, reconstructing the non-ideal factor weights of the floating point value representation from the non-ideal factor hardware level weights includes:
for each weight parameter, calculating an actual value Qnonideal of the integer value of the quantized absolute value of the weight parameter under the influence of non-ideal factors, wherein:
in this case, the bitvalue_nonideal i A value represented by an ith memristor unit which represents an integer value obtained by quantizing the absolute value of the weight parameter after being influenced by a non-ideal factor; bitweight i And the bit weight of the numerical value represented by the ith memristor unit which represents the integer value after the quantification of the absolute value of the weight parameter.
Calculating a non-ideal factor weight parameter xnonideal represented by the floating point value, wherein:
xnonideal＝Qnonidealsign*Δ
in the formula, qnonideal represents Qnonideal after corresponding signs are added; delta is the minimum quantization unit of the weight parameter during quantization.
In a second aspect of an embodiment of the present invention, there is provided an apparatus for mitigating memristor non-idealities, the apparatus comprising:
the parameter acquisition module is used for acquiring the original weight represented by the floating point value of the convolution layer and/or the full connection layer in the trained neural network, the quantized bit width for mapping the weight of each layer and the memristor representation precision;
The quantization module is used for quantizing the original weight according to the quantization bit width and the memristor representation precision to obtain a first ideal hardware level weight; the hardware-level weight characterizes the numerical value and the bit weight of the numerical value which are respectively stored by a single memristor unit or a plurality of memristor units by the integer value after the quantization of the weight parameter;
the first remapping module is used for mapping the first ideal hardware level weight into the memristor unit to obtain a first non-ideal factor hardware level weight;
the reconstruction module is used for reconstructing the first non-ideal factor weight represented by the floating point value according to the first non-ideal factor hardware level weight;
the processing module is used for processing the first non-ideal factor weight to obtain a non-ideal factor weight represented by a floating point value;
and the second remapping module is used for obtaining a second ideal hardware level weight according to the non-ideal factor resistant weight and remapping the second ideal hardware level weight into the memristor unit.
Optionally, the apparatus further comprises:
and the refreshing module is used for remapping the second ideal hardware level weight into the memristor unit at intervals of preset time and/or at intervals of preset calculation times in the operation process of the memristor.
The embodiment of the invention has the following advantages:
in the embodiment, the original weight represented by the floating point value of the convolution layer and/or the full connection layer in the trained neural network, the quantized bit width for mapping the weight of each layer and the memristor representation precision can be obtained; quantizing the original weight according to the quantized bit width and the memristor representation precision to obtain a first ideal hardware level weight; mapping the first ideal hardware level weight into the memristor unit to obtain a first non-ideal factor hardware level weight; reconstructing a first non-ideal factor weight represented by a floating point value according to the first non-ideal factor hardware level weight; processing the first non-ideal factor weight to obtain a non-ideal factor weight represented by a floating point value; obtaining a second ideal hardware level weight according to the non-ideal factor resisting weight; the second ideal hardware level weight is remapped into the memristor cell. In this way, the tolerance of the weight parameters of the neural network to be mapped to the memristor on the influence of the non-ideal factors of the resistance deviation and the fixed faults can be enhanced to a certain extent, and the influence of the non-ideal factors of the resistance drift accumulation effect is relieved, so that the degree of the accuracy degradation of the neural network caused by the non-ideal factors is reduced.
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In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of steps of a method for mitigating memristive accelerator non-idealities in an embodiment of the present disclosure;
FIG. 2 is a flow chart of the steps of a back propagation training scheme in an embodiment of the present invention;
FIG. 3 is a flow chart of steps of a retraining-back propagation training joint scheme in an embodiment of the invention;
FIG. 4 is a schematic diagram of deriving ideal hardware level weights from the weight quantization results and mapping the ideal hardware level weights into memristor cells in an embodiment of the present disclosure;
FIG. 5 is a block diagram of an apparatus for mitigating memristive accelerator non-idealities in an embodiment of the present disclosure.
Detailed Description
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.
The memristor cross array refers to transverse and longitudinal metal wire cross connection, and memristor units with variable resistance values are arranged on connection points. The memristor cross array performs a calculation process in which the current on each column of the cross array is equal to the sum of the products of the input voltages of the columns and the conductance of the corresponding memristor cells. The weight parameters of the convolution layer and/or the full-connection layer in the neural network are generally stored in the memristor unit in a resistor mode, input characteristics are input into the cross array in a voltage mode, and therefore parallelization calculation of the convolution layer or the full-connection layer can be conveniently achieved.
Those skilled in the art should appreciate that the method for relieving the non-ideal factor of the memristor accelerator provided by the present invention is not only suitable for mapping and accelerating the calculation of the convolution layer and/or the full connection layer in the neural network, but also suitable for other calculation requiring the storage of the weight parameter in the form of resistance in the memristor unit. Therefore, the method for relieving the non-ideal factors of the memristor accelerator provided by the invention is not only suitable for relieving the non-ideal factors of the memristor accelerator in the calculation of the convolution layer and/or the full connection layer in the neural network, but also suitable for relieving the non-ideal factors of the memristor accelerator in other calculation.
Referring to fig. 1, a flowchart illustrating steps of a method for mitigating memristive accelerator non-idealities in an embodiment of the present disclosure, as shown in fig. 1, the method for mitigating memristive accelerator non-idealities may specifically include the following steps:
step S110: and obtaining the original weight represented by the floating point value of the convolution layer and/or the full connection layer in the trained neural network, the quantized bit width for mapping the weight of each layer and the memristor representation precision.
The weight parameters of the convolution layer and/or the full connection layer in the neural network are stored in the memristor unit in the form of resistance. Weights for convolutional layers and/or fully-connected layers in the neural network are mapped into a memristor cross array of the memristor accelerator for computation.
Quantization bit width refers to the number of bits of the binary code used when the weights are quantized. According to different weight quantization strategies, the same quantization bit width can be globally and uniformly set, and different quantization bit widths can be set for weights of different convolution layers and full connection layers. In the embodiment of the invention, the most significant bit of the quantized weight is used for representing the positive and negative of the weight value, and the rest bits are used for representing the absolute value of the weight value. The sign of the weight value is represented by a binary 1 or a binary 0, and the embodiment of the present invention is not limited thereto.
The accuracy of the memristor representation refers to the number of bits of a binary number that a single cell of the memristor employed can represent, typically equal to the base-2 logarithm of the discrete resistance state number of the memristor cell. For example, if the memristor cell used has 4 resistance states for representing binary numbers 00, 01, 10, and 11, respectively, the memristor is represented with a log precision 2 4＝2。
Depending on the quantized bit width of the weights and the accuracy of the memristor representation, it may be determined that one weight value needs to be represented by several memristor cells. Specifically, the quantized bit width minus the bit occupied by the highest bit representing positive and negative is divided by the memristor representation precision, and the resulting quotient is rounded up to be the number of memristor cells required.
Step S120: quantizing the original weight according to the quantized bit width and the memristor representation precision to obtain a first ideal hardware level weight; the hardware level weight characterizes the value and the bit weight of the value which are respectively saved by the single memristor units through the integer value quantized by the weight parameter.
And carrying out quantization processing on the original weight according to the quantization bit width, and then obtaining a first ideal hardware level weight according to the memristor representation precision. The hardware level weight characterizes the value and the bit weight of the value which are respectively saved by the single memristor units through the integer value quantized by the weight parameter. The first ideal hardware level weight is the hardware level weight for which the original weight is ideal. The first ideal hardware level weight characterizes the value that the individual memristor cells used to represent the integer value quantized by the respective weight parameter should each store and the bit weight of the stored value when not affected by non-idealities.
Step S130: and mapping the first ideal hardware level weight into the memristor unit to obtain a first non-ideal factor hardware level weight.
It is mapped into the corresponding memristor array according to the positive and negative of the weight. Specifically, positive weights are mapped into memristor cells in the memristor array representing positive, and negative weights are mapped into memristor cells in the memristor array representing negative. Mapping refers to storing weights in memristor cells.
When mapping the first ideal hardware level weight into the memristor cell, the ideal hardware level weight becomes an non-ideal factor hardware level weight because there is a deviation of the actual value stored by the memristor cell from the value that should be stored in the ideal case.
Thus, mapping the first ideal hardware-level weight into the memristor cell results in a first non-ideal-factor hardware-level weight.
Step S140: and reconstructing the first non-ideal factor weight represented by the floating point value according to the first non-ideal factor hardware level weight.
A first non-ideal factor hardware level weight with a non-ideal factor is extracted from the memristor unit and reconstructed into a first non-ideal factor weight represented by a floating point value.
Step S150: and processing the first non-ideal factor weight to obtain the non-ideal factor weight represented by the floating point value.
The reconstructed first non-ideal factor weight is processed to obtain a weight which is expressed by a floating point value and is resistant to the influence of the non-ideal factor, wherein the processing can be processed by adopting a retraining scheme or a back propagation compensation scheme or a retraining-back propagation compensation combined scheme. The processing can be other processing, and the influence of non-ideal factors of the memristor can be relieved as long as the result obtained after the processing is quantized and remapped into the memristor unit.
After the first non-ideal factor weight is processed, a non-ideal factor-resistant weight can be obtained, and the non-ideal factor-resistant weight can be represented by a floating point value.
Step S160: and obtaining a second ideal hardware level weight according to the non-ideal factor resistant weight, and remapping the second ideal hardware level weight into the memristor unit.
After quantization processing is performed on the anti-non-ideal factor weights, second ideal hardware level weights can be obtained. The second ideal hardware level weight is mapped into the memristor cell. The hardware level weight characterizes the value and the bit weight of the value which are respectively saved by the single memristor units through the integer value quantized by the weight parameter. The second ideal hardware-level weight is a hardware-level weight that is ideal against the non-ideal factor weight.
The non-ideal factor resisting weight is obtained after processing, so that the non-ideal factor can be relieved, and correspondingly, the non-ideal factor can be relieved by the second ideal hardware-level weight. Thus, mapping the second ideal hardware-level weights into memristor cells, while affected by non-idealities, has been mitigated in advance.
By adopting the technical scheme of the embodiment of the application, the tolerance of the weight parameters of the neural network to be mapped on the memristor to the influence of the resistance deviation and the fixed fault nonideal factors can be enhanced, so that the degree of accuracy degradation of the neural network caused by the nonideal factors is reduced.
In another embodiment of the present application, the second ideal hardware level weight is remapped into the memristor unit every preset time and/or every preset number of computations during operation of the memristor accelerator.
The sensing current generated by the input signal during the memristor reading or the small current flowing through the memristor in the calculation process can generate tiny disturbance on the resistance state of the memristor, namely memristor value drift, after multiple sensing or calculation operations, the memristor value representing the weight gradually deviates from the original design value, so that the memristor unit is refreshed by programming and writing the second ideal hardware-level weight into the memristor unit every preset time and/or every preset calculation time during the operation of the memristor accelerator, correction is performed before the weight error stored by the memristor is overlarge, and the reliability of the weight in the calculation process is ensured.
By adopting the technical scheme of the embodiment of the application, the second ideal hardware level weight is not required to be obtained by head calculation every time, but only the second ideal hardware level weight is required to be calculated once, and then the second ideal hardware level weight is mapped into the memristor unit every preset time and/or every preset calculation times, so that the non-ideal factor influence of the resistance drift accumulation effect caused by the operation of the memristor accelerator is relieved, and the degree of accuracy degradation of the neural network is reduced.
In another embodiment of the present application, the processing the first non-ideal factor weight to obtain a non-ideal factor weight represented by a floating point value includes:
step S210: and retraining by taking the first non-ideal factor weight as an initial value of the neural network weight.
The first non-ideal factor weight is a weight influenced by the non-ideal factors of the memristor unit, and is used as an initial value of the neural network weight to be retrained. During retraining, training and updating all weight parameters can be selected; it is also possible to choose to fix those weight parameters that are affected by SAF (stuck-at fault) non-idealities, and only train and update those weight parameters that are not affected by SAF factors. The first training weight obtained after training is equivalent to carrying correction data to a certain extent. Therefore, the non-ideal factors can be relieved by mapping the trained first training weight into the memristor unit.
Step S220: and when the first training weight obtained by retraining converges, taking the first training weight as a first non-ideal factor resisting weight.
And when the first training weight obtained by retraining is converged, ending the retraining process to obtain the trained converged first training weight. And taking the trained converged first training weight as a first non-ideal factor resisting weight, wherein the first non-ideal factor resisting weight is the non-ideal factor resisting weight.
By adopting the technical scheme of the embodiment of the application, namely adopting the retraining scheme to process the first non-ideal factor weight, after being influenced by the non-ideal factor, the parameters of the neural network come to a new position in the hyperspace formed by the neural network, and retraining is actually to find a local optimal solution of the weight parameters near the new position in the hyperspace. Depending on the adaptivity of the neural network training, retraining may be embodied as the network may weaken the weighting of those parameters that are greatly affected by non-idealities during the training process, and adjust the parameters to accommodate the situation where certain parameters affected by fixed faults are redirected to 0 or maximum.
Referring to fig. 2, a flowchart illustrating a step of processing the first non-ideal factor weight to obtain a non-ideal factor weight represented by a floating point value, which is referred to as a back propagation training scheme, is shown in another embodiment, where the method may specifically include the following steps as shown in fig. 2:
Step S310: and taking the first non-ideal factor weight as an initial value of the neural network weight, and performing back propagation training to obtain a second training weight.
And taking the first non-ideal factor weight as an initial value of the neural network weight, and performing one or a few times of back propagation training to obtain a second training weight. During back propagation training, training and updating all weight parameters can be selected; it is also possible to choose to fix those weight parameters that are affected by SAF (stuck-at fault) non-idealities, and only train and update those weight parameters that are not affected by SAF factors.
Step S320: and calculating a first offset added in the back propagation training, wherein the first offset is a difference value between the second training weight and the first non-ideal factor weight.
The first offset is added in the back propagation training, where the first offset is a difference between the second training weight and the first non-ideal factor weight, and specifically, the first offset is a difference obtained by subtracting the first non-ideal factor weight from the second training weight.
Step S330: and taking the sum of the original weight and the first offset as a second anti-non-ideal factor weight.
And adding the first offset to the original weight to obtain a second non-ideal factor resisting weight, wherein the second non-ideal factor resisting weight is the non-ideal factor resisting weight.
By adopting the technical scheme of the embodiment of the application, namely adopting the back propagation training scheme to process the weight of the first non-ideal factor, after being influenced by the non-ideal factor, the accuracy of the neural network is reduced, the weight parameter of the neural network comes to a new position from a home position in a hyperspace formed by the neural network, and then the influence of the non-ideal factor on the weight parameter is expressed as the offset of the new position relative to the home position in the hyperspace formed by the weight parameter, namely the non-ideal offset. After the weight affected by the non-ideal factors is trained by single-step or few steps of back propagation, the parameters are updated from the new position to another new position in the hyperspace, and the accuracy of the neural network is improved at the moment, so that the offset from the other new position to the new position can be considered as offset compensation, and the influence of a part of non-ideal factors can be compensated. Therefore, the compensation offset can be added to the weight parameter before the neural network is mapped to the memristor, and the influence of non-ideal factors after mapping can be partially counteracted.
Referring to fig. 3, a flowchart illustrating a step of processing the first non-ideal factor weight to obtain a non-ideal factor weight represented by a floating point value, which is referred to as a retraining-back propagation training combination scheme, in another embodiment, may specifically include the following steps as shown in fig. 3:
step S410: and retraining by taking the first non-ideal factor weight as an initial value of the neural network weight.
The first non-ideal factor weight is a weight influenced by the non-ideal factors of the memristor unit, and is used as an initial value of the neural network weight to be retrained. During retraining, training and updating all weight parameters can be selected; it is also possible to choose to fix those weight parameters that are affected by SAF (stuck-at fault) non-idealities, and only train and update those weight parameters that are not affected by SAF factors. The third training weight obtained after training is equivalent to carrying correction data to a certain extent.
Step S420: when the third training weight obtained by retraining converges, obtaining a third ideal hardware level weight according to the third training weight;
And when the third training weight obtained by retraining is converged, ending the retraining process to obtain the trained converged third training weight. And quantizing the third training weight, and obtaining a third ideal hardware level weight according to the quantized third training weight and the memristor representation precision.
Step S430: and mapping the third ideal hardware level weight into the memristor unit to obtain a second non-ideal factor hardware level weight.
And mapping the third ideal hardware level weight into the memristor unit, wherein the third ideal hardware level weight is influenced by non-ideal factors of the memristor unit, and the second non-ideal factor hardware level weight can be obtained.
Step S440: reconstructing a second non-ideal factor weight represented by the floating point value according to the second non-ideal factor hardware level weight.
And extracting a second non-ideal factor hardware level weight with the non-ideal factor from the memristor unit, and reconstructing the second non-ideal factor hardware level weight into a second non-ideal factor weight represented by a floating point value.
Step S450: and taking the second non-ideal factor weight as an initial value of the neural network weight, and performing back propagation training to obtain a fourth training weight.
And taking the second non-ideal factor weight as an initial value of the neural network weight, and performing one or a few times of back propagation training to obtain a fourth training weight. During back propagation training, training and updating all weight parameters can be selected; it is also possible to choose to fix those weight parameters that are affected by SAF (stuck-at fault) non-idealities, and only train and update those weight parameters that are not affected by SAF factors.
Step S460: and calculating a second offset added in the back propagation training, wherein the second offset is a difference value between the fourth training weight and the second non-ideal factor weight.
A second offset is added to the back propagation training, where the second offset is a difference between the fourth training weight and the second non-ideal factor weight, and specifically, the second offset is a difference obtained by subtracting the second non-ideal factor weight from the fourth training weight.
Step S470: and taking the sum of the third training weight and the second offset as a third anti-non-ideal factor weight.
And adding a second offset to the third training weight to obtain a third anti-non-ideal factor weight, wherein the third anti-non-ideal factor weight is the anti-non-ideal factor weight.
By adopting the technical scheme of the embodiment of the application, namely adopting the retraining-back propagation training combined scheme to process the weight of the first non-ideal factor, on one hand, the retraining can be specifically expressed as that the network can weaken the weight of parameters greatly influenced by the non-ideal factor in the training process according to the self-adaptability of the neural network training, and the parameters are adjusted to adapt to the situation that certain parameters influenced by fixed faults are redirected to 0 or the maximum value; on the other hand, the influence of a part of non-ideal factors can be compensated, the compensation offset is added to the weight parameters before the neural network is mapped to the memristor, and the influence of the non-ideal factors after the mapping can be counteracted by a part.
In another embodiment of the present application, the quantization processing for the weights includes:
step S510: the maximum value max_abs of the absolute value of the weight represented by the layer floating point value is obtained.
One convolutional layer or one fully-connected layer contains multiple weights. The maximum value max_abs of the absolute value of the weight represented by the floating point value of the layer is the absolute value of the weight with the largest absolute value of the weight represented by the floating point value in the layer.
Step S520: based on the quantized bit width of the layer, a maximum integer max_int representable by a bit representing the absolute value of the weight is obtained, wherein:
max_int＝2 qbits-1 -1
in this equation, qbits represents the quantization bit width.
Since the most significant bit of the quantized bits represents the weight sign, the remaining bits represent the weight absolute value.
Step S530: obtaining a minimum quantization unit delta, wherein:
step S540: quantizing the weight parameter x represented by each floating point value in the layer to a corresponding integer value Q (x), wherein:
in this formula, round () is a rounding function used to convert floating point numbers to integers nearest to it; clip (-) is a truncation function for limiting the range of quantized integers, wherein:
in the T 1 ＝max_int，T 2 ＝-max_int。
The technical scheme of the embodiment of the application is suitable for carrying out quantization processing on any weight, such as original weight, anti-non-ideal factor weight and third training weight. Any weight needs to be quantized, and the technical scheme of the embodiment of the application can be adopted.
In another embodiment of the present application, obtaining ideal hardware-level weights from the weight quantization results includes:
step S610: for each weight parameter, calculating the number n of memristor units required to map the integer value quantized by the weight parameter, wherein:
in the formula, cbits is the expression precision of the memristor unit; qbits is the quantization bit width.
Step S620: calculating a value bitvalue of an ith memristor cell map representing the integer value Q (x) after the quantization of the absolute value of the weight parameter i And the bit weight of the mapped value i Wherein:
bitweight i ＝2 (i-1)*cbits
in this formula, mod is a remainder function, the first parameter p of mod (p, q) is a dividend, the second parameter q is a divisor, i=1, 2, n; the cbits is the expression precision of the memristor unit; the meaning of other parameters in the formula is consistent with the previous.
Referring to fig. 4, a schematic diagram of obtaining an ideal hardware level weight from a weight quantization result and mapping the hardware level weight into memristor units in an embodiment of the present invention is shown, where a binary integer after the absolute value quantization of the weight represents 8 bits in total, and each memristor represents 2 bits of binary number, that is, the precision of the representation of the memristor unit is 2, so that 4 memristor units are required to map the weight into the memristor unit. The values of the corresponding mappings in the hardware level weights are stored in each memristor cell in the form of resistors. The ideal hardware level weight stored in each memristor cell becomes the non-ideal hardware level weight, affected by memristor non-ideal factors.
In another embodiment of the present application, reconstructing non-ideal factor weights of a floating point value representation from non-ideal factor hardware level weights includes:
step S710: for each weight parameter, calculating an actual value Qnonideal of the integer value of the quantized absolute value of the weight parameter under the influence of non-ideal factors, wherein:
in this case, the bitvalue_nonideal i A value represented by an ith memristor unit which represents an integer value obtained by quantizing the absolute value of the weight parameter after being influenced by a non-ideal factor; bitweight i Bit weights for values represented by the ith memristor cell representing the integer values quantized by the weight parameter absolute values; n is the number of memristor cells used to hold the absolute value of the weight.
Step S720: calculating a non-ideal factor weight parameter xnonideal represented by the floating point value, wherein: xnonitdeal=qnonidesign × Δ
In the formula, qnonideal represents Qnonideal after corresponding signs are added; delta is the minimum quantization unit of the weight parameter during quantization.
And adding signs to the quantized value Qnonideal with non-ideal factors according to the positive and negative values of the weights to obtain signed Qnonideal.
The non-ideal factor weight represented by the floating point value is a set of non-ideal factor weight parameters xnonideal represented by the floating point value.
The technical scheme of the embodiment of the application is suitable for reconstructing the weight of the floating point value representation according to the weight of any hardware level.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
FIG. 5 is a block diagram of an apparatus for mitigating memristive accelerator non-idealities, as shown in FIG. 5, may include: a parameter acquisition module 510, a quantization module 520, a first remapping module 530, a reconstruction module 540, a processing module 550, a second remapping module 560, wherein:
The parameter obtaining module 510 is configured to obtain an original weight represented by a floating point value of a convolutional layer and/or a full-connection layer in the trained neural network, a quantization bit width mapped to the weight of each layer, and memristor representation accuracy;
the quantization module 520 is configured to quantize the original weight according to the quantization bit width and the memristor representation precision, to obtain a first ideal hardware level weight; the hardware-level weight characterizes the numerical value and the bit weight of the numerical value which are respectively stored by a single memristor unit or a plurality of memristor units by the integer value after the quantization of the weight parameter;
a first remapping module 530, configured to map the first ideal hardware level weight into the memristor unit, to obtain a first non-ideal factor hardware level weight;
a reconstruction module 540, configured to reconstruct the first non-ideal factor weight represented by the floating point value according to the first non-ideal factor hardware level weight;
a processing module 550, configured to process the first non-ideal factor weight to obtain a non-ideal factor weight represented by a floating point value;
and a second remapping module 560, configured to obtain a second ideal hardware level weight according to the anti-non-ideal factor weight, and remap the second ideal hardware level weight into the memristor unit.
As can be seen from the above embodiments, in this embodiment, the weight parameters of the neural network to be mapped onto the memristive accelerator can be enhanced, and tolerance to the effects of resistance offset and fixed-type fault non-ideal factors can be reduced, so as to reduce the degree of degradation of the neural network accuracy caused by the non-ideal factors.
In another embodiment of the present application, an apparatus 500 for mitigating memristive accelerator non-idealities further includes a refresh module 570.
And the refreshing module is used for remapping the second ideal hardware level weight into the memristor unit at intervals of preset time and/or at intervals of preset calculation times in the operation process of the memristor.
As can be seen from the foregoing embodiments, in this embodiment, the second ideal hardware level weight does not need to be calculated from the header each time, but only needs to be calculated once, and then the second ideal hardware level weight is mapped into the memristor unit every preset time and/or every preset number of calculations, so as to alleviate the non-ideal factor influence of the resistance drift accumulation effect caused by the operation of the memristor accelerator, thereby reducing the degree of accuracy degradation of the neural network.
Optionally, as an embodiment, the processing module 550 may specifically further include the following submodules:
The first retraining sub-module is used for retraining by taking the first non-ideal factor weight as an initial value of the neural network weight;
and the first convergence sub-module is used for converging the first training weight obtained through retraining and taking the first training weight as a first non-ideal factor resisting weight.
Optionally, as an embodiment, the processing module 550 may specifically further include the following submodules:
the first back propagation training sub-module is used for performing back propagation training by taking the first non-ideal factor weight as an initial value of the neural network weight to obtain a second training weight;
the first offset quantum module is used for calculating a first offset added in the back propagation training, wherein the first offset is a difference value between the second training weight and the first non-ideal factor weight;
and the first adding sub-module is used for taking the sum of the original weight and the first offset as a second anti-non-ideal factor weight.
Optionally, as an embodiment, the processing module 550 may specifically further include the following submodules:
the second retraining sub-module is used for retraining by taking the first non-ideal factor weight as an initial value of the neural network weight;
The second convergence training submodule is used for converging the third training weight obtained through retraining and obtaining a third ideal hardware-level weight according to the third training weight;
a remapping sub-module, configured to map the third ideal hardware level weight into the memristor unit, to obtain a second non-ideal factor hardware level weight;
a reconstruction sub-module, configured to reconstruct a second non-ideal factor weight represented by a floating point value according to the second non-ideal factor hardware level weight;
the second back propagation training sub-module is used for performing back propagation training by taking the second non-ideal factor weight as an initial value of the neural network weight to obtain a fourth training weight;
the second offset quantum module is used for calculating a second offset added in the back propagation training, wherein the second offset is a difference value between the fourth training weight and the second non-ideal factor weight;
and the second adding sub-module is used for taking the sum of the third training weight and the second offset as a third anti-non-ideal factor weight.
Optionally, as an embodiment, the apparatus 500 for mitigating memristive accelerator non-ideality may further include a general quantization module, where the general quantization module is configured to:
Obtaining the maximum value max_abs of the absolute value of the weight represented by the floating point value of the layer;
based on the quantized bit width of the layer, a maximum integer max_int representable by a bit representing the absolute value of the weight is obtained, wherein:
max_int＝2 qbits-1 -1
in the formula, qbits represents the quantization bit width;
obtaining a minimum quantization unit delta, wherein:
quantizing the weight parameter x represented by each floating point value in the layer to a corresponding integer value Q (x), wherein:
/>
in this formula, round () is a rounding function used to convert floating point numbers to integers nearest to it; clip (-) is a truncation function for limiting the range of quantized integers, wherein:
in the T 1 ＝max_int，T 2 ＝-max_int。
Optionally, as an embodiment, the apparatus 500 for mitigating memristive accelerator non-ideality may further include a hardware-level weight obtaining module, where the hardware-level weight obtaining module is configured to:
for each weight parameter, calculating the number n of memristor units required to map the integer value quantized by the weight parameter, wherein:
in the formula, cbits is the expression precision of the memristor unit; qbits represents the quantization bit width;
calculating a value bitvalue of an ith memristor cell map representing the integer value Q (x) after the quantization of the absolute value of the weight parameter i And the bit weight of the mapped value i Wherein:
bitweight i ＝2 (i-1)*cbits
in this formula, mod is a remainder function, the first parameter p of mod (p, q) is a dividend, and the second parameter q is a divisor, i=1, 2.
Optionally, as an embodiment, the apparatus 500 for mitigating memristive accelerator non-ideality may further include a general reconstruction module, where the general reconstruction module is configured to:
for each weight parameter, calculating an actual value Qnonideal of the integer value of the quantized absolute value of the weight parameter under the influence of non-ideal factors, wherein:
in this case, the bitvalue_nonideal i A value represented by an ith memristor unit which represents an integer value obtained by quantizing the absolute value of the weight parameter after being influenced by a non-ideal factor; bitweight i And the bit weight of the numerical value represented by the ith memristor unit which represents the integer value after the quantification of the absolute value of the weight parameter.
Calculating a non-ideal factor weight parameter xnonideal represented by the floating point value, wherein:
xnonideal＝Qnonidealsign*Δ
in the formula, qnonideal represents Qnonideal after corresponding signs are added; delta is the minimum quantization unit of the weight parameter during quantization.
It should be noted that, the device embodiment is similar to the method embodiment, so the description is simpler, and the relevant places refer to the method embodiment.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods and apparatus according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The above detailed description of the method and the device for relieving the non-ideal factors of the memristor provided by the present invention applies specific examples to illustrate the principles and the embodiments of the present invention, and the above examples are only used to help understand the method and the core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (10)
1. A method of mitigating memristive accelerator non-idealities, the method comprising:
acquiring an original weight represented by a floating point value of a convolution layer and/or a full connection layer in the trained neural network, a quantized bit width for mapping weights of all layers and memristor representation precision;
quantizing the original weight according to the quantized bit width and the memristor representation precision to obtain a first ideal hardware-level weight, including: calculating the number of memristor units required by the integer value quantized by each weight parameter of the original weight according to the quantized bit width and the memristor representation precision, calculating the value mapped by each memristor unit representing the integer value quantized by the absolute value of each weight parameter of the original weight, and the bit weight of the mapped value; the hardware-level weight characterizes the numerical value and the bit weight of the numerical value which are respectively stored by a single memristor unit or a plurality of memristor units by the integer value after the quantization of the weight parameter;
mapping the first ideal hardware level weight into the memristor unit to obtain a first non-ideal factor hardware level weight;
reconstructing a first non-ideal factor weight represented by a floating point value according to the first non-ideal factor hardware level weight, including: calculating the actual value of the quantized integer value of the absolute value of each weight parameter of the first non-ideal factor hardware level weight under the influence of the non-ideal factor; calculating a first non-ideal factor weight parameter represented by the floating point value according to the actual value and a minimum quantization unit of each weight parameter of the first non-ideal factor hardware level weight during quantization; determining the first non-ideal factor weight according to the first non-ideal factor weight parameter;
Processing the first non-ideal factor weight to obtain a non-ideal factor weight represented by a floating point value;
and obtaining a second ideal hardware level weight according to the non-ideal factor resistant weight, and remapping the second ideal hardware level weight into the memristor unit.
2. The method according to claim 1, wherein the method further comprises:
and remapping the second ideal hardware level weight into the memristor unit every preset time and/or every preset calculation times in the operation process of the memristor accelerator.
3. The method of claim 1, wherein processing the first non-ideal factor weight to obtain a non-ideal factor-resistant weight represented by a floating point value comprises:
retraining with the first non-ideal factor weight as an initial value of the neural network weight;
and when the first training weight obtained by retraining converges, taking the first training weight as a first non-ideal factor resisting weight.
4. The method of claim 1, wherein processing the first non-ideal factor weight to obtain a non-ideal factor-resistant weight represented by a floating point value comprises:
Taking the first non-ideal factor weight as an initial value of the neural network weight, and performing back propagation training to obtain a second training weight;
calculating a first offset added in the back propagation training, wherein the first offset is a difference value between the second training weight and the first non-ideal factor weight;
and taking the sum of the original weight and the first offset as a second anti-non-ideal factor weight.
5. The method of claim 1, wherein processing the first non-ideal factor weight to obtain a non-ideal factor-resistant weight represented by a floating point value comprises:
retraining with the first non-ideal factor weight as an initial value of the neural network weight;
when the third training weight obtained by retraining converges, obtaining a third ideal hardware level weight according to the third training weight;
mapping the third ideal hardware level weight into the memristor unit to obtain a second non-ideal factor hardware level weight;
reconstructing a second non-ideal factor weight represented by the floating point value according to the second non-ideal factor hardware level weight;
taking the second non-ideal factor weight as an initial value of the neural network weight, and performing back propagation training to obtain a fourth training weight;
Calculating a second offset added in the back propagation training, wherein the second offset is a difference value between the fourth training weight and the second non-ideal factor weight;
and taking the sum of the third training weight and the second offset as a third anti-non-ideal factor weight.
6. The method of any of claims 1-5, wherein quantizing the weights comprises:
obtaining the maximum value max_abs of the absolute value of the weight represented by the floating point value of the layer;
based on the quantized bit width of the layer, a maximum integer max_int representable by a bit representing the absolute value of the weight is obtained, wherein:
max_int＝2 qbits-1 -1
in the formula, qbits represents the quantization bit width;
obtaining a minimum quantization unit delta, wherein:
quantizing the weight parameter x represented by each floating point value in the layer to a corresponding integer value Q (x), wherein:
in this formula, round () is a rounding function used to convert floating point numbers to integers nearest to it; clip (-) is a truncation function for limiting the range of quantized integers, wherein:
in the T 1 ＝max_int，T 2 ＝-max_int。
7. The method of any of claims 1-5, wherein deriving ideal hardware-level weights from the weight quantization results comprises:
For each weight parameter, calculating the number n of memristor units required to map the integer value quantized by the weight parameter, wherein:
in the formula, cbits is the expression precision of the memristor unit; qbits represents the quantization bit width;
calculating a value bitvalue of an ith memristor cell map representing the integer value Q (x) after the quantization of the absolute value of the weight parameter i And the bit weight of the mapped value i Wherein:
bitweight i ＝2 (i-1)*cbits
in this equation, mod is a remainder function, the first parameter p of mod (p, q) is a dividend, and the second parameter q is a divisor, i=1, 2, …, n.
8. The method of any of claims 1-5, wherein reconstructing the non-ideal factor weights of the floating point value representation from the non-ideal factor hardware level weights comprises:
for each weight parameter, calculating an actual value Qnonideal of the integer value of the quantized absolute value of the weight parameter under the influence of non-ideal factors, wherein:
in this case, the bitvalue_nonideal i A numerical value represented by an ith memristor unit which represents an integer value obtained by quantizing the absolute value of the weight parameter after being influenced by non-ideal factors; bitweight i Bit weights of the numerical values represented by the ith memristor unit representing the integer values after the quantization of the absolute values of the weight parameters;
Calculating a non-ideal factor weight parameter xnonideal represented by the floating point value, wherein:
xnonideal＝Qnonidealsign*Δ
in the formula, qnonideal represents Qnonideal after corresponding signs are added; delta is the minimum quantization unit of the weight parameter during quantization.
9. An apparatus for mitigating memristive accelerator non-idealities, the apparatus comprising:
the parameter acquisition module is used for acquiring the original weight represented by the floating point value of the convolution layer and/or the full connection layer in the trained neural network, the quantized bit width for mapping the weight of each layer and the memristor representation precision;
the quantization module is configured to quantize the original weight according to the quantization bit width and the memristor representation precision, and obtain a first ideal hardware-level weight, and includes: calculating the number of memristor units required by the integer value quantized by each weight parameter of the original weight according to the quantized bit width and the memristor representation precision, calculating the value mapped by each memristor unit representing the integer value quantized by the absolute value of each weight parameter of the original weight, and the bit weight of the mapped value; the hardware-level weight characterizes the numerical value and the bit weight of the numerical value which are respectively stored by a single memristor unit or a plurality of memristor units by the integer value after the quantization of the weight parameter;
The first remapping module is used for mapping the first ideal hardware level weight into the memristor unit to obtain a first non-ideal factor hardware level weight;
a reconstruction module, configured to reconstruct a first non-ideal factor weight represented by a floating point value according to the first non-ideal factor hardware level weight, including: calculating the actual value of the quantized integer value of the absolute value of each weight parameter of the first non-ideal factor hardware level weight under the influence of the non-ideal factor; calculating a first non-ideal factor weight parameter represented by the floating point value according to the actual value and a minimum quantization unit of each weight parameter of the first non-ideal factor hardware level weight during quantization; determining the first non-ideal factor weight according to the first non-ideal factor weight parameter;
the processing module is used for processing the first non-ideal factor weight to obtain a non-ideal factor weight represented by a floating point value;
and the second remapping module is used for obtaining a second ideal hardware level weight according to the non-ideal factor resistant weight and remapping the second ideal hardware level weight into the memristor unit.
10. The apparatus of claim 9, wherein the apparatus further comprises:
And the refreshing module is used for remapping the second ideal hardware level weight into the memristor unit at intervals of preset time and/or at intervals of preset calculation times in the operation process of the memristor.
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