CN113515474A

CN113515474A - Data processing apparatus, method, computer device, and storage medium

Info

Publication number: CN113515474A
Application number: CN202110875105.1A
Authority: CN
Inventors: 张启荣; 王文强; 徐宁仪
Original assignee: Shanghai Power Tensors Intelligent Technology Co Ltd
Current assignee: Shanghai Power Tensors Intelligent Technology Co Ltd
Priority date: 2021-07-30
Filing date: 2021-07-30
Publication date: 2021-10-19
Also published as: WO2023005352A1

Abstract

The present disclosure provides a data processing apparatus, a method, a computer device, and a storage medium, wherein the apparatus includes: a data reading component, a data buffer component and a data storage component; the data reading component is in communication connection with the data caching component, and the data caching component is in communication connection with the data storage component; a read data component for determining a read data request for the data storage component; the data reading request comprises a first data address corresponding to data to be read; and determining the data storage state of the data to be read in a preset data cache component based on the first data address, indicating that the data cache component stores effective data to be read in response to the data storage state, and acquiring the data to be read from the data cache component. The embodiment of the disclosure can reduce the access power consumption and avoid the waste of resources.

Description

Data processing apparatus, method, computer device, and storage medium

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to a data processing apparatus, a data processing method, a computer device, and a storage medium.

Background

With the development of Artificial Intelligence technology, AI (Artificial Intelligence) chips are increasingly widely used. The AI algorithm and the application scenario that are continuously iterated also have higher and higher requirements on an AI chip PPA (performance, Power consumption, Area). In an end-side device, particularly, a mobile device, control of power consumption is important for a certain performance.

In the process of data processing by using the AI chip, the data reading module needs to access a data address of the random access memory RAM to acquire data stored in the RAM. With the increase of the data reading module and the increase of the access times, a large amount of memory access power consumption is generated, and resource waste is caused.

Disclosure of Invention

The embodiment of the disclosure at least provides a data processing device, a data processing method, computer equipment and a storage medium, so as to reduce the access power consumption.

In a first aspect, an embodiment of the present disclosure provides a data processing apparatus, including: a data reading component, a data buffer component and a data storage component; the data reading component is in communication connection with the data caching component, and the data caching component is in communication connection with the data storage component;

the data reading component is used for determining a data reading request aiming at the data storage component; the data reading request comprises a first data address corresponding to data to be read; and determining the data storage state of the data to be read in a preset data cache component based on the first data address, responding to the data storage state indicating that effective data to be read is stored in the data cache component, and acquiring the data to be read from the data cache component.

Whether effective data to be read is stored in the data cache component or not can be determined based on the data storage state of the data to be read corresponding to the first data address in the preset data cache component. Because the power consumption of the access data cache part is lower than that of the access data storage part (such as RAM), under the condition that effective data to be read is stored in the data cache part, the data to be read can be directly obtained from the data cache part without obtaining the data to be read from the data storage part, and the access power consumption for obtaining the data to be read is reduced. In addition, aiming at the condition that the same RAM data address needs to be repeatedly accessed for a plurality of times or in a short time, the data cache component is utilized to store the data to be read, the data to be read can be directly obtained from the data cache component every time, and the data to be read does not need to be obtained from the data storage component every time, so that the access power consumption is greatly reduced, and the waste of resources is effectively avoided.

In a possible implementation, the data reading unit is further configured to, in response to the data storage status indicating that valid data to be read does not exist in the data cache unit, obtain the data to be read from the data storage unit based on the read data request and the first data address.

In a possible embodiment, the data processing apparatus further comprises a data writing unit, the data writing unit is connected to the data buffering unit and the data storage unit in communication;

the write data component to determine a first write data request for the data storage component; the first data writing request comprises first data to be written and a second data address of the first data to be written; and updating the data storage state of the valid data corresponding to the second data address to an invalid state if it is determined that the valid data corresponding to the second data address is stored in the data cache part based on the second data address; and storing the first data to be written at a position corresponding to the second data address in the data storage unit based on the first data writing request.

In a possible implementation manner, the first write data request further includes first write cache information;

the data writing part is configured to update the data storage status of the valid data corresponding to the second data address to an invalid status when it is determined that the valid data corresponding to the second data address is stored in the data caching part based on the second data address and the first write cache information indicates that the first data to be written does not need to be cached in the data caching part.

the write data unit is used for determining a second write data request aiming at the data storage unit; the second data writing request comprises second data to be written and a third data address of the second data to be written;

under the condition that the data cache part is determined to store valid data corresponding to the third data address based on the third data address, the valid data corresponding to the third data address is updated to be the second data to be written;

and storing the second data to be written at a position corresponding to a third data address in the data storage part based on the second data writing request.

In a possible implementation manner, the second write data request further includes second write cache information;

the data writing component is configured to update the valid data corresponding to the third data address to the second data to be written when it is determined that the valid data corresponding to the third data address is stored in the data caching component and the second write caching information indicates that the second data to be written needs to be cached in the data caching component based on the third data address.

In a possible implementation, the data processing apparatus further comprises a priority determining component, the priority determining component is in communication connection with the data caching component and the data storage component;

the data access component is used for determining the data storage state of the data to be read corresponding to the data read request in the corresponding data cache component based on the first data address corresponding to the data read request for each data read request in the data access requests under the condition that a plurality of data access requests for the data storage component are determined; the data access component comprises a read data component and/or a write data component;

screening target read data requests meeting preset conditions from the read data requests based on the data storage state; the preset condition comprises that effective data to be read does not exist in a data cache component corresponding to the data reading request;

determining the access priority of each target access request by using a preset priority determining part under the condition that the number of the target access requests is larger than the preset number; the number of the target access requests is determined according to the number of the target read data requests and/or the number of write data requests in the plurality of data access requests;

and sequentially accessing the data storage component based on the access priority of each target access request.

In one possible implementation, the data caching component includes a plurality of cache subcomponents corresponding to each respective data access component.

In a possible embodiment, the data access unit is configured to set target read data requests having the same first data address to the same access priority by using a preset priority determination unit.

In one possible implementation, the read data request includes third write cache information;

the data reading component is further configured to, after the data to be read is acquired from the data storage component, store the data to be read based on a latest address to be written corresponding to the data cache component when it is determined that the third write cache information indicates that the data to be read needs to be cached in the data cache component;

and setting the data storage state of the stored data to be read as a valid state.

In a second aspect, an embodiment of the present disclosure provides a data processing method, including:

determining a read data request for a target memory; the data reading request comprises a first data address corresponding to data to be read;

determining the data storage state of the data to be read in a preset data cache module based on the first data address;

and responding to the data storage state to indicate that the data cache module stores effective data to be read, and acquiring the data to be read from the data cache module.

In one possible embodiment, the method further comprises:

and responding to the data storage state indicating that no effective data to be read exists in the data cache module, and acquiring the data to be read from the target memory based on the data reading request and the first data address.

In one possible embodiment, the method further comprises:

determining a first write data request for a target memory; the first data writing request comprises first data to be written and a second data address of the first data to be written;

under the condition that the data caching module is determined to store valid data corresponding to the second data address based on the second data address, updating the data storage state of the valid data corresponding to the second data address to be an invalid state;

and storing the first data to be written at a position corresponding to the second data address in the target memory based on the first data writing request.

the updating the data storage state of the valid data corresponding to the second data address to an invalid state includes:

and updating the data storage state of the valid data corresponding to the second data address to be an invalid state when it is determined that the valid data corresponding to the second data address is stored in the data cache module and the first write cache information indicates that the first data to be written does not need to be cached in the data cache module based on the second data address.

In one possible embodiment, the method further comprises:

determining a second write data request for the target memory; the second data writing request comprises second data to be written and a third data address of the second data to be written;

under the condition that the data caching module is determined to store valid data corresponding to the third data address based on the third data address, the valid data corresponding to the third data address is updated to be the second data to be written;

and storing the second data to be written at a position corresponding to a third data address in the target memory based on the second data writing request.

the updating the valid data corresponding to the third data address to the second data to be written includes:

and updating the valid data corresponding to the third data address to the second data to be written when it is determined that the data caching module stores the valid data corresponding to the third data address and the second write caching information indicates that the second data to be written needs to be cached in the data caching module based on the third data address.

In one possible embodiment, the method further comprises:

under the condition that a plurality of data access requests for a target memory are determined, determining the data storage state of data to be read corresponding to the data access requests in a corresponding data cache module according to a first data address corresponding to the data access request for each data access request in the data access requests;

screening target read data requests meeting preset conditions from the read data requests based on the data storage state; the preset condition comprises that effective data to be read does not exist in a data cache module corresponding to the data reading request;

under the condition that the number of the target access requests is larger than the preset number, determining the access priority of each target access request by using a preset priority determining module; the number of the target access requests is determined according to the number of the target read data requests and/or the number of write data requests in the plurality of data access requests;

and sequentially accessing the target memory based on the access priority of each target access request.

In one possible implementation, the data caching module includes a plurality of caching sub-modules respectively corresponding to each data access module; the data access module comprises a data reading module and a data writing module.

In a possible embodiment, the determining the access priority of each target access request by using a preset priority determination module includes:

and setting target read data requests with the same first data address to be the same access priority by using a preset priority determining module.

after the data to be read is obtained from the target memory, the method further comprises the following steps:

under the condition that the third write cache information indicates that the data to be read needs to be cached in the data cache module, storing the data to be read based on the latest address to be written corresponding to the data cache module;

In a third aspect, an alternative implementation manner of the present disclosure also provides a computer device, including the apparatus in the first aspect described above, or any one of the possible implementation manners of the first aspect.

In a fourth aspect, alternative implementations of the present disclosure also provide a computer-readable storage medium having a computer program stored thereon, the computer program being executable by a processor to perform the steps of the second aspect described above, or any one of the possible implementations of the second aspect.

For the description of the effects of the data processing method, the data processing apparatus, the computer device, and the computer-readable storage medium, reference is made to the description of the data processing apparatus in the first aspect, and details are not repeated here.

In order to make the aforementioned objects, features and advantages of the present disclosure more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly described below, and the drawings herein incorporated in and forming a part of the specification illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the technical solutions of the present disclosure. It is appreciated that the following drawings depict only certain embodiments of the disclosure and are therefore not to be considered limiting of its scope, for those skilled in the art will be able to derive additional related drawings therefrom without the benefit of the inventive faculty.

Fig. 1 shows a flow chart of a data processing method provided by an embodiment of the present disclosure;

FIG. 2 is a schematic diagram illustrating a read data module accessing a data address in a data cache module according to an embodiment of the present disclosure;

FIG. 3 is a flow chart illustrating a method of data writing provided by an embodiment of the present disclosure;

FIG. 4 is a flow chart illustrating a method for processing a determined plurality of data access requests provided by an embodiment of the present disclosure;

fig. 5 is a schematic diagram illustrating that multiple read data modules provided by an embodiment of the present disclosure access data to be read at data addresses in a data cache module independently from each other;

fig. 6 is a schematic diagram illustrating that multiple read data modules provided by an embodiment of the present disclosure access data to be read at data addresses in a data cache module in an interleaving manner;

FIG. 7 is a schematic diagram of a data processing apparatus provided by an embodiment of the present disclosure;

fig. 8 shows a schematic structural diagram of a computer device provided by an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. The components of embodiments of the present disclosure, as generally described and illustrated herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present disclosure is not intended to limit the scope of the disclosure, as claimed, but is merely representative of selected embodiments of the disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the disclosure without making creative efforts, shall fall within the protection scope of the disclosure.

Furthermore, the terms "first," "second," and the like in the description and in the claims, and in the drawings described above, in the embodiments of the present disclosure are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein.

Reference herein to "a plurality or a number" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

Research shows that along with the development of Artificial Intelligence technology, AI (Artificial Intelligence) chips are more and more widely applied. The AI algorithm and the application scenario that are continuously iterated also have higher and higher requirements on an AI chip PPA (Performance, Power consumption, Area). In an end-side device, particularly, a mobile device, control of power consumption is important for a certain performance. In the process of data processing by using the AI chip, the data reading module needs to access a data address of the random access memory RAM to acquire data stored in the RAM. With the increase of the data reading module and the increase of the access times, a large amount of memory access power consumption is generated, and resource waste is caused.

Based on the above research, the present disclosure provides a data processing apparatus, a data processing method, a computer device, and a storage medium, which can determine whether valid data to be read is stored in a data cache module based on a data storage state of the data to be read corresponding to a first data address in the preset data cache module. Because the power consumption of the access data cache module is lower than that of the access target memory (for example, RAM), under the condition that effective data to be read is stored in the data cache module, the data to be read can be directly obtained from the data cache module without obtaining the data to be read from the target memory, and the access power consumption for obtaining the data to be read is reduced. In addition, aiming at the condition that the same RAM data address needs to be repeatedly accessed for multiple times continuously or in a short time, the data to be read is stored by the data cache module, the data to be read can be directly obtained from the data cache module every time, and the data to be read does not need to be obtained from the target memory every time, so that the access power consumption is greatly reduced, and the waste of resources is effectively avoided.

The defects found by the above researches are the results of the inventor after practice and careful study, therefore, the discovery process of the above problems and the solutions proposed by the present disclosure to the above problems in the following should be the contribution of the inventor to the present disclosure in the process of the present disclosure.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

To facilitate understanding of the present embodiment, a data processing method disclosed in the embodiments of the present disclosure is first described in detail, where an execution subject of the data processing method provided in the embodiments of the present disclosure is generally a computer device with certain computing capability, and in some possible implementations, the data processing method may be implemented by a processor calling a computer-readable instruction stored in a memory.

The data processing method provided by the embodiment of the present disclosure is described below by taking an execution subject as a computer device as an example.

As shown in fig. 1, a flowchart of a data processing method provided in an embodiment of the present disclosure may include the following steps:

s101: and determining a read data request aiming at the target memory, wherein the read data request comprises a first data address corresponding to the data to be read.

Here, the target memory may be a random access memory RAM in a chip (hereinafter, an AI chip is taken as an example, and other types of chips may also be applicable to the scheme provided by the present disclosure, which is not described herein again), and different data addresses in the RAM may be used for storing different data, and may also be used for writing new data.

The read data request may be a request to obtain data in the target memory, the first data address is a certain data address in the target memory, and the data to be read is data stored at the first data address in the target memory.

In specific implementation, the read data request for the target memory may be determined by any read data module having an access requirement based on a first data address corresponding to the to-be-read data to be acquired, or the read data request may be generated by the user side based on the first data address under the condition that the to-be-read data corresponding to the first data address needs to be acquired, and the read data request is sent to the read data module in the AI chip, and then the read data module determines according to the received read data request. There is no limitation on how the read data request is determined.

S102: and determining the data storage state of the data to be read in a preset data cache module based on the first data address.

Here, the preset data caching module may be a first-level Cache, for example, a Register, or may be a Cache memory, specifically, a Cache represented by L0. The data cache module is used for caching the data addresses and the data to be read corresponding to the data addresses, and during specific implementation, the data cache module can be provided with a limited data storage space and used for storing a limited number of data addresses and the data to be read corresponding to the data addresses. The setting of the data storage space of the data cache module can be set according to the application scene.

And the data stored in the data cache module can be updated according to the access and storage requirements of different data reading modules and the data to be read acquired by the data reading module which currently initiates the data reading request.

In addition, because the data storage space of the data cache module is limited and the data in the data cache module can be updated, in the process of data processing by using the AI chip, there may be a case where the target memory is frequently accessed and the accessed data addresses include a plurality of addresses, and if the data addresses accessed each time are different, the valid data and data address cached in the data caching module will not match the data to be read corresponding to the read data request each time, therefore, the method provided by the embodiment of the present disclosure can be applied to the case where the same RAM data address needs to be accessed for a plurality of times in succession or repeatedly accessed for a short time, and thus, the data cache module can ensure that effective data stored in the data cache module can be matched with data to be read corresponding to the data reading request, so that the memory access power consumption of the data reading module during memory access is reduced.

The data storage state is used for representing whether an effective first data address and corresponding data to be read are stored in a preset data cache module. In a specific implementation, the data storage state may include a valid state indicating that a valid first data address and data to be read corresponding to the valid first data address exist in the data cache module, an invalid state indicating that the first data address and data to be read corresponding to the valid first data address exist, and a state indicating that the first data address and data to be read corresponding to the invalid first data address do not exist in the data cache module.

The read data module can comprise a plurality of modules, and each read data module can initiate a read data request aiming at different data addresses in the RAM.

One data reading module can be correspondingly provided with one data caching module, and different data reading modules are correspondingly provided with different data caching modules. Fig. 2 is a schematic diagram illustrating a read data module accessing a data address in a data cache module according to an embodiment of the present disclosure. The system comprises a data reading module, a read module and a Register, wherein Rd _ mdl represents the data reading module and is used for initiating a data reading request, cupen represents an identifier representing third write Cache information and is used for indicating whether data to be read and read from a target memory need to be written into the data Cache module, rden represents read enable of the data reading module, raddr represents a data address in the data reading request and corresponds to a first data address, and rdata represents the read data to be read, can be data read from an L0Cache/Register, and can also be data read from the target memory; the L0Cache represents a preset data Cache module, the Register may also represent a preset data Cache module, and different symbols may be used to represent the data Cache module according to different settings of the data Cache module, but L0Cache/Register may both be used to represent the data Cache module, RAM _ rden represents the target memory read enable, RAM _ raddr represents a first data address corresponding to the target memory in the read data request, RAM _ rdata represents the data to be read obtained from the target memory, RAM represents the target memory, Wr _ mdl represents a write data module in the data processing apparatus, wren represents the write enable of the write data module, waddr represents a data address in the write data request, and wdata represents the data to be written.

In specific implementation, after any Rd _ mdl with access requirements determines a data reading request, Rd _ mdl is enabled to have the data reading capability through rden, and then the data storage state of data to be read corresponding to raddr in the data reading request in the L0Cache/Register can be determined. And under the condition that the data storage state indicates that effective data to be read is stored in the L0Cache/Register, directly acquiring the data rdata to be read from the L0 Cache/Register.

Under the condition that the data storage state indicates that no valid data to be read is stored in the L0Cache/Register, the Rd _ mdl may have the capability of reading data from the RAM through RAM _ rden, and then the data to be read, corresponding to RAM _ raddr, RAM _ rdata may be read from the RAM by using raddr in the data reading request as RAM _ raddr, so that the data to be read, RAM _ rdata, may be acquired from the RAM by Rd _ mdl.

For the write data module Wr _ mdl, after any write data request is determined by Wr _ mdl with a write data requirement, Wr _ mdl can have the capacity of writing data wdata to be written into the RAM through wren, and then wdata can be written into the RAM at waddr corresponding to the write data request. Also, after going through wren, Wr _ mdl also has the ability to write wdata into waddr in L0Cache/Register, or wdata and waddr may be written directly into L0 Cache/Register.

For S102, a mapping relationship exists between data addresses stored in the data cache module, data corresponding to the data addresses, and data storage states of the data corresponding to the data addresses. After the data reading module acquires the first data address, the data reading module can also determine each data address stored in the data caching module, and further determine whether a data address matched with the first data address exists in each data address, if so, the data storage state of the data corresponding to the matched data address can be determined according to the mapping relation, and if not, the data storage state can be directly determined to be the data to be read does not exist.

Furthermore, the same data cache module may be correspondingly arranged in a plurality of data reading modules. In specific implementation, the setting may be performed according to a data address correspondingly accessed by the data reading module, or may be performed based on a user requirement, which is not limited herein. For example, in a case where each of the plurality of data reading modules can access the data to be read at the data address in the RAM independently from each other, a corresponding data cache module may be provided for each data reading module; under the condition that each read data module in the plurality of read data modules has the data to be read at the data address in the mutually crossed access RAM, the same data cache module can be correspondingly arranged for the plurality of read data modules, wherein the mutually crossed access can be used for indicating the plurality of read data modules to access the same data address at certain access times at intervals so as to obtain the condition of the data to be read.

In this step, after determining the data read request, the data read module may determine, based on the first data address in the data read request and the data cache module corresponding to the data read request, a data storage state of the data to be read corresponding to the first data address in the data cache module.

S103: and responding to the data storage state indication that the data cache module stores effective data to be read, and acquiring the data to be read from the data cache module.

Here, when it is determined that valid data to be read is stored in the data cache module based on the data storage state, that is, when it is determined that the data state corresponding to the data to be read in the data cache module is a valid state, the data read module may directly obtain the data to be read at the first data address from the data cache module.

And then, the data reading module can perform data processing based on the acquired data to be read, and can also send the acquired data to be read to the user side, so that the user side acquires the data to be read and performs data processing based on the data to be read.

Therefore, whether effective data to be read is stored in the data cache module or not can be determined based on the data storage state of the data to be read corresponding to the first data address in the preset data cache module. Because the power consumption of the access data cache module is lower than that of the access target memory (for example, RAM), under the condition that effective data to be read is stored in the data cache module, the data to be read can be directly obtained from the data cache module without obtaining the data to be read from the target memory, and the access power consumption for obtaining the data to be read is reduced. In addition, aiming at the condition that the same RAM data address needs to be repeatedly accessed for multiple times continuously or in a short time, the data to be read is stored by the data cache module, the data to be read can be directly obtained from the data cache module every time, and the data to be read does not need to be obtained from the target memory every time, so that the access power consumption is greatly reduced, and the waste of resources is effectively avoided.

In another embodiment, when it is determined that valid data to be read does not exist in the data cache module based on the data storage state, that is, it is determined that the first data address and the data to be read corresponding to the first data address do not exist in the data cache module, or it is determined that the data storage state corresponding to the data to be read is an invalid state, the target memory may be directly accessed based on the read data request and the first data address corresponding to the read data address, and the data corresponding to the first data address is directly read from the target memory and is used as the data to be read, so that the data to be read corresponding to the read data request may be acquired.

Therefore, even if the data cache module is determined not to have effective data to be read, the data to be read stored in the target memory can be obtained in a mode of directly accessing the target memory, and each data reading request can be ensured to be responded to obtain the required data to be read.

In one embodiment, the request to the target memory may also include a write data request determined by the Wr _ mdl module in fig. 2, which may enable data writing to the target memory based on the write data request. In specific implementation, data writing may be performed on the target memory according to the steps shown in fig. 3, and as shown in fig. 3, a flowchart of a data writing method provided for the embodiment of the present disclosure may include the following steps:

s301: a first write data request to a target memory is determined.

The first data writing request includes first data to be written and a second data address of the first data to be written, where the second data address is a data address in the target memory, and specifically may be a data address in the RAM.

In particular implementation, when there is a need to write data into the target memory, the Wr _ mdl module may determine a first request for writing data to the target memory based on a first data address to be written and a second data address to be written.

S302: and updating the data storage state of the valid data corresponding to the second data address to be an invalid state under the condition that the data cache module is determined to store the valid data corresponding to the second data address based on the second data address.

Here, after determining the first write data request, the write data module may determine whether the second data address and its corresponding valid data are cached in the data cache module based on the second data address. If so, the state of the data corresponding to the second data address in the data cache module may be updated to an invalid state. In a specific implementation, the state of the data may be updated to an invalid state. In this way, new data needs to be written into the second data address of the target memory, so that the data at the second data address of the target memory changes, the data corresponding to the second data address stored in the data cache module is already inaccurate, and the state of the data is updated to be an invalid state, so that the situation that the data which is not updated in the data cache module is fed back when a new read data request including the second data address is acquired can be prevented, and the accuracy of the fed-back data is improved.

S303: and storing the first data to be written in the target memory at a position corresponding to the second data address based on the first data writing request.

In this step, after the first data writing request is determined, the target memory may be accessed directly based on the first data writing request and the second data address, and the first data to be written is written in a position corresponding to the second data address of the target memory.

If the position corresponding to the second data address has the previously stored data, the previously stored data can be updated by using the first data to be written, and the data at the position corresponding to the second data address is updated to be the first data to be written. Or, if no data exists at the position corresponding to the second data address, the first data to be written may be directly stored at the position corresponding to the second data address.

In addition, in specific implementation, S303 and S302 may be executed synchronously or asynchronously, where both the synchronous execution and the asynchronous execution may be used to update the data storage state of the valid data corresponding to the second data address in the data cache module to an invalid state but not update the data, but the asynchronous execution may also be used to update the data storage state corresponding to the second data address in the data cache module first and then write the first data to be written into the target memory.

In one embodiment, the first write data request further includes first write cache information. The first write cache information is used for indicating whether the first to-be-written data corresponding to the first write data request needs to be used for updating valid data corresponding to the second data address stored in the data cache module.

For S302, when it is determined that the second data address and the valid data corresponding to the second data address are stored in the data cache module based on the second data address, it is determined whether the valid data corresponding to the second data address in the data cache module needs to be updated by using the first data to be written, that is, it is determined whether the first data to be written needs to be cached in the data cache module again based on the first write cache information, and if not, the data storage state of the valid data corresponding to the second data address in the data cache module may be updated to be the invalid state. If so, the first data to be written can be directly written at the second data address in the data cache module, and the state of the first data to be written is not required to be updated.

In another embodiment, in the case that the request for the target memory includes a request for writing data, the writing of data to the target memory may also be implemented as follows:

step one, a second data writing request aiming at the target memory is determined.

The second data writing request comprises second data to be written and a third data address of the second data to be written.

And step two, under the condition that the data caching module is determined to store effective data corresponding to the third data address based on the third data address, the effective data corresponding to the third data address is updated to be second data to be written.

In this step, when it is determined that the third data address and the corresponding valid data are stored in the data cache module based on the third data address, the valid data may be updated to the second data to be written. Therefore, when a new read data request including the third data address is acquired, the updated second data to be written (i.e. the data to be read) can be directly acquired from the data cache module, and the updated data to be read can be acquired without accessing the target memory, so that the access power consumption is reduced.

And thirdly, storing the second data to be written in the position corresponding to the third data address in the target memory based on the second data writing request.

For the specific implementation step of step three, reference may be made to S303, which is not described herein again.

In an embodiment, the second write data request further includes second write cache information, where the second write cache information is used to indicate whether it is necessary to update valid data corresponding to the third data address stored in the data cache module with second to-be-written data corresponding to the second write data request.

For the second step, under the condition that it is determined that valid data corresponding to the third data address is stored in the data cache module based on the third data address, it is determined whether valid data corresponding to the third data address in the data cache module needs to be updated by using second data to be written, that is, it is determined whether the second data to be written needs to be cached in the data cache module again based on the second write cache information, and if so, the valid data corresponding to the second data address in the data cache module may be updated to the second data to be written.

The first write cache information and the second write cache information are information for indicating whether to cache the data to be written in the data request in the data cache module.

In an embodiment, the data processing method provided by the embodiment of the present disclosure further includes a step of processing a plurality of data access requests obtained synchronously, where the data access requests may be initiated by the data access module and include a read data request and a write data request, the read data request is initiated by the read data module, and the write data request is initiated by the write data module. As shown in fig. 4, a flowchart of a method for processing a plurality of determined data access requests provided by an embodiment of the present disclosure may include the following steps:

s401: under the condition that a plurality of data access requests for the target memory are determined, for each data access request in the data access requests, the data storage state of the data to be read corresponding to the data access request in the corresponding data cache module is determined based on the first data address corresponding to the data access request.

Here, in the process of data processing using the AI chip, there may be a case where a plurality of data access modules (including a data read module and a data write module) simultaneously determine and initiate a data access request for accessing the target memory, and the target memory can only satisfy the requirement of reading or writing data corresponding to one data address at the same time.

Therefore, when a plurality of data access requests for the target memory are determined, the data access requests may include a read data request and a write data request, and for the write data request, the purpose is to write data to be written into the target memory.

For the read data requests, under the condition that valid data is stored in the data cache module, the data can be directly obtained from the data cache module without accessing the target memory, so that under the condition that a plurality of read data requests for the target memory are determined, the data requests need to be screened first, and the target read data requests needing to access the target memory are selected.

In specific implementation, for each read data request, the data storage state of the data to be read corresponding to the read data request in the corresponding data cache module is determined based on the first data address in the read data request.

Here, if the read data module corresponding to each of the obtained multiple data access requests can access the data address in different address intervals of the target memory independently, the data cache module may include multiple cache sub-modules. Each cache submodule corresponds to one read data module, and the specific arrangement of the cache submodule is shown in fig. 5. As shown in fig. 5, a schematic diagram of a multi-read data module provided in the embodiment of the present disclosure, where the multi-read data module accesses data to be read at a data address in a data cache module independently from each other. In fig. 5, Rd _ mdl0 to Rd _ mdln represent different read data modules, and fig. 5 shows only an Rd _ mdl0 read data module, an Rd _ mdl1 read data module, and an Rd _ mdln read data module, and the remaining read data modules are not shown. L0_0 indicates a preset cache submodule corresponding to Rd _ mdl0, which can be used for caching data corresponding to the first data address in the read data request determined by Rd _ mdl0, L0_1 indicates a preset cache submodule corresponding to Rd _ mdl1, L0_1 indicates a preset cache submodule corresponding to Rd _ mdl1, L0_ n indicates a preset cache submodule corresponding to Rd _ mdln, and cache submodules corresponding to other read data modules are not shown. Moreover, the write data module Wr _ mdl in fig. 5 may correspond to each cache submodule, and wren/addr corresponding to each cache submodule represents write enable of the write data module and write data to a data address corresponding to addr of the cache submodule. In the case that the write data module includes a plurality of write data modules, each write data module may also correspond to one cache submodule, specifically, one read data module, one write data module, and one cache submodule constitute one module group, and the read data module and the write data module in the module group both correspond to the cache submodule in the module group and are responsible for reading and writing data of a data address in a specific range in the target memory.

In another embodiment, if it is determined that the read data modules corresponding to each of the multiple data access requests access the data address of the target memory in an intersecting manner, only one data cache module corresponding to the multiple read data modules may be set, and in a specific implementation, the setting of the data cache module may refer to fig. 6. As shown in fig. 6, a schematic diagram of a multi-read data module provided in an embodiment of the present disclosure, which accesses data to be read at a data address in a data cache module in an interleaving manner. L0 denotes a data buffer module corresponding to a plurality of read data modules Rd _ mdl0 to Rd _ mdln and write data module Wr _ mdl.

Here, the data storage state of the data to be read corresponding to each read data request may be determined from the data cache module (or cache submodule) corresponding to each read data request based on the manner (mutually independent access or mutually cross access) of the target memory accessed by the read data module corresponding to each read data request.

S402: and screening target data reading requests meeting preset conditions from the data reading requests based on the data storage state.

The preset condition comprises that valid data to be read does not exist in a data cache module corresponding to the data reading request.

Here, for each read data request, whether valid data to be read is stored in the data cache module (or the data cache submodule) may be determined based on the determined data storage state corresponding to the data to be read corresponding to the read data request, and if so, the valid data to be read may be fed back to the data read module corresponding to the data.

And if not, sending the read data request as a target read data request to the target memory for processing. Here, the obtained plurality of read data requests may be filtered according to the determined data storage state, and the target access request determined to meet the preset condition may be filtered.

That is, a target read data request for which valid data to be read does not exist in the data cache module (or the cache submodule) corresponding to the read data request is screened out from the plurality of read data requests.

S403: and under the condition that the number of the target access requests is larger than the preset number, determining the access priority of each target access request by using a preset priority determining module.

The target access request comprises a target read data request and/or a write data request in a plurality of data access requests; the number of target access requests is determined based on the number of target read data requests and/or the number of write data requests in the plurality of data access requests.

Here, the preset priority determination module is used to determine the access priority of each target access request. In particular, the priority determining module may be an Arbiter, and in fig. 5 and 6, the priority determining module may be denoted by Arbiter.

After the target read data requests are screened out, the number of the target read data requests may be determined, the number of write data requests in the plurality of data access requests may be determined, the sum of the number of the target read data requests and the determined number of the write data requests may be used as the number of the target access requests, and then whether the number is greater than a preset number, where the preset number may be 1. As can be seen from the above description of the embodiments, the target memory can only satisfy the requirement of reading or writing data corresponding to one data address at the same time, and therefore, if the number of target access requests for the target memory is greater than 1, it is not possible to process two target access requests synchronously. Therefore, it is necessary to separately process a plurality of target access requests, that is, to determine the access priority of each target access request, so it is possible to determine whether the access priority of the target access request needs to be determined using a preset number.

Here, if there is no read data request among the plurality of data access requests, the number of target read data requests may be set to 0 by default.

In addition, in the process of determining the number of target read data requests, it may also be determined that there are target read data requests of the same first data address based on the first data address in each target read data request, and then, the last number corresponding to the target read data requests may be determined based on the number of target read data requests having the same first data address and the number of target access requests of which the first data addresses are different. In specific implementation, no matter how many target read data requests with the same first data address are, in the process of determining the number of the target read data requests, the number is calculated as 1.

Here, since the data to be read that needs to be acquired by the target read data requests having the same first data address are the same, after responding to one target read data request, the data to be read stored in the target memory can be acquired, and then the data to be read can be sent to the read data module corresponding to each target read data request having the same first data address, so that each read data module can acquire the needed data to be read synchronously. Therefore, in determining the number of target access requests, the number of target read data requests having the same first data address may be calculated as 1.

Further, when it is determined that the number of the target access requests is greater than the preset number, each target access request may be arbitrated by using a preset priority determining module (i.e., an arbiter) to determine the access priority of each target access request, and further, each target access request may be sequentially responded based on the access order corresponding to the determined access priority.

Regarding determining the access priority of each target access request, the following ways may be included, but not limited to: firstly, the arbiter can be used to determine the access priority of each target access request according to the module function of the data access module corresponding to each target access request. And secondly, determining the access priority of each target access request by using the arbiter according to the position of the first data address corresponding to the target read data request in each target access request and the write data address corresponding to the write data request. And thirdly, determining the access priority of each target access request by using the arbiter according to the identifier which is carried in each target access request and used for representing the importance degree of the request. And fourthly, the access priority is preset.

In one example, the priority determination module may set the priority of each target access request to the same priority for each target access request having the same first data address.

In fig. 5 and 6, ram _ rdif 0-ram _ rdif may be arbitration signals issued by their corresponding data access modules, ram _ rdif0 represents arbitration signals for arbitrating target access requests from Rd _ mdl0 to access the target memory, ram _ rdif represents arbitration signals for arbitrating target access requests from Rd _ mdln to access the target memory, and arbitration signals for arbitrating target access requests from Rd _ mdln to access the target memory are not shown, and are all denoted by ram _ rdif … …. Arbiters denote pre-set priority determination modules (arbiters). The data access module corresponding to each target access request may simultaneously send an arbitration signal to the priority determination module, and then the priority determination module may determine the access priority of the target access request corresponding to each arbitration signal according to the obtained arbitration signal.

In specific implementation, after the arbiter receives a plurality of arbitration signals at the same time, that is, according to the received arbitration signals, the arbiter determines the access priority of the target access request corresponding to each arbitration signal, and then, according to the determined access priority, sequentially connects the data access interface of the target memory to the data access module corresponding to each target access request, and then, each data access module can read or write data from or into the target memory based on the connected data access interface.

In addition, if the priority determining module receives a new arbitration signal in the process of determining the access priority of the target access request corresponding to each acquired arbitration signal, the newly acquired arbitration signal can be stored into a preset arbitration queue according to the generation time of the newly acquired arbitration signal, and when the priority determining module completes the current arbitration, the new arbitration signal is acquired from the arbitration queue according to the sequence of the generation time to perform the new arbitration.

The arbitration process of the arbiter will be described by taking a plurality of read data modules Rd _ mdl 0-Rd _ mdln shown in fig. 5 as an example. When it is determined that a plurality of read data modules Rd _ mdl 0-Rd _ mdln send out a plurality of read data requests for a target memory, and data storage states of data to be read corresponding to the plurality of read data requests in each of cache sub-modules L0_ 0-L0 _ n indicate that valid data to be read is not stored, the plurality of read data modules Rd _ mdl 0-Rd _ mdln may send arbitration signals to an arbiter, wherein Rd _ mdl0 requests arbitration to the arbiter by generating and sending an ram _ rdif0 arbitration signal, Rd _ mdl1 requests arbitration to the arbiter by generating and sending an ram _ rdif1 signal, Rd _ mdln requests arbitration to the arbiter by generating and sending a ram _ rdif arbitration signal, and details about an arbitration process initiated by Rd _ md 2-Rd _ mdn-1 are repeated. Thus, the arbiter may receive a plurality of arbitration signals ram _ rdif 0-ram _ rdifn, and further, the arbiter may arbitrate the read data requests corresponding to each arbitration signal to determine the access priority of each read data request. Then, each read data request can sequentially acquire the data to be read from the target memory according to the determined access priority.

S404: the target memory is accessed in turn based on the access priority of each target access request.

Here, for each target data reading request in the target access requests, the priority determining module may sequentially establish a connection between the data reading module corresponding to each target data reading request and the data access interface of the target memory according to the determined access priority of each target data reading request, and further, each data reading module may access the target memory by using the data access interface based on the first data address of the corresponding target data reading request, thereby sequentially obtaining the data to be read corresponding to each target data reading request from the target memory.

And if a plurality of target read data requests with the same access priority exist, when responding to a target read data request corresponding to the access priority, randomly responding to any one of the plurality of target read data requests corresponding to the access priority, establishing connection between a read data module corresponding to the target read data request and a target data access interface, and further, the read data module can access a target memory by using the data access interface based on a first data address corresponding to the target read data request, so as to acquire data to be read at the first data address in the target memory.

For each write data request in the target access request, based on the determined access priority of each write data request, the connection between the write data module corresponding to each write data request and the data access interface is sequentially established, so that each write data module writes the data to be written corresponding to the write data request into the target memory by using the data access interface.

In an embodiment, if the request for the target memory synchronously obtained includes a read data request and a write data request, the arbiter may be first used to determine an access priority corresponding to the write data request, then sequentially write the data to be written corresponding to the write data request into the target memory, and then sequentially obtain the data to be read from the target memory based on the determined access priority of the read data request. Alternatively, the arbiter may be directly utilized to determine the access priority of each read data request and the whole of each write data request, and based on the determined access priority, the operations of reading the data to be read from the target memory and writing the data to be written into the target memory may be completed.

In an embodiment, the read data request may further include third write cache information, where the third write cache information is used to indicate whether the data to be read, which is obtained from the target memory, needs to be cached in the data cache module. For example, the third write cache information may be identified by cupen in fig. 2, 5, and 6, for example, when cupen is set to 1, it indicates that the acquired data to be read may be cached in the data cache module, and when cupen is set to 0, it indicates that the acquired data to be read may not be cached in the data cache module. The value corresponding to the cupen identifier can be determined by the data reading module corresponding to the identifier according to the corresponding access and storage requirements.

In specific implementation, after the data to be read is acquired from the target memory, whether the data to be read needs to be cached in the data caching module or not can be determined based on the third write caching information in the read data request corresponding to the data to be read. If so, determining whether the data cache module stores the stored data placed in the invalid state corresponding to the first data address corresponding to the data to be read, if so, updating the stored data placed in the invalid state to the data to be read, completing updating the data corresponding to the first data address in the data cache module, and setting the data storage state of the updated data to be read to a valid state, for example, to a valid state.

Or, under the condition that it is determined that the stored data corresponding to the first data address corresponding to the data to be read is not stored in the data cache module, determining whether the storage space of the data cache module is used up, if not, selecting the lowest idle address from the cache addresses corresponding to the remaining space of the data cache module, caching the first data address and the data to be read corresponding to the first data address in the lowest idle address, and setting the data storage state of the data to be read to be an effective state. If the data cache module does not have a usable storage space, determining a latest address to be written corresponding to the data cache module, wherein the latest address to be written is used for representing the address which can be used for storing the data address and the data corresponding to the data address by the data cache module at the current time. And updating the data corresponding to the latest address to be written into the first data address and the data to be read corresponding to the first data address, and setting the data storage state of the data to be read into an effective state.

The latest address to be written may be determined by performing address increment on the address, which is used for storing the data address and the data corresponding to the data address, of the data cache module last time according to an address increment mode. And when the address in the data cache module is used for storing the data and the data address, if the address for storage is the highest address in the data cache module, the address for storage next time is looped back to the lowest address in the data cache module, so that the storage time of the data and the data address which are stored corresponding to the latest address to be written determined each time is the longest, and the data which are stored for the longest time are replaced by the currently acquired data to be read, thereby ensuring the timeliness of the effective data stored in the data cache module.

The above-mentioned each judgment step related to caching the acquired data to be read in the data cache module by using the third write cache information can be executed synchronously.

In addition, an embodiment of the present disclosure provides a data processing apparatus corresponding to the data processing method, including: a data reading component, a data buffer component and a data storage component; the data reading component is in communication connection with the data caching component, and the data caching component is in communication connection with the data storage component;

In one embodiment, the data reading unit is further configured to, in response to the data storage status indicating that valid data to be read does not exist in the data cache unit, retrieve the data to be read from the data storage unit based on the read data request and the first data address.

In one embodiment, the data processing apparatus further comprises a data writing component, the data writing component being communicatively coupled to the data caching component and the data storage component;

In one embodiment, the first write data request further includes first write cache information;

In one embodiment, the second write data request further includes second write cache information;

In one embodiment, the data processing apparatus further comprises a priority determining component, the priority determining component being communicatively connected with the data caching component and the data storage component;

In one embodiment, the data caching component includes a plurality of cache subcomponents corresponding to each respective data access component.

In one embodiment, the data access unit is configured to set target read data requests having the same first data address to the same access priority using a preset priority determination unit.

In one embodiment, the read data request includes third write cache information;

Here, the function of the data reading component is the same as that of the data reading module in the foregoing embodiment, the function of the data storage component is the same as that of the target memory in the foregoing embodiment, the function of the data caching component is the same as that of the data caching module in the foregoing embodiment, the function of the data writing component is the same as that of the data writing module in the foregoing embodiment, the function of the priority determining component is the same as that of the priority determining module in the foregoing embodiment, and the function of the data accessing component is the same as that of the data accessing module in the foregoing embodiment.

It will be understood by those skilled in the art that in the method of the present invention, the order of writing the steps does not imply a strict order of execution and any limitations on the implementation, and the specific order of execution of the steps should be determined by their function and possible inherent logic.

Based on the same inventive concept, a data processing apparatus corresponding to the data processing method is also provided in the embodiments of the present disclosure, and because the principle of the apparatus in the embodiments of the present disclosure for solving the problem is similar to the data processing method described above in the embodiments of the present disclosure, the implementation of the apparatus may refer to the implementation of the method, and repeated details are not described again.

As shown in fig. 7, a schematic diagram of a data processing apparatus provided in an embodiment of the present disclosure includes:

a first determining module 701, configured to determine a read data request for a target memory; the data reading request comprises a first data address corresponding to data to be read;

a second determining module 702, configured to determine, based on the first data address, a data storage state of the data to be read in a preset data caching module;

the obtaining module 703 is configured to, in response to the data storage status indicating that the data cache module stores valid data to be read, obtain the data to be read from the data cache module.

In a possible implementation manner, the obtaining module 703 is further configured to, in response to the data storage status indicating that valid data to be read does not exist in the data caching module, obtain the data to be read from the target memory based on the read data request and the first data address.

In a possible implementation, the apparatus further includes a first updating module 704;

the first determining module 701 is further configured to determine a first write data request for a target memory; the first data writing request comprises first data to be written and a second data address of the first data to be written;

the first updating module 704 is configured to update the data storage status of the valid data corresponding to the second data address to an invalid status when it is determined that the valid data corresponding to the second data address is stored in the data caching module based on the second data address;

the first updating module 704 is configured to update the data storage state of the valid data corresponding to the second data address to an invalid state when it is determined that the valid data corresponding to the second data address is stored in the data caching module based on the second data address and the first write caching information indicates that the first data to be written does not need to be cached in the data caching module.

In a possible implementation, the apparatus further comprises a second update module 705;

the first determining module 701 is further configured to determine a second write data request for the target memory; the second data writing request comprises second data to be written and a third data address of the second data to be written;

the second updating module 705 is configured to update the valid data corresponding to the third data address to the second data to be written when it is determined, based on the third data address, that the valid data corresponding to the third data address is stored in the data caching module;

the second updating module 705 is configured to update the valid data corresponding to the third data address to the second data to be written when it is determined that the valid data corresponding to the third data address is stored in the data caching module based on the third data address and the second write caching information indicates that the second data to be written needs to be cached in the data caching module.

In a possible implementation, the apparatus further includes a third determining module 706;

the second determining module 702 is configured to, when multiple data access requests for a target memory are determined, determine, for each data access request in the data access requests, a data storage state of data to be read corresponding to the data access request in a corresponding data cache module based on a first data address corresponding to the data access request;

the third determining module 706 is configured to filter a target read data request meeting a preset condition from the read data requests based on the data storage state; the preset condition comprises that effective data to be read does not exist in a data cache module corresponding to the data reading request;

In a possible implementation manner, the third determining module 706 is configured to set the target read data requests having the same first data address to the same access priority by using a preset priority determining module.

the device further comprises:

a third updating module 707, configured to, after the obtaining module 703 obtains the data to be read from the target memory, store the data to be read based on a latest address to be written corresponding to the data caching module when it is determined that the third write cache information indicates that the data to be read needs to be cached in the data caching module;

The data processing device provided by the embodiment of the disclosure may include a chip, an AI chip, and the like.

The description of the processing flow of each module in the device and the interaction flow between the modules may refer to the related description in the above method embodiments, and will not be described in detail here.

The embodiment of the disclosure also provides a computer device which can comprise the data processing device provided by the embodiment of the disclosure. As shown in fig. 8, a schematic structural diagram of a computer device provided for an embodiment of the present disclosure includes:

a processor 81 and a memory 82; the memory 82 stores machine-readable instructions executable by the processor 81, the processor 81 being configured to execute the machine-readable instructions stored in the memory 82, the processor 81 performing the following steps when the machine-readable instructions are executed by the processor 81: s101: determining a data reading request aiming at a target memory, wherein the data reading request comprises a first data address corresponding to data to be read; s102: determining the data storage state of the data to be read in a preset data cache module based on the first data address, and S103: and responding to the data storage state indication that the data cache module stores effective data to be read, and acquiring the data to be read from the data cache module.

The memory 82 includes a memory 821 and an external memory 822; the memory 821 is also referred to as an internal memory and temporarily stores operation data in the processor 81 and data exchanged with the external memory 822 such as a hard disk, and the processor 81 exchanges data with the external memory 822 through the memory 821.

For the specific execution process of the instruction, reference may be made to the steps of the data processing method described in the embodiments of the present disclosure, and details are not described here.

The embodiments of the present disclosure also provide a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the steps of the data processing method described in the above method embodiments. The storage medium may be a volatile or non-volatile computer-readable storage medium.

The computer program product of the data processing method provided in the embodiments of the present disclosure includes a computer-readable storage medium storing a program code, where instructions included in the program code may be used to execute steps of the data processing method in the above method embodiments, which may be referred to specifically for the above method embodiments, and are not described herein again.

The computer program product may be embodied in hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied in a computer storage medium, and in another alternative embodiment, the computer program product is embodied in a Software product, such as a Software Development Kit (SDK), or the like.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working process of the apparatus described above may refer to the corresponding process in the foregoing method embodiment, and is not described herein again. In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implementing, and for example, a plurality of units or components may be combined, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a target Access Memory (RAM), a magnetic disk, or an optical disk.

Finally, it should be noted that: the above-mentioned embodiments are merely specific embodiments of the present disclosure, which are used for illustrating the technical solutions of the present disclosure and not for limiting the same, and the scope of the present disclosure is not limited thereto, and although the present disclosure is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive of the technical solutions described in the foregoing embodiments or equivalent technical features thereof within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present disclosure, and should be construed as being included therein. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A data processing apparatus, comprising: a data reading component, a data buffer component and a data storage component; the data reading component is in communication connection with the data caching component, and the data caching component is in communication connection with the data storage component;

2. The data processing apparatus of claim 1, wherein the read data component is further configured to retrieve the data to be read from the data storage component based on the read data request and the first data address in response to the data storage status indicating that valid data to be read does not exist in the data cache component.

3. The data processing apparatus of claim 1 or 2, further comprising a write data component communicatively coupled to the data cache component and the data storage component;

4. The data processing apparatus of claim 3, wherein the first write data request further includes first write cache information;

5. The data processing apparatus of claim 1 or 2, further comprising a write data component communicatively coupled to the data cache component and the data storage component;

6. The data processing apparatus of claim 5, wherein the second write data request further includes second write cache information;

7. The data processing apparatus according to claim 1, further comprising a priority determining component communicatively coupled to the data caching component and the data storage component;

8. The data processing apparatus of claim 7, wherein the data caching component comprises a plurality of cache subcomponents corresponding to each respective data access component.

9. The data processing apparatus according to claim 7 or 8, wherein the data access unit is configured to set target read data requests having the same first data address to the same access priority using a preset priority determination unit.

10. The data processing apparatus according to any of claims 2 to 9, wherein the read data request comprises third write cache information;

11. A data processing method, comprising:

12. The method of claim 11, further comprising:

13. The method according to claim 11 or 12, characterized in that the method further comprises:

14. A computer device, comprising: a data processing apparatus as claimed in any one of claims 1 to 10.

15. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a computer device, performs the steps of the data processing method according to any one of claims 11 to 13.