CN113515166A - Sine lookup table data compression method based on FPGA - Google Patents
Sine lookup table data compression method based on FPGA Download PDFInfo
- Publication number
- CN113515166A CN113515166A CN202110467287.9A CN202110467287A CN113515166A CN 113515166 A CN113515166 A CN 113515166A CN 202110467287 A CN202110467287 A CN 202110467287A CN 113515166 A CN113515166 A CN 113515166A
- Authority
- CN
- China
- Prior art keywords
- output
- polynomial
- lookup table
- waveform
- fpga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000013144 data compression Methods 0.000 title claims abstract description 14
- 238000005070 sampling Methods 0.000 claims abstract description 15
- 238000011084 recovery Methods 0.000 claims abstract description 12
- 238000007906 compression Methods 0.000 claims abstract description 5
- 230000006835 compression Effects 0.000 claims abstract description 5
- 238000006243 chemical reaction Methods 0.000 claims description 18
- 238000004364 calculation method Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 241000084490 Esenbeckia delta Species 0.000 claims description 3
- 238000013459 approach Methods 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims description 3
- 230000009466 transformation Effects 0.000 claims description 2
- 238000003860 storage Methods 0.000 abstract description 10
- 238000009825 accumulation Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/03—Digital function generators working, at least partly, by table look-up
- G06F1/035—Reduction of table size
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The invention discloses a sine lookup table data compression method based on an FPGA (field programmable gate array), which comprises the following steps of: s1, calculating the theoretical minimum input address bit width n according to the given m-bit output data bit width, and calculating proper sin omega x as a basic waveform according to the values of m and n; s2, constructing a polynomial f (x), solving the polynomial coefficient according to omega to obtain a function sin omega x-f (x) in a lookup table module,
1/4 cycles; s3, constructing a lookup table module on the FPGA for storing the sampling value of the compression function; s4, constructing an address generating module on the FPGA for obtaining the data in the lookup table module; and S5, constructing a waveform recovery module on the FPGA for recovering the compressed sinusoidal signal. The invention optimizes the sine function based on the existing lookup table, and solves the problems of insufficient precision and more occupied storage resources when the sine output with larger data depth is realized by the original method.
Description
Technical Field
The invention belongs to the field of signal processing, and particularly relates to a sine lookup table data compression method based on an FPGA.
Background
In the fields of signal generation and processing, automatic control and the like, a trigonometric function, particularly a sine waveform is often used, and when the trigonometric function waveform is generated through trigonometric function address coordinates on hardware, high waveform accuracy, good time delay performance and less consumed storage resources are often required. The generation of trigonometric waveforms is a common method implemented by a lookup table method.
The lookup table is the most convenient method for generating the trigonometric function waveform, the address coordinates of the trigonometric function are taken as input, the sampling value of the trigonometric function is taken as output, and the input, the output and the relationship between the input and the output are stored in the ROM. The traditional lookup table method has the advantages that when the lookup table is called according to different output requirements, the reading and output speed can be very high, and the time delay is short. The disadvantage is that the prior period needs very complicated preparation work, because the input and output and the relationship between the input and the output need to be stored in the ROM in advance; another disadvantage is that as the output precision is improved, the storage resource consumed by hardware is greatly increased, and the realization of high-precision trigonometric function waveform has certain limitation.
Disclosure of Invention
Aiming at the defects of large storage capacity consumption, low precision and the like of the traditional lookup table, the invention aims to provide an optimization method of a sine lookup table based on an FPGA, which has low error and small occupation of hardware storage resources, and comprises the following steps:
s1, calculating the theoretical minimum input address bit width n according to the given m-bit output data bit width, and calculating proper sin omega x as a basic waveform according to the values of m and n;
s2, constructing a polynomial f (x), solving the polynomial coefficient according to omega to obtain a function sin omega x-f (x) in a lookup table module,
1/4 cycles;
s3, constructing a lookup table module on the FPGA for storing the sampling value of the compression function;
s4, constructing an address generating module on the FPGA for obtaining the data in the lookup table module;
and S5, constructing a waveform recovery module on the FPGA for recovering the compressed sinusoidal signal.
Preferably, the S1, calculating the theoretical minimum input address bit width n according to the given m-bit output data bit width, and selecting an appropriate sin ω x as the basic waveform according to the m and n values, includes the following steps:
s10, knowing the bit width of m-bit output data, outputting an external DAC, and traversing all values in the output data bits in order to obtain undistorted waveforms in the limited DAC bit width;
s11, minimum output increment, i.e. delta y min1, which has a relation of 2 to the smallest increment of the input addressm*sinΔxmin＝Δy min1, thereby
The number of points required should therefore be
S12, when a high-precision DAC is externally connected, m is usually a large value,
approaches 0, can be obtained
Value of 2m+3The minimum input address bit width n is m + 3;
s13, storing 1/4 waveforms in the original waveforms, outputting other parts through trigonometric function coordinate transformation, and reducing the input address to n-2 bits;
s14, the amplitude of basic waveform is A2mThe waveform is compressed in equal proportion, the amplitude is compressed to be A' ═ 1,
coordinates of (2)n-2(i.e., the maximum address saved) is compressed into
Also, given that n is m +3, the value of ω in the base waveform sin ω x is given by:
preferably, said S2, constructing a polynomial f (x), solving polynomial coefficients according to ω, comprises the following steps:
s20, f (x) is a fourth-order polynomial, 5 sampling points in a sin omega x quarter period are taken, the sampling rule is that the first derivative is quartered, and five sampling points are respectively (0, 0),
s21, solving the coefficient of the fourth-order polynomial using the newton interpolation formula according to the obtained four points to obtain f (x) ax4+bx3+cx2+ dx + e, and rewritten as x (x (x (a))1x+b1)+b2)+b3)+b4Then set a1,b1，b2,b3,b4These coefficients retain the 4 bits after the decimal point.
Preferably, the S3, constructing a lookup table module on the FPGA with a size of 2n-2*2xIn which 2 isn -2The address length of the ROM, x, the data length of the ROM, the ROM storing the original waveform and the sample data of the difference function sin ω x-f (x) of the polynomial, x should satisfy x ═ x
Preferably, the S4, the address generation module, consists of one2n-2The bit counter is composed of a clock signal and an accumulation signal, wherein the clock signal is used for driving the counter, the accumulation signal specifies a count accumulation value, and the output signal is a count value and is sent to the storage module and the waveform recovery module as an address.
Preferably, the S5, the waveform recovery module, includes the following circuits:
the coordinate conversion circuit converts the address value transmitted by the address generation module into a polynomial abscissa value, and transmits the polynomial abscissa value into the polynomial calculation circuit, wherein the conversion formula is as follows: x is the number ofaddress＝xcounter/2mOutputting the result to a polynomial calculating circuit;
the polynomial calculation circuit obtains an f (x) result by calculating an abscissa value transmitted by the coordinate conversion circuit through a four-stage pipeline, and transmits the f (x) result to the summation circuit, and the polynomial calculation circuit comprises the following steps:
s50, calling a multiplier and an adder on the FPGA, wherein two input ends of the multiplier are respectively connected with the output of the coordinate conversion circuit and the coefficient a1Connected, the two inputs of the adder being respectively connected to the output of the multiplier and to the constant term b1The output of the adder and the output of the coordinate conversion circuit are respectively sent to two triggers for registering, and a first-stage production line is completed;
s51, multiplexing the pipeline module in S50, connecting the two inputs of the multiplier with the two register outputs of the previous stage, connecting the two inputs of the adder with the multiplier output and the constant term b corresponding to the current pipeline stageiThe output of the adder and the register output of the coordinate conversion circuit are respectively sent to two triggers for registering, and an ith-stage production line is completed;
s52, repeatedly executing S51 until the construction of the fourth-order polynomial calculation circuit is completed;
s53, taking the high m +1 bit data output by the pipeline as the polynomial calculation result, wherein the m +1 bit is the sign bit.
The waveform register circuit is formed by connecting four triggers in series, the input of the waveform register circuit is connected with the output of the ROM, and the output of the waveform register circuit is transmitted into the summing circuit;
and the summing circuit consists of an adder, the input end of the adder is connected with the output of the polynomial calculating circuit and the output of the waveform registering circuit, and the output is a required standard sine wave signal.
Compared with the prior art, the method for compressing the sine lookup table data based on the FPGA can solve the problems of insufficient precision and insufficient storage resources when the traditional lookup table generates the waveform. Meanwhile, the lookup table data compression method is simple in structure and high in universality. The invention adopts a polynomial function calculation method to compress the waveforms stored in the lookup table, obviously reduces the requirement on hardware storage resources compared with the traditional lookup table method, and simultaneously improves the output precision to a certain extent. .
Drawings
FIG. 1 is a flowchart illustrating steps of a method for compressing sine lookup table data based on FPGA according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a sinusoidal lookup table data compression method based on an FPGA on the FPGA according to an embodiment of the present invention;
fig. 3 is a flowchart of the step of determining the base waveform sin ω x by S1 in the method for compressing sine lookup table data based on FPGA according to the embodiment of the present invention;
fig. 4 is a flowchart of the step of constructing the polynomial f (x) by S2 in the method for compressing sine lookup table data based on FPGA according to the embodiment of the present invention;
fig. 5 is a flowchart of a S5 waveform recovery module in a sinusoidal lookup table data compression method based on FPGA according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an S5 waveform recovery module in a sinusoidal lookup table data compression method based on an FPGA according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
On the contrary, the invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, certain specific details are set forth in order to provide a better understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details.
Firstly, it should be understood that the sine lookup table data compression method based on the FPGA according to the present invention is used in this embodiment to solve the problem that the sine lookup table consumes a large storage capacity when implemented on the FPGA, and the present invention mainly aims at the case that the output data bit width m is large, but when the output data bit width m is small, the present invention can also be used for compression.
Referring to fig. 1 and fig. 2, a schematic structural diagram and a flowchart of steps of a sinusoidal lookup table data compression method based on an FPGA according to an embodiment of the present invention are respectively shown, where the method includes the following steps:
s1, calculating the theoretical minimum input address bit width n according to the given m-bit output data bit width, and calculating proper sin omega x as a basic waveform according to the values of m and n;
s2, constructing a polynomial f (x), solving the polynomial coefficient according to omega to obtain a function sin omega x-f (x) in a lookup table module,
1/4 cycles;
s3, constructing a lookup table module on the FPGA for storing the sampling value of the compression function;
s4, constructing an address generating module on the FPGA for obtaining the data in the lookup table module;
and S5, constructing a waveform recovery module on the FPGA for recovering the compressed sinusoidal signal.
Detailed description of the preferred embodiments
Referring to fig. 3, a flowchart of the steps of calculating the theoretical minimum input address bit width n according to the given m-bit output data bit width and determining the base waveform sin ω x according to the sinusoidal lookup table data compression method based on the FPGA according to the embodiment of the present invention is shown, and the output data bit width m ═ 12 of the embodiment is shown, including the following steps:
s10, knowing that m is 12 bits of output data bit width, outputting an external DAC, and traversing all values within the output data bits in order to obtain an undistorted waveform within the limited DAC bit width;
s11, minimum output increment, i.e. delta y min1, which has a relation of 2 to the smallest increment of the input addressm*sinΔxmin＝Δy min1, thereby
The number of points required should therefore be
S12, where m is 12 in the present embodiment,
approaches 0, can be obtained
Value of 2m+3The minimum input address bit width n is m +3 is 15;
s13, storing 1/4 waveforms in the original waveforms, converting other parts through trigonometric function coordinates and outputting, and reducing the input address to n-2-13 bits;
s14, the amplitude of basic waveform is A2mThe waveform is compressed in equal proportion, the amplitude is compressed to be A' ═ 1,
coordinates of (2)n-2(i.e., the maximum address saved) is compressed into
Also, given that n is m +3, the value of ω in the base waveform sin ω x is given by:
referring to fig. 4, a flowchart of steps of solving polynomial coefficients according to ω according to a given structural polynomial f (x) of a sinusoidal lookup table data compression method based on FPGA according to an embodiment of the present invention includes the following steps:
s20, f (x) is a fourth-order polynomial, 5 sampling points in a sin omega x quarter period are taken, the sampling rule is that the first derivative is quartered, and five sampling points are respectively (0, 0),
s21, solving the coefficient of the fourth-order polynomial using the newton interpolation formula according to the obtained four points to obtain f (x) ax2+bx3+cx2+ dx + e, and rewritten as x (x (x (a))1x+b1)+b2)+b3)+b2Then set a1,b1,b2,b3，b2These coefficients retain the 4 bits after the decimal point, in this example, a1＝0.0127，b1＝-0.1064，b2＝0.0233，b3＝0.7776，b2＝0；
S3, constructing a lookup table module on the FPGA, and constructing a size of 2n-2*2xIn which 2 isn-2The address length of the ROM, x, the data length of the ROM, the ROM storing the original waveform and the sample data of the difference function sin ω x-f (x) of the polynomial, x should satisfy x ═ x
In the present embodiment, x is 2, that is, one 2 is configured13*22The ROM of (a) is,
the S4, address generation module, is composed of a 2n-2The bit counter is composed of a clock signal and an accumulation signal, wherein the clock signal is used for driving the counter, the accumulation signal specifies a count accumulation value, and the output signal is a count value and is sent to the storage module and the waveform recovery module as an address.
Referring to fig. 5 and fig. 6, which are a flow chart of steps and a schematic structural diagram of a waveform recovery module of a sinusoidal lookup table data compression method based on an FPGA according to an embodiment of the present invention, respectively, the method includes the following circuits:
the coordinate conversion circuit converts the address value transmitted by the address generation module into a polynomial abscissa value, and transmits the polynomial abscissa value into the polynomial calculation circuit, wherein the conversion formula is as follows: x is the number ofaddress＝xcounter/2mThe output result is sent to a polynomial computing circuit, in this embodiment, xaddress＝xcounter/212；
The polynomial calculation circuit obtains an f (x) result by calculating an abscissa value transmitted by the coordinate conversion circuit through a four-stage pipeline, and transmits the f (x) result to the summation circuit, and the polynomial calculation circuit comprises the following steps:
s50, calling a multiplier 1 and an adder 1 on the FPGA, wherein two input ends of the multiplier 1 are respectively connected with the output of the coordinate conversion circuit and the coefficient a1Connected, two inputs of the adder 1 respectively with the output of the multiplier 1 and the constant term b1The output of the adder 1 and the output of the coordinate conversion circuit are respectively sent to two triggers for registering, and a first-stage production line is completed;
s51, multiplexing the pipeline module in S50, connecting the two inputs of the multiplier i (2, 3, 4) with the two register outputs of the previous stage, connecting the two inputs of the adder i (2, 3, 4) with the output of the multiplier i (2, 3, 4) and the constant term b corresponding to the current pipeline stageiThe outputs of the adders i (2, 3 and 4) and the register output of the coordinate conversion circuit are respectively sent to two triggers for registering, and the ith-stage production line is completed;
s52, repeatedly executing S51 until the construction of the fourth-order polynomial calculation circuit is completed;
s53, the high m + 1-13 bit data output from the pipeline is taken as the polynomial calculation result, where the 13 th bit is the sign bit.
The waveform register circuit is formed by connecting four triggers in series, the input of the waveform register circuit is connected with the output of the ROM, and the output of the waveform register circuit is transmitted into the summing circuit;
and the summing circuit consists of an adder 5, and the input end of the adder 5 is connected with the output of the polynomial computing circuit and the output of the waveform registering circuit and outputs the required standard sine wave signal.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (6)
1. A sine lookup table data compression method based on FPGA is characterized by comprising the following steps:
s1, calculating the theoretical minimum input address bit width n according to the given m-bit output data bit width, and calculating proper sin omega x as a basic waveform according to the values of m and n;
s2, constructing a polynomial f (x), solving the polynomial coefficient according to omega to obtain a function sin omega x-f (x) in a lookup table module,
1/4 cycles;
s3, constructing a lookup table module on the FPGA for storing the sampling value of the compression function;
s4, constructing an address generating module on the FPGA for obtaining the data in the lookup table module;
and S5, constructing a waveform recovery module on the FPGA for recovering the compressed sinusoidal signal.
2. The method according to claim 1, wherein said S1, calculating a theoretical minimum input address bit width n according to a given m-bit output data bit width, and selecting an appropriate sin ω x as a base waveform according to m and n values, comprises the steps of:
s10, knowing the bit width of m-bit output data, outputting an external DAC, and traversing all values in the output data bits in order to obtain undistorted waveforms in the limited DAC bit width;
s11, minimum output increment, i.e. delta ymin1, which has a relation of 2 to the smallest increment of the input addressm*sinΔxmin＝Δymin1, thereby
The number of points required should therefore be
S12, when a high-precision DAC is externally connected, m is usually a large value,
approaches 0, can be obtained
Value of 2m+3The minimum input address bit width n is m + 3;
s13, storing 1/4 waveforms in the original waveforms, outputting other parts through trigonometric function coordinate transformation, and reducing the input address to n-2 bits;
s14, the amplitude of basic waveform is A2mThe waveform is compressed in equal proportion, the amplitude is compressed to be A' ═ 1,
coordinates of (2)n-2I.e. maximum address saved, compressed proportionally to
Also, given that n is m +3, the value of ω in the base waveform sin ω x is given by:
3. the method of claim 2, wherein said S2, constructing a polynomial f (x), solving polynomial coefficients according to ω, comprises the steps of:
s20, f (x) is a fourth-order polynomial, 5 sampling points in a sin omega x quarter period are taken, the sampling rule is that the first derivative is quartered, five sampling points are (0, 0) respectively,
s21, solving the coefficient of the fourth-order polynomial using the newton interpolation formula according to the obtained four points to obtain f (x) ax4+bx3+cx2+ dx + e, and rewritten as x (x (x (a))1x+b1)+b2)+b3)+b4Then set a1，b1，b2，b3，b4These coefficients retain the 4 bits after the decimal point.
4. The method according to claim 3, wherein S3, constructing a lookup table module on FPGA, constructing a size of 2n-2*2xIn which 2 isn-2Is the address length of the ROM, x is the data length of the ROM, the ROM stores the sampling data of the difference function sin omega x-f (x) of the original waveform and the polynomial, and x should satisfy
5. The method of claim 4, wherein said S4, address generation module, is composed of a 2n-2The bit counter is composed of clock signal for driving counter and accumulating signal for defining accumulated value, and output signal as counting value and sent to memory module as addressAnd a shape recovery module.
6. The method according to claim 5, wherein the S5, waveform recovery module, comprises the following circuits:
the coordinate conversion circuit converts the address value transmitted by the address generation module into a polynomial abscissa value, and transmits the polynomial abscissa value into the polynomial calculation circuit, wherein the conversion formula is as follows: x is the number ofaddress＝xcounter/2mOutputting the result to a polynomial calculating circuit;
the polynomial calculation circuit obtains an f (x) result by calculating an abscissa value transmitted by the coordinate conversion circuit through a four-stage pipeline, and transmits the f (x) result to the summation circuit, and the polynomial calculation circuit comprises the following steps:
s50, calling a multiplier and an adder on the FPGA, wherein two input ends of the multiplier are respectively connected with the output of the coordinate conversion circuit and the coefficient a1Connected, the two inputs of the adder being respectively connected to the output of the multiplier and to the constant term b1The output of the adder and the output of the coordinate conversion circuit are respectively sent to two triggers for registering, and a first-stage production line is completed;
s51, multiplexing the pipeline module in S50, connecting the two inputs of the multiplier with the two register outputs of the previous stage, connecting the two inputs of the adder with the multiplier output and the constant term b corresponding to the current pipeline stageiThe output of the adder and the register output of the coordinate conversion circuit are respectively sent to two triggers for registering, and an ith-stage production line is completed;
s52, repeatedly executing S51 until the construction of the fourth-order polynomial calculation circuit is completed;
s53, taking high m +1 bit data output by the pipeline as a polynomial calculation result, wherein the m +1 bit is a sign bit;
the waveform register circuit is formed by connecting four triggers in series, the input of the waveform register circuit is connected with the output of the ROM, and the output of the waveform register circuit is transmitted into the summing circuit;
and the summing circuit consists of an adder, the input end of the adder is connected with the output of the polynomial calculating circuit and the output of the waveform registering circuit, and the output is a required standard sine wave signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110467287.9A CN113515166B (en) | 2021-04-28 | 2021-04-28 | Sine lookup table data compression method based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110467287.9A CN113515166B (en) | 2021-04-28 | 2021-04-28 | Sine lookup table data compression method based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113515166A true CN113515166A (en) | 2021-10-19 |
| CN113515166B CN113515166B (en) | 2024-04-19 |
Family
ID=78063763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110467287.9A Active CN113515166B (en) | 2021-04-28 | 2021-04-28 | Sine lookup table data compression method based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113515166B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5453945A (en) * | 1994-01-13 | 1995-09-26 | Tucker; Michael R. | Method for decomposing signals into efficient time-frequency representations for data compression and recognition |
| CN110633447A (en) * | 2019-08-30 | 2019-12-31 | 中国人民解放军军事科学院国防科技创新研究院 | Spherical distance fixed-point calculation method based on FPGA and calculation device thereof |
-
2021
- 2021-04-28 CN CN202110467287.9A patent/CN113515166B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5453945A (en) * | 1994-01-13 | 1995-09-26 | Tucker; Michael R. | Method for decomposing signals into efficient time-frequency representations for data compression and recognition |
| CN110633447A (en) * | 2019-08-30 | 2019-12-31 | 中国人民解放军军事科学院国防科技创新研究院 | Spherical distance fixed-point calculation method based on FPGA and calculation device thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113515166B (en) | 2024-04-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103051339B (en) | A kind of AD sampling value correcting method and system | |
| CN109542393B (en) | Approximate 4-2 compressor and approximate multiplier | |
| CN110515589B (en) | Multiplier, data processing method, chip and electronic equipment | |
| JP2001230671A (en) | Count-down/up circuit and analog/digital converting method | |
| CN109521992B (en) | Linear frequency modulation signal generation method without multiplier based on CORDIC algorithm | |
| WO2021136259A1 (en) | Floating-point number multiplication computation method and apparatus, and arithmetical logic unit | |
| Dianov et al. | Review of fast square root calculation methods for fixed point microcontroller-based control systems of power electronics | |
| CN110515584A (en) | Floating-point Computation method and system | |
| CN113515166A (en) | Sine lookup table data compression method based on FPGA | |
| CN102566965B (en) | Floating-point number logarithmic operation device with flat errors | |
| CN111399803A (en) | Division operation method, device, storage medium and electronic equipment | |
| CN113377340A (en) | Digital oscilloscope with fractional calculus operation and display function | |
| CN107943204B (en) | Digital frequency synthesis method and device | |
| CN117032625A (en) | Low-delay floating point square root function hardware implementation method | |
| US20210224035A1 (en) | Xiu-accumulating register, xiu-accumulating register circuit, and electronic device | |
| CN115146769A (en) | Digital circuit module for calculating tanh function based on range addressable lookup table | |
| US7519642B2 (en) | Parallel computation structures to enhance signal-quality, using arithmetic or statistical averaging | |
| CN109190084B (en) | Hardware implementation method for sine and cosine calculation | |
| CN109885970B (en) | Look-up table digital circuit and processing method thereof | |
| JP4696920B2 (en) | DDS signal generator | |
| JP5883705B2 (en) | Signal generator | |
| CN113778379A (en) | CORDIC-based low-complexity hardware system and application method | |
| CN116865763A (en) | High-linearity edge ramp wave generation device and method | |
| Cao et al. | A piecewise cubic polynomial interpolation algorithm for approximating elementary function | |
| CN111814107B (en) | Computing system and computing method for realizing reciprocal of square root with high precision |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |