CN109190084B - Hardware implementation method for sine and cosine calculation - Google Patents
Hardware implementation method for sine and cosine calculation Download PDFInfo
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- CN109190084B CN109190084B CN201810827739.8A CN201810827739A CN109190084B CN 109190084 B CN109190084 B CN 109190084B CN 201810827739 A CN201810827739 A CN 201810827739A CN 109190084 B CN109190084 B CN 109190084B
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Abstract
The invention discloses a hardware implementation method for sine and cosine calculation, and belongs to the technical field of medium-power permanent magnet synchronous motor control. According to the invention, a feedback structure is designed through the basic principle of a CORDIC iterative algorithm, only a first-stage operation iterative unit is designed in the structure, the output of the stage is used as the input of the stage, the operation is completed through the first-stage iteration, and a plurality of clock cycles are required for completing one CORDIC operation. The invention is realized by hardware, only adopts hardware addition and shift calculation, is very suitable for FPGA hardware realization, and saves hardware resources and expenses. Meanwhile, the IP soft core obtained by the invention is downloaded to an FPGA chip and is equivalent to a hardware ASIC, thereby facilitating the control of system calling.
Description
Technical Field
The invention discloses a hardware implementation method for sine and cosine calculation, and belongs to the technical field of medium-power permanent magnet synchronous motor control.
Background
Trigonometric function solution is an important operation in engineering application, and is frequently used in a plurality of scientific and technical fields such as motor control, probability statistics, image processing and the like. Due to the complex calculation process and the obviously lower operation speed than other operations, the operation is mainly performed in a Digital Signal Processor (DSP). However, due to the complexity of the algorithm, for example, the calculation process of the vector control algorithm for motor control is complex, the DSP implemented by software occupies a lot of time of the CPU, and sometimes dual DSPs have to be used to improve the performance of the system.
With the maturity of FPGA hardware design methods and the increase of monolithic scale, FPGA-based servo control systems have emerged. However, the complexity of implementing the operation of the trigonometric function by using hardware is very high, so people are always looking for an algorithm easy to implement by using hardware to improve the operation speed of the trigonometric function, and the CORDIC algorithm is a relatively ideal algorithm recognized at present.
Disclosure of Invention
The purpose of the invention is: the invention provides a hardware realization method for sine and cosine calculation, which is mainly used for realizing the calculation of a trigonometric function in the prior engineering application by adopting a DSP (digital signal processor), occupies more time of a CPU (central processing unit), has the defects of high calculation speed and the like, realizes the calculation of the trigonometric function in a hardware mode, uses hardware addition and shift processing, and simultaneously adopts a CORDIC (coordinated rotation digital computer) iterative algorithm, saves hardware resources and improves the calculation speed.
The technical scheme of the invention is as follows:
a hardware implementation method for sine and cosine calculation is applied to a programmable logic array FPGA, and comprises the following steps:
1) Inputting a rotation angle theta to the programmable logic array FPGA, judging a quadrant where the rotation angle theta is located by the programmable logic array FPGA through a quadrant conversion unit, recording a quadrant mark number Q1Q2 of the rotation angle theta, and when the rotation angle theta is more than or equal to 0 degree and less than or equal to 90 degrees, judging that Q is equal to 1 Q 2 =00; when the rotation angle theta is more than 90 degrees and less than or equal to 180 degrees, Q is 1 Q 2 =01; when the rotation angle theta is 1180 DEG < theta ≦ 270 DEG, Q1Q 2 =10; when the rotation angle theta is more than 270 degrees and less than or equal to 360 degrees, Q is 1 Q 2 =11; meanwhile, the programmable logic array FPGA converts the rotation angle theta into an equivalent angle between 0 DEG and 90 DEG;
2) The programmable logic array FPGA sends an equivalent angle between theta which is more than or equal to 0 degree and less than or equal to 90 degrees to a CORDIC algorithm unit for calculation, a hardware adder and a shifting operation in the programmable logic array FPGA are utilized to realize the CORDIC algorithm unit, the CORDIC algorithm unit adopts an iterative algorithm, the number of shifting bits is equal to the current iterative series, the selection of an adding and subtracting method in the CORDIC algorithm unit is determined by the highest position of Z in the stage, namely a sign bit, and the CORDIC algorithm unit obtains the values of x, y and Z of the next stage through iterative calculation; after the CORDIC algorithm unit performs N-level operation, the value of z is changed into 0, and the values of x and y are the cosine and sine values of the rotation angle theta; the CORDIC algorithm unit mainly comprises 2 shifters, 2 adders or 2 subtractors, the programmable logic array FPGA sends the result obtained by the CORDIC algorithm unit to the post-processing unit, and the result obtained by the CORDIC algorithm unit is according to a quadrant mark number Q 1 Q 2 Carrying out conversion output; the function of the post-processing unit is as follows: when Q is 1 Q 2 When =00, the programmable logic array FPGA directly outputs sine and cosine function values; when Q is 1 Q 2 When the signal strength is =01, the programmable logic array FPGA outputs a cosine function value equal to the opposite number of the y value of the CORDIC algorithm unit and outputs a sine function value equal to the x value of the CORDIC algorithm unit; when Q is 1 Q 2 When the output value is not less than 10, the programmable logic array FPGA outputs cosine function value equal to the opposite number of the x value of the CORDIC arithmetic unit and outputs sineThe function value is equal to the opposite number of the y value of the CORDIC arithmetic unit; when Q is 1 Q 2 And when the output is 11, the programmable logic array FPGA outputs a cosine function value equal to the y value of the CORDIC algorithm unit and outputs a sine function value equal to the opposite number of the x value of the CORDIC algorithm unit.
The CORDIC algorithm unit uses an iterative algorithm of a feedback structure.
The CORDIC algorithm unit uses an iterative algorithm of a multi-stage pipeline structure.
The CORDIC arithmetic unit is designed into a single-stage pipeline structure, and the calculation result of the stage serves as the calculation input of the next stage.
The invention has the advantages that: the improved and optimized CORDIC algorithm is adopted to carry out sine and cosine calculation, the calculation range of the algorithm is expanded to improve the angle range of the calculation of the traditional algorithm from-99.88 degrees to 0-360 degrees, the iterative algorithm of a feedback structure is used, only one stage of operation iteration unit is designed, the output of the stage is used as the input of the stage, the operation is completed through the iteration of the same stage, the calculation of the sine and the cosine consumes less resources through the addition and the shift processing of hardware in the FPGA, and meanwhile, the obtained IP soft core is downloaded to an FPGA chip and is equivalent to a hardware ASIC, and the control system is convenient to call.
Drawings
FIG. 1 is a flow chart of sine and cosine calculation;
FIG. 2 is an iterative flow of the CORDIC algorithm;
Detailed Description
A hardware implementation method for sine and cosine calculation is applied to a programmable logic array FPGA, and comprises the following steps:
1) Inputting a rotation angle theta to the programmable logic array FPGA, judging a quadrant where the rotation angle theta is located by the programmable logic array FPGA through a quadrant conversion unit, recording a quadrant mark number Q1Q2 of the rotation angle theta, and when the rotation angle theta is more than or equal to 0 degree and less than or equal to 90 degrees, judging that Q is equal to 1 Q 2 =00; when the rotation angle theta is more than 90 degrees and less than or equal to 180 degrees, Q is 1 Q 2 =01; when the rotation angle theta is more than 180 DEG and less than or equal to 270 DEG, then Q1Q 2 =10; when the rotation angle theta is more than 270 degrees and less than or equal to 360 degrees, Q is 1 Q 2 ＝11；Meanwhile, the programmable logic array FPGA converts the rotation angle theta into an equivalent angle between 0 DEG and 90 DEG;
working process of the quadrant conversion unit:
a. theta is more than or equal to 0 degree and less than or equal to 90 degrees at the input angle, then Q is 1 Q 2 ＝00；
b. The input angle is more than 90 degrees and less than or equal to 180 degrees, then Q 1 Q 2 ＝01；
c. The input angle is more than 180 degrees and less than or equal to 270 degrees, and then Q1Q2=10;
d. the input angle is more than 270 degrees and less than or equal to 360 degrees, then Q 1 Q 2 ＝11；
2) The programmable logic array FPGA sends an equivalent angle between theta which is more than or equal to 0 degree and less than or equal to 90 degrees to a CORDIC algorithm unit for calculation, a hardware adder and a shifting operation in the programmable logic array FPGA are utilized to realize the CORDIC algorithm unit, the CORDIC algorithm unit adopts an iterative algorithm, the number of shifting bits is equal to the current iterative series, the selection of an adding and subtracting method in the CORDIC algorithm unit is determined by the highest position of Z in the stage, namely a sign bit, and the CORDIC algorithm unit obtains the values of x, y and Z of the next stage through iterative calculation; after N-stage pipeline operation, the value of z is changed into 0, and the values of x and y are the cosine and sine values of the initial value z 0. The iterative structure mainly comprises 2 shifters and 2 addition (subtraction) devices. Theta i Has a value of arctan (2) -i ) The decimal may be converted to a binary number and stored in a storage unit to provide a look-up table for the iterative process.
After N-stage operation, the CORDIC algorithm unit changes the value of z into 0, and the values of x and y are cosine and sine values of a rotation angle theta; the CORDIC algorithm unit mainly comprises 2 shifters, 2 adders or 2 subtractors, the programmable logic array FPGA sends the result obtained by the CORDIC algorithm unit to the post-processing unit, and the result obtained by the CORDIC algorithm unit is according to a quadrant mark number Q 1 Q 2 Carrying out conversion output; the function of the post-processing unit is as follows: when Q is 1 Q 2 When =00, the programmable logic array FPGA directly outputs sine and cosine function values; when Q is 1 Q 2 When =01, the programmable logic array FPGA outputs the cosine function value equal to the CORDIC algorithmThe y value of the element is opposite, and the output sine function value is equal to the x value of the CORDIC algorithm unit; when Q is 1 Q 2 When the value is not less than 10, the programmable logic array FPGA outputs a cosine function value equal to the opposite number of the x value of the CORDIC algorithm unit and outputs a sine function value equal to the opposite number of the y value of the CORDIC algorithm unit; when Q is 1 Q 2 And when the output sine function value is equal to the x value of the CORDIC algorithm unit, the programmable logic array FPGA outputs the cosine function value equal to the y value of the CORDIC algorithm unit and outputs the sine function value equal to the opposite number of the x value of the CORDIC algorithm unit.
Examples
With the calculation precision of 20 bits, the number of design iterations must be equal to or greater than the calculation precision, and therefore the number of iterations is designed to be 20. The RAM table stores the arctan angle values for 20 iterations as follows:
case(rom_addr)
13'd0:arctan＝20'd823550；
13'd1:arctan＝20'd486170；
13'd2:arctan＝20'd256879；
13'd3:arctan＝20'd130396；
13'd4:arctan＝20'd65451；
13'd5:arctan＝20'd32757；
13'd6:arctan＝20'd16383；
13'd7:arctan＝20'd8192；
13'd8:arctan＝20'd4096；
13'd9:arctan＝20'd2048；
13'd10:arctan＝20'd1024；
13'd11:arctan＝20'd512；
13'd12:arctan＝20'd256；
13'd13:arctan＝20'd128；
13'd14:arctan＝20'd64；
13'd15:arctan＝20'd32；
13'd16:arctan＝20'd16；
13'd17:arctan＝20'd8；
13'd18:arctan＝20'd4；
13'd19:arctan＝20'd2；
13'd20:arctan＝20'd1；
default:arctan＝20'd0；
input angle θ = pi/4, first enters the quadrant conversion unit, Q 1 Q 2 =00. The camber value is then converted to a binary number of 20' d823550, then given an initial value of X =30' h136_E9DD, Y =30' h0; after the cyclic iteration algorithm, X =30'hB _4FDF, Y =30' hB _4FDF, and after the 20-bit right shift algorithm, cos θ =0.706999 and sin θ =0.706999 are carried out.
Claims (4)
1. A hardware implementation method for sine and cosine calculation is applied to a programmable logic array (FPGA), and is characterized by comprising the following steps of:
1) Inputting a rotation angle theta to the programmable logic array FPGA, judging a quadrant where the rotation angle theta is located by the programmable logic array FPGA through a quadrant conversion unit, recording a quadrant mark number Q1Q2 of the rotation angle theta, and when the rotation angle theta is more than or equal to 0 degree and less than or equal to 90 degrees, judging that Q is equal to 1 Q 2 =00; when the rotation angle theta is more than 90 degrees and less than or equal to 180 degrees, Q is 1 Q 2 =01; when the rotation angle theta is more than 180 DEG and less than or equal to 270 DEG, Q is 1 Q 2 =10; when the rotation angle theta is more than 270 degrees and less than or equal to 360 degrees, Q is 1 Q 2 =11; meanwhile, the rotation angle theta is converted into an equivalent angle between 0 degrees and more than or equal to theta and less than or equal to 90 degrees by the FPGA;
2) The programmable logic array FPGA sends an equivalent angle between theta which is more than or equal to 0 degree and less than or equal to 90 degrees to a CORDIC algorithm unit for calculation, a hardware adder and a shifting operation in the programmable logic array FPGA are utilized to realize the CORDIC algorithm unit, the CORDIC algorithm unit adopts an iterative algorithm, the number of shifting bits is equal to the current iterative series, the selection of an adding and subtracting method in the CORDIC algorithm unit is determined by the highest position of Z in the stage, namely a sign bit, and the CORDIC algorithm unit obtains the values of x, y and Z of the next stage through iterative calculation; after N-stage operation, the CORDIC algorithm unit changes the value of z into 0, and the values of x and y are cosine and sine values of a rotation angle theta; the CORDIC algorithm unit mainly comprises 2 shifters, 2 adders or 2 subtractors, and the programmable logic array FPGA obtains the CORDIC algorithm unitThe result is sent to a post-processing unit, and the result obtained by the CORDIC algorithm unit is based on the quadrant mark number Q 1 Q 2 Carrying out conversion output; the function of the post-processing unit is as follows: when Q is 1 Q 2 When =00, the programmable logic array FPGA directly outputs sine and cosine function values; when Q is 1 Q 2 When the output signal is not less than 01, the programmable logic array FPGA outputs a cosine function value equal to the opposite number of the y value of the CORDIC algorithm unit and outputs a sine function value equal to the x value of the CORDIC algorithm unit; when Q is 1 Q 2 When the value is not less than 10, the programmable logic array FPGA outputs a cosine function value equal to the opposite number of the x value of the CORDIC algorithm unit and outputs a sine function value equal to the opposite number of the y value of the CORDIC algorithm unit; when Q is 1 Q 2 And when the output is 11, the programmable logic array FPGA outputs a cosine function value equal to the y value of the CORDIC algorithm unit and outputs a sine function value equal to the opposite number of the x value of the CORDIC algorithm unit.
2. The hardware implementation method of sine and cosine computation of claim 1, wherein the CORDIC algorithm unit uses an iterative algorithm of a feedback structure.
3. The hardware implementation method of sine and cosine computation of claim 1, wherein the CORDIC algorithm unit uses an iterative algorithm of a multi-stage pipeline structure.
4. The hardware implementation method of sine and cosine computation of claim 1, wherein the CORDIC arithmetic unit is designed as a single-stage pipeline structure, and the result of the current stage of computation is used as the input of the next stage of computation.
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