CN113506829A - Step gate dielectric layer structure and manufacturing method thereof - Google Patents
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Abstract
A step gate dielectric layer structure comprises an N + substrate, an N-epitaxial layer, a P-body diffusion window, and an N+JFETThe gate source isolation layer is arranged on the diffusion window; the invention relates to a stepped gate dielectric layer structure for improving the single-particle gate penetration resistance of a MOSFET (metal-oxide-semiconductor field effect transistor) and a manufacturing method thereof
The thickness of the gate dielectric layer on the N + JFET area can be grown to
The thickness of the gate dielectric layer in the P-body channel region is set to
The channel region of the gate dielectric layer with the stepped structure is thin oxygen, so that the total dose performance of the device is not affected; the JFET area is made of thick oxygen, the breakdown voltage of a gate dielectric is improved, and the single-particle-resistant gate penetration capability of the device is further improved.
Description
Technical Field
The invention belongs to the technical field of semiconductor discrete devices, and relates to a step gate dielectric layer structure and a manufacturing method thereof.
Background
The aerospace-grade MOSFET is applied to a space radiation environment, a total dose effect and a Single Event effect can be generated, the Single Event effect mainly comprises two failure mechanisms, namely Single Event Burnout (SEB) and Single Event Gate penetration (SEGR), and the two mechanisms can cause irreversible failure of a device and influence the normal work of the whole system. The main failure mechanism of the single-particle gate penetration is as follows: taking an N-channel MOSFET as an example, when high-energy particles are incident into a device from a gate region of the device, a large number of electron-hole pairs are generated in a gate dielectric and a semiconductor material along a track after the particles are incident, electrons are collected by a drain electrode under the action of an external electric field, holes drift toward a Si/SiO2 interface, charges accumulated at the Si/SiO2 interface induce opposite charges on a gate, an electric field formed by the charges and the induced charges can increase an electric field of the gate dielectric, and when a breakdown voltage of the gate dielectric is reached, a single-particle gate tunneling (SEGR) effect can be initiated.
The commonly adopted single-particle gate penetration reinforcing technology mainly improves the growth quality of a gate dielectric layer and increases the thickness of the gate dielectric layer. The increase of the thickness of the gate dielectric layer can improve the breakdown voltage of the gate dielectric, thereby effectively improving the single-particle gate-through effect of the device, but the increase of the thickness of the gate dielectric is not beneficial to the total dose resistance of the device and is generally controlled in
In the MOSFET deviceEnergy is also limited as a result.
Disclosure of Invention
The present invention is directed to a step gate dielectric structure and a method for fabricating the same to solve the above-mentioned problems.
In order to achieve the purpose, the invention adopts the following technical scheme:
a step gate dielectric layer structure comprises an N + substrate, an N-epitaxial layer, a P-body diffusion window, and an N+JFETThe gate source isolation layer is arranged on the diffusion window; the N-epitaxial layer is arranged on the N + substrate, P-body diffusion windows are respectively arranged on two sides of the N-epitaxial layer, an N + JFET diffusion window is arranged between the two P-body diffusion windows, gate dielectric layers are arranged in the longitudinal direction of the P-body diffusion window and the N + JFET diffusion window, and gate polycrystalline silicon and a gate source isolation layer are sequentially arranged on the gate dielectric layers from bottom to top; the gate dielectric layer is of a stepped structure.
Furthermore, the gate dielectric layer is provided with an active N + diffusion window and a source P + diffusion window, the source N + diffusion window, the source P + diffusion window and the source metal are connected to form a source electrode, the gate metal is connected with the gate polysilicon to form a gate, and the drain metal is connected with the N + substrate to form a drain electrode.
Further, the gate dielectric layer is a gate dielectric layer
Growth process condition, the thickness of the gate dielectric layer is divided into two parts, N+JFETThe thickness of the gate dielectric layer on the diffusion window is
And the thickness of the gate dielectric layer on the P-body diffusion window is
Furthermore, the length of the gate dielectric layer is 4-5 μm.
Further, N+JFETThe diffusion window is arranged between the two P-body diffusion windows, and the length of the diffusion window is 1.2-1.6 mu m; the length of the grid polysilicon is 4-5 mu m, and the thickness is
Furthermore, the length of the source N + diffusion window is 1.2-1.5 μm; the length of the source P + diffusion window is 2-3 mu m; the length of the gate-source isolation layer is 6-7 μm, and the thickness is 0.8-1.2 μm; the size of the N + substrate is 8-10 mu m; the length of the P-body diffusion window is 3.6-4 μm.
Further, a manufacturing method of the step gate dielectric layer structure comprises the following steps:
after P-body injection and diffusion and before gate dielectric layer growth, N+JFETThe injection and annealing process comprises the following specific process manufacturing flows: sacrificial oxide growth → P-body region lithography → P-body implantation → photoresist removal → P-body diffusion → N+JFETArea lithography → N+JFETInject → strip → N+JFETActivating → removing the sacrificial oxide layer; the process manufacturing flow before the growth of the sacrifice oxide layer and after the removal of the sacrifice oxide layer is consistent with the prior flow.
Further, N+JFETThe diffusion window process parameters are as follows: injecting AsH3 as an injection material, with the injection dosage of 1e 15-1.5 e15, the injection energy of 80 Kev-90 Kev, the activation temperature of 850-900 ℃ and the activation time of 10-15 min.
Compared with the prior art, the invention has the following technical effects:
the invention relates to a stepped gate dielectric layer structure for improving the single-particle gate penetration resistance of a MOSFET (metal-oxide-semiconductor field effect transistor) and a manufacturing method thereof
The thickness of the gate dielectric layer on the N + JFET area can be grown to
The thickness of the gate dielectric layer in the P-body channel region is set to
The channel region of the gate dielectric layer with the stepped structure is thin oxygen, so that the total dose performance of the device is not affected; the JFET area is made of thick oxygen, the breakdown voltage of a gate dielectric is improved, and the single-particle-resistant gate penetration capability of the device is further improved.
In actual design and production, aiming at products with different single particle requirements, the gate dielectric layer in the channel region is controlled to be
The gate dielectric layer of the JFET region is controlled at
By adopting the stepped gate dielectric layer structure and the manufacturing method, for the MOSFET with high voltage of 500V, when the gate bias is zero, the single-particle safe voltage can be increased from the previous 45% VDS (225V) to 65% VDS (325V).
Drawings
FIG. 1 is a schematic diagram of a unit cell of the structure of the present invention;
FIG. 2 is a schematic representation of a cell of a prior art structure.
Wherein, 1, N + substrate; an N-epitaxial layer; a P-body diffusion window; an N + JFET diffusion window; 5. a gate dielectric layer; 6. grid polysilicon; 7. a source N + diffusion window; 8. a source P + diffusion window; 9. a gate source isolation layer.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
Referring to fig. 1, the present invention discloses a step gate dielectric layer structure for improving the single particle penetration resistance of a MOSFET and a method for manufacturing the same. The basic unit structure of the device is strip-shaped and comprises an N + substrate 1, an N-epitaxial layer 2, a P-body diffusion window 3 and N +JFET A diffusion window 4, a gate dielectric layer 5, a gate polysilicon 6, a source N + diffusion window 7, a source P + diffusion window 8 and a gate source isolation layer 9, wherein an N-epitaxial layer 2 is arranged on an N + substrate 1, the left side and the right side of the N-epitaxial layer 2 are provided with a single cell main junction P-body diffusion window 3 of a device, and the two are arrangedN + is arranged between P-body diffusion windows 3JFET Diffusion window 4, P-body diffusion window 3 and N +JFETA gate dielectric layer 5 is arranged in the longitudinal direction of the diffusion window 4, a gate polycrystalline silicon 6 and a gate source isolation layer 9 are sequentially arranged on the gate dielectric layer 5, an active N + diffusion window 6 and a source P + diffusion window 7 are arranged on the gate dielectric layer, the source N + diffusion window 6, the source P + diffusion window 7 and a source metal are connected to form a source electrode, a gate metal is connected with the gate polycrystalline silicon 6 to form a gate, and a drain metal is connected with the N + substrate 1 to form a drain electrode.
N+JFETThe process manufacturing method of the diffusion window 5 comprises the following steps: adding a step of N + after P-body injection and diffusion and before gate dielectric layer growthJFETThe injection and annealing process comprises the following specific process manufacturing flows: sacrificial oxide growth → P-body region lithography → P-body implantation → photoresist removal → P-body diffusion → N +JFETRegion lithography → N +JFETInject → remove glue → N +JFETAnd the process manufacturing flow before the growth of the sacrifice oxide layer and after the removal of the sacrifice oxide layer is consistent with the conventional flow.
The complete manufacturing process flow comprises the following steps: epitaxial wafer → laser marking → growth of sacrificial oxide layer → field limiting ring lithography → injection of field limiting ring → photoresist removal → annealing of field limiting ring → removal of oxide layer → growth of field oxide → field oxide lithography + etching → photoresist removal → growth of sacrificial oxide layer → P-body region lithography → P-body implantation → photoresist removal → P-body diffusion → N-body implantation+JFETArea lithography → N+JFETInject → strip → N+JFETActivation → removal of sacrificial oxide layer → growth of gate oxide layer → polysilicon deposition → polysilicon doping → polysilicon lithography + etching → photoresist removal → NSD lithography → NSD injection → photoresist removal → PSD lithography → PSD injection → photoresist removal → DP + lithography → DP + injection → photoresist removal → isolation layer deposition → reflow → lead hole lithography + etching → photoresist removal → front side metal aluminum sputtering → aluminum lithography + etching → photoresist removal → deposition of passivation layer → PAD lithography + etching → photoresist removal → alloy → back side thinning → back side metallization → CP testing → warehousing.
N+JFETThe diffusion window 4 is arranged between the two P-body diffusion windows 3, the length is 1.2-1.6 μm, and the technological parameters are as follows: implant material AsH3The implantation dose is 1e 15-1.5 e15,the injection energy is 80 Kev-90 Kev, the activation temperature is 850-900 ℃, and the activation time is 10-15 min.
The gate dielectric layer 5 is of a stepped structure, has a length of 4-5 μm, and is provided with a gate dielectric layer
The growth process condition is that the thickness of the gate dielectric layer 5 is divided into two parts, N +JFETThe thickness of the gate dielectric layer on the diffusion window 4 is
And the thickness of the gate dielectric layer on the P-body diffusion window 3 is
The length of the grid polysilicon 6 is 4-5 mu m, and the thickness is
The source N + diffusion window 7 has a length of 1.2 μm to 1.5. mu.m.
The length of the source P + diffusion window 8 is 2 μm to 3 μm.
The length of the gate-source isolation layer 9 is 6-7 μm, and the thickness is 0.8-1.2 μm.
The cell size, i.e., the size of the N + substrate 1 in fig. 1, is 8 μm to 10 μm.
The length of the P-body diffusion window 3 is 3.6 to 4 μm.
The technical scheme takes an N-channel MOSFET as an example and is suitable for a P-channel MOFET. In order to achieve the above purpose, compared with the prior unit cell structure schematic diagram shown in FIG. 2, the unit cell structure of the present invention has the advantage that N + is added between two P-body diffusion windows 3JFET Diffusion window 4, N +JFETThe implantation material is AsH3And is heavily doped. In the growth process of the gate dielectric layer, N +JFETThe oxidation growth rate on the diffusion window 4 is faster, the P-body area is lightly doped, and the oxidation growth on the P-body diffusion window 3 is normal, so that a step gate dielectric layer structure is formed. N + CJFETA thick gate dielectric layer on the diffusion window 4, and a gate dielectric layerThe breakdown voltage is improved, the single particle resistance of the device is enhanced, and N +JFETThe gate dielectric layer on the P-body channel region between the diffusion window 4 and the source N + diffusion window 7 is of normal process growth thickness, and the total dose resistance of the device is not affected.
FIG. 1 is compared with the prior art, N +JFETThe thickness of the gate dielectric layer on the diffusion window 4 is the same as that of the original structure
Is increased to
The breakdown voltage of the gate dielectric is improved, and the single-particle-resistant gate penetration capability is improved. Taking 200V and 500V products as examples, the statistics of the single-particle-resistant gate penetration test data in the technical scheme compared with the existing scheme are shown in the following table 1.
TABLE 1 comparison of Single particle resistance to Gate punch through
The structure of the invention is realized without additionally adding process equipment, is compatible with the plane process of the prior anti-radiation MOSFET, and only needs to add a step of N after P-body injection and diffusion and before gate dielectric layer growth in the process of manufacturing the process+JFETAnd (5) performing implantation and annealing processes. In the design process, the size and doping concentration of an injection window of the N + JFET are mainly considered to form N+JFETThe diffusion window should just abut the P-body diffusion window. The stepped gate dielectric layer structure obtained by the scheme can effectively improve the single-particle gate penetration resistance of the MOSFET.
Claims (8)
1. A step gate dielectric layer structure is characterized by comprising an N + substrate (1), an N-epitaxial layer (2), a P-body diffusion window (3) and N+JFETThe gate structure comprises a diffusion window (4), a gate dielectric layer (5), gate polysilicon (6) and a gate source isolation layer (9); an N-epitaxial layer (2) is arranged on an N + substrate (1), two sides of the N-epitaxial layer (2) are respectively provided with a P-body diffusion window (3), and the two P-body diffusion windowsAn N + JFET diffusion window (4) is arranged between the diffusion windows (3), a gate dielectric layer (5) is arranged on the P-body diffusion window (3) and the N + JFET diffusion window (4) in the longitudinal direction, and a gate polysilicon (6) and a gate source isolation layer (9) are sequentially arranged on the gate dielectric layer (5) from bottom to top; the gate dielectric layer (5) is of a stepped structure.
2. The step gate dielectric layer structure of claim 1, wherein the gate dielectric layer (5) is provided with an active N + diffusion window (7) and a source P + diffusion window (8), the source N + diffusion window (7), the source P + diffusion window (8) and a source metal are connected to form a source, a gate metal is connected to the gate polysilicon (6) to form a gate, and a drain metal is connected to the N + substrate (1) to form a drain.
3. The step gate dielectric layer structure of claim 1, wherein the gate dielectric layer (5) is a gate dielectric layer
The growth process condition is that the thickness of the gate dielectric layer (5) is divided into two parts, N+JFETThe thickness of the gate dielectric layer on the diffusion window (4) is as follows
And the thickness of the gate dielectric layer on the P-body diffusion window (3) is equal to
4. The step gate dielectric layer structure of claim 1, wherein the gate dielectric layer (5) has a length of 4 μm to 5 μm.
5. The step gate dielectric layer structure of claim 1, wherein N is+JFETThe diffusion window (4) is expanded in two P-bodiesThe length between the scattered windows (3) is 1.2-1.6 mu m; the length of the grid polysilicon (6) is 4-5 mu m, and the thickness is
6. The step gate dielectric layer structure of claim 2, wherein the length of the source N + diffusion window (7) is 1.2 μm to 1.5 μm; the length of the source P + diffusion window (8) is 2-3 mu m; the length of the gate-source isolation layer (9) is 6-7 μm, and the thickness is 0.8-1.2 μm; the size of the N + substrate (1) is 8-10 mu m; the length of the P-body diffusion window (3) is 3.6-4 μm.
7. A method for manufacturing a step gate dielectric layer structure, which is based on any one of claims 1 to 6, and comprises the following steps:
after P-body injection and diffusion and before gate dielectric layer growth, N+JFETThe injection and annealing process comprises the following specific process manufacturing flows: sacrificial oxide growth → P-body region lithography → P-body implantation → photoresist removal → P-body diffusion → N+JFETArea lithography → N+JFETInject → strip → N+JFETActivate → remove the sacrificial oxide layer.
8. The method of claim 7, wherein N is N+JFETThe diffusion window process parameters are as follows: injecting AsH3 as an injection material, with the injection dosage of 1e 15-1.5 e15, the injection energy of 80 Kev-90 Kev, the activation temperature of 850-900 ℃ and the activation time of 10-15 min.
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