CN113506798B

CN113506798B - ESD protection structure for integrated circuit

Info

Publication number: CN113506798B
Application number: CN202110722669.1A
Authority: CN
Inventors: 易永财; 朱小安; 邵宇; 叶平平
Original assignee: Ji'an Lixin Semiconductor Co ltd
Current assignee: Ji'an Lixin Semiconductor Co ltd
Priority date: 2021-06-28
Filing date: 2021-06-28
Publication date: 2023-05-12
Anticipated expiration: 2041-06-28
Also published as: CN113506798A

Abstract

The invention discloses an ESD protection structure for an integrated circuit, and relates to the technical field of electronics. The structure includes an IC chip and an ESD device; the first end of the ESD device is connected with the power port of the IC chip, the second end of the ESD device is connected with the I/O port of the IC chip, and the third end of the ESD device is connected with the grounding port of the IC chip; the ESD device is used for discharging ESD current between any two pins of the IC chip when the pins of the IC chip are impacted by ESD stress. Through the circuit structure, the ESD current between any two pins of the IC chip can be discharged by using one ESD device, and compared with a traditional mode, the invention can effectively reduce the complexity of the circuit and improve the use experience of a user.

Description

ESD protection structure for integrated circuit

Technical Field

The present invention relates to the field of electronic technology, and in particular, to an ESD protection structure for an integrated circuit.

Background

With the development of semiconductor technology and the improvement of integrated structure technology, the integration level of the integrated structure is higher and higher, but at the same time, the effect of electrostatic discharge (ESD, electrostatic Discharge) phenomenon on the structure is also larger and higher, and ESD protection is one of the important problems for chip designers.

During the operation of the chip, ESD events may occur between any two pins, ESD current may find a path with minimum resistance to flow through, and the ESD transient high voltage and large current may cause problems such as gate oxide breakdown, melting of pn junction silicon body, melting of contact melting tip, polysilicon or metal layer, etc.

In order to solve the above problems, the conventional method adopts an ESD device between any two pins of a chip to protect, but the method can make the ESD device used in the whole circuit more, resulting in more complicated circuit and serious device parasitics.

The foregoing is provided merely for the purpose of facilitating understanding of the technical solutions of the present invention and is not intended to represent an admission that the foregoing is prior art.

Disclosure of Invention

The invention mainly aims to provide an ESD protection structure for an integrated circuit, which aims to solve the technical problem that in the prior art, more ESD devices are used in the ESD protection process of a chip, so that a circuit is complicated.

To achieve the above object, the present invention provides an ESD protection structure for an integrated circuit, the structure including an IC chip and an ESD device;

the first end of the ESD device is connected with the power port of the IC chip, the second end of the ESD device is connected with the I/O port of the IC chip, and the third end of the ESD device is connected with the grounding port of the IC chip;

the ESD device is used for discharging ESD current between any two pins of the IC chip when the pins of the IC chip are impacted by ESD stress.

Optionally, the ESD device comprises a P-type substrate, a P-well region, and an N-well region;

the N well region and the P well region are formed on the P type substrate and are in contact with the P type substrate, and the N well region and the P well region are not closely adjacent;

the P well region comprises a first N+ contact region and a first P+ contact region, the first N+ contact region and the first P+ contact region are both positioned above the inside of the P well region, the first N+ contact region is isolated from the first P+ contact region, the first N+ contact region is connected with an I/O port of the IC chip, and the first P+ contact region is connected with a ground port of the IC chip;

the N well region comprises a second P+ contact region, the second P+ contact region is located above the inside of the N well region, and the second P+ contact region is connected with a power port of the IC chip.

Optionally, the ESD device further comprises a second n+ contact region;

the second N+ contact region is positioned in the N well region and is adjacent to the second P+ contact region, and the second N+ contact region is connected with a power port of the IC chip.

Optionally, the ESD device further comprises a third p+ contact region;

the third P+ contact region is positioned in the N well region and is isolated from the second P+ contact region, and the third P+ contact region is connected with a grounding port of the IC chip.

Optionally, the ESD device further comprises a third n+ contact region;

the third N+ contact region is positioned in the P well region, is adjacent to the first P+ contact region, is isolated from the first N+ contact region, and is connected with a grounding port of the IC chip.

Optionally, the ESD device further comprises a first gate;

the first grid electrode part is positioned on the upper surfaces of the first N+ contact region and the third N+ contact region, and the first grid electrode is connected with a grounding port of the IC chip.

Optionally, the first gate includes a first gate oxide region and a first polysilicon gate region;

the first gate oxide layer region is arranged on the upper surfaces of part of the first N+ contact region and the third N+ contact region, the first polysilicon gate region is arranged on the first gate oxide layer region, and the first polysilicon gate region is connected with a grounding port of the IC chip.

Optionally, the ESD device further comprises a second gate;

the second grid electrode part is positioned on the upper surfaces of the second P+ contact region and the third P+ contact region, and the second grid electrode part is connected with a power port of the IC chip.

Optionally, the second gate includes a second gate oxide region and a second polysilicon gate region;

the second gate oxide layer region is arranged on the upper surfaces of part of the second P+ contact region and the third P+ contact region, the second polysilicon gate region is arranged on the second gate oxide layer region, and the second polysilicon gate region is connected with a grounding port of the IC chip.

Optionally, the ESD device further comprises an SOI structure and a P-type epitaxial region;

the SOI structure is positioned above the P-type substrate, the P-type epitaxial region is positioned above the SOI structure, and the N well region and the P well region are formed on the P-type epitaxial region and are in contact with the P-type epitaxial region.

The invention provides an ESD protection structure for an integrated circuit, which comprises an IC chip and an ESD device; the first end of the ESD device is connected with the power port of the IC chip, the second end of the ESD device is connected with the I/O port of the IC chip, and the third end of the ESD device is connected with the grounding port of the IC chip; the ESD device is used for discharging ESD current between any two pins of the IC chip when the pins of the IC chip are impacted by ESD stress. Through the structure, the power port, the I/O port and the grounding port of the chip are respectively connected through one ESD device, so that when the power port of the chip is impacted by ESD stress, a corresponding current discharging path can be formed through the ESD device to discharge the generated ESD current, and the internal circuit of the chip is protected from being damaged by the ESD current. The invention has simple circuit structure, can greatly reduce the complexity and the chip area of the circuit, simplifies the ESD circuit and can effectively improve the use experience of users.

Drawings

FIG. 1 is a schematic diagram illustrating a first embodiment of an ESD protection structure for an integrated circuit;

fig. 2 is a schematic structural diagram of an ESD device according to a second embodiment of the ESD protection structure for an integrated circuit of the present invention;

fig. 3 is a schematic structural diagram of an ESD device according to a third embodiment of the ESD protection structure for an integrated circuit of the present invention.

Reference numerals illustrate:

reference numerals	Name of the name	Reference numerals	Name of the name
				10	IC chip	20	ESD device
1	Chip power port	2	Chip I/O port
				3	Chip grounding port	01	P-type substrate
02	P-well region	03	N well region
				04	SOI structure	05	P-type epitaxial region
11-13	First to third P+ contact regions	21-23	First to third N+ contact regions
				31-31	First to second gate oxide regions	41-42	First to second polysilicon gate regions

The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.

Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the technical solutions should be considered that the combination does not exist and is not within the scope of protection claimed by the present invention.

Referring to fig. 1, fig. 1 is a schematic connection diagram of a first embodiment of an ESD protection structure for an integrated circuit according to the present invention. Referring to fig. 1, a first embodiment of an ESD protection structure for an integrated circuit according to the present invention is presented.

As shown in fig. 1, in the present embodiment, an ESD protection structure for an integrated circuit includes an IC chip 10 and an ESD device 20.

It should be noted that ESD, i.e. electrostatic discharge, is a phenomenon commonly existing in nature, and in the use process of an integrated circuit, an external environment or working conditions can cause an IC chip to generate static electricity, so that an ESD device is required to discharge the generated static electricity so as to protect an internal circuit of the IC chip from being damaged by ESD current.

A first terminal of the ESD device 20 is connected to the power port 1 of the IC chip 10, a second terminal of the ESD device 20 is connected to the I/O port 2 of the IC chip 10, and a third terminal of the ESD device 20 is connected to the ground port 3 of the IC chip 10.

It will be readily appreciated that since ESD events may occur between any two pins of the IC chip, the resulting ESD current will find a path of least resistance to flow through, and thus ESD stress shock needs to be considered for each pin of the chip, the ESD device 20 needs to be connected between any two pins of the IC chip 10, so that the ESD device 20 can discharge static electricity between any two pins of the IC chip 10.

The ESD device 20 is configured to discharge ESD current between any two pins of the IC chip 10 when the pins of the IC chip 10 are impacted by ESD stress.

It should be noted that, when the different pins of the IC chip are impacted by ESD stress, different current discharging paths may be correspondingly formed in the ESD device 20 to discharge ESD static electricity.

In an implementation, when the pins between the power port 1 and the I/O port 2 of the IC chip are subjected to ESD shock, diodes with PNP structure and PN structure may be formed inside the ESD device 20 to construct a current drain path. When the pin between the I/O port 2 and the power port 1 of the IC chip is subjected to ESD shock, an NPN structure path is correspondingly formed inside the ESD device 20 to discharge ESD current. When the pins between the power port 1 and the ground port 3 of the IC chip are subjected to ESD shock, a PNP structure is correspondingly formed inside the ESD device 20 to clamp the ESD voltage, and meanwhile, an anti-latch-up effect is achieved, so that the integrity of the internal components is ensured. When the pins between the I/O port 2 and the G ground port 3 of the IC chip are subjected to ESD shock, an NPN structure is correspondingly formed inside the ESD device 20 to discharge ESD current, and meanwhile, noise immunity is achieved, and voltage is clamped.

The embodiment provides an ESD protection structure for an integrated circuit, wherein the structure comprises an IC chip and an ESD device; the first end of the ESD device is connected with the power port of the IC chip, the second end of the ESD device is connected with the I/O port of the IC chip, and the third end of the ESD device is connected with the grounding port of the IC chip; the ESD device is used for discharging ESD current between any two pins of the IC chip when the pins of the IC chip are impacted by ESD stress. Through the structure, the process that the ESD current between any two pins of the IC chip can be discharged by only using one ESD device is realized, and compared with a traditional mode, the structure provided by the embodiment is simple in wiring, the complexity of a circuit and the area of the chip can be effectively reduced, meanwhile, materials are saved, and the use experience of a user is improved.

Referring to fig. 2, fig. 2 is a schematic structural diagram of an ESD device according to a second embodiment of the ESD protection structure for an integrated circuit of the present invention. Based on the above-described first embodiment, a second embodiment of the present invention is proposed.

In the second embodiment, the ESD device 20 includes a P-type substrate 01, a P-well 02, and an N-well 03;

the N well region 03 and the P well region 02 are formed on the P type substrate and are in contact with the P type substrate, and the N well region 03 is not adjacent to the P well region 02;

the P-well region 02 includes a first n+ contact region 21 and a first p+ contact region 11, wherein the first n+ contact region 21 and the first p+ contact region 11 are both located above the P-well region 02, the first n+ contact region 21 is isolated from the first p+ contact region 11, the first n+ contact region 21 is connected with the I/O port 2 of the IC chip, and the first p+ contact region 11 is connected with the ground port 3 of the IC chip.

The N-well region 03 includes a second p+ contact region 12, the second p+ contact region 12 is located above the inside of the N-well region 03, and the second p+ contact region 12 is connected to the power port 1 of the IC chip 10.

It is easy to understand that when the pins between the power port 1 and the I/O port 2 of the IC chip 10 are subjected to ESD shock, the second p+ contact region 12, the N well region 03, and the P-type substrate 01 form a PNP structure, and the diode formed by the P well region 02 and the first n+ contact region 21 forms a current drain path, so that the ESD current is discharged to ensure that the internal circuit of the IC chip is not impacted by ESD.

The ESD device 20 further comprises a second n+ contact region 22;

the second n+ contact region 22 is located in the N well region 03 and is adjacent to the second p+ contact region 12, and the second n+ contact region 22 is connected to the power port 1 of the IC chip 10.

It will be readily appreciated that under this structure, when the pin between the I/O port 2 of the IC chip 10 and the power supply port 1 is subjected to ESD shock, the structure may bleed ESD current through the NPN structure formed by the first n+ contact region 21, the P-well region 02, the P-type substrate 01, the N-well region 03, and the second n+ contact region 22.

The ESD device 20 further comprises a third p+ contact region 13;

the third p+ contact region 13 is located in the N-well region 03 and is isolated from the second p+ contact region 12, and the third p+ contact region 13 is connected to the ground port 3 of the IC chip 10.

It is easy to understand that, under this structure, when the pin between the power port 1 and the ground port 3 of the IC chip is subjected to ESD shock, the PNP structure formed by the second p+ contact region 12, the N well region 03, and the third p+ contact region 13 clamps the ESD voltage, and also has an anti-latch effect, so that the integrity of the internal components of the IC chip 10 is further ensured.

The ESD device 20 further comprises a third n+ contact region 23;

the third n+ contact region 23 is located in the P-well region 02 and is adjacent to the first p+ contact region 11, and is isolated from the first n+ contact region 21, and the third n+ contact region 23 is connected to the ground port 3 of the IC chip 10.

It is easy to understand that, in this structure, when the pin between the I/O port 2 and the ground port 3 of the IC chip 10 is subjected to ESD attack, the NPN structure formed by the first n+ contact region 21, the P-well region 02 and the third n+ contact region 23 can discharge ESD current, clamp voltage, and meanwhile, the structure can resist noise.

The ESD device 20 further comprises a first gate;

the first gate part is located on the upper surfaces of the first n+ contact region 21 and the third n+ contact region 23, and the first gate is connected to the ground port 3 of the IC chip 10.

The first gate includes a first gate oxide region 31 and a first polysilicon gate region 41;

the first gate oxide region 31 is disposed on a portion of the upper surfaces of the first n+ contact region 21 and the third n+ contact region 23, the first polysilicon gate region 41 is disposed on the first gate oxide region 31, and the first polysilicon gate region 41 is connected to the ground port 3 of the IC chip 10.

The ESD device 20 further comprises a second gate;

the second gate part is located on the upper surfaces of the second p+ contact region 12 and the third p+ contact region 13, and the second gate is connected to the power port 1 of the IC chip 10.

The second gate includes a second gate oxide region 32 and a second polysilicon gate region 42;

the second gate oxide region 32 is disposed on a portion of the upper surfaces of the second p+ contact region 12 and the third p+ contact region 13, the second polysilicon gate region 42 is disposed on the second gate oxide region 32, and the second polysilicon gate region 42 is connected to a ground port of the IC chip.

Note that, the gate oxide thicknesses of the first gate oxide region 31 and the second gate oxide region 32 may directly affect the performance of the transistor, and the reduced gate oxide thickness may enhance the current driving capability of the transistor and improve the speed and power characteristics, so, with respect to the structure in this embodiment, the gate oxide thicknesses of the first gate oxide region 31 and the second gate oxide region 32 may be specifically set according to the specific implementation scenario, which is not limited in this embodiment.

In a second embodiment, an ESD device structure is provided, under which a corresponding ESD current discharge path can be formed according to ESD stress shocks between different pins of an IC chip, and electrostatic discharge between any two pins of the IC chip is achieved.

Referring to fig. 3, fig. 3 is a schematic structural diagram of an ESD device according to a third embodiment of the ESD protection structure for an integrated circuit of the present invention. Based on the above-described second embodiment, a third embodiment of the present invention is proposed.

The ESD device 20 further comprises an SOI structure 04 and a P-type epitaxial region 05;

the SOI structure 04 is located above the P-type substrate 01, the P-type epitaxial region 05 is located above the SOI structure 04, and the N-well region 03 and the P-well region 02 are formed on the P-type epitaxial region 05 and are in contact with the P-type epitaxial region 05.

It should be noted that the SOI (Silicon-On-Insulator) structure is one in which a buried oxide layer is introduced between the top Silicon layer and the bottom of the backing. By forming the semiconductor thin film on the insulator, a better isolation effect can be achieved, and parasitic phenomenon is avoided.

In this embodiment, the ESD device further includes an SOI structure and a P-type epitaxial region; the SOI structure is positioned above the P-type substrate, the P-type epitaxial region is positioned above the SOI structure, and the N well region and the P well region are formed on the P-type epitaxial region and are in contact with the P-type epitaxial region. By introducing the SOI structure, isolation can be better realized, and parasitic phenomenon is avoided.

The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims

1. An ESD protection structure for an integrated circuit, the structure comprising an IC chip and an ESD device;

the ESD device is used for discharging ESD current between any two pins of the IC chip when the pins of the IC chip are impacted by ESD stress;

the ESD device comprises a P-type substrate, a P-type well region, an N-type well region and a third P+ contact region;

the N well region comprises a second P+ contact region, the second P+ contact region is positioned above the inside of the N well region, and the second P+ contact region is connected with a power port of the IC chip;

2. The structure of claim 1 wherein the ESD device further comprises a second n+ contact region;

3. The structure of claim 2 wherein the ESD device further comprises a third n+ contact region;

4. The structure of claim 3 wherein said ESD device further comprises a first gate;

5. The structure of claim 4 wherein said first gate comprises a first gate oxide region and a first polysilicon gate region;

6. The structure of claim 5 wherein the ESD device further comprises a second gate;

7. The structure of claim 6 wherein said second gate comprises a second gate oxide region and a second polysilicon gate region;

8. The structure of claim 7 wherein said ESD device further comprises an SOI structure and a P-type epitaxial region;