CN113505645B - Gating circuit and optical sensor circuit - Google Patents
Gating circuit and optical sensor circuit Download PDFInfo
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- CN113505645B CN113505645B CN202110640262.4A CN202110640262A CN113505645B CN 113505645 B CN113505645 B CN 113505645B CN 202110640262 A CN202110640262 A CN 202110640262A CN 113505645 B CN113505645 B CN 113505645B
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- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
- G01D5/26—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light
Abstract
The present disclosure relates to a gating circuit and an optical sensor circuit, including: the device comprises a gating unit, an initialization unit, a compensation unit and a bootstrap unit, wherein the gating unit comprises a first switching transistor and a second switching transistor; the first end of the first switching transistor is electrically connected with the bias voltage signal end, the second end of the first switching transistor is electrically connected with the first end of the second transistor, the control end of the first switching transistor is electrically connected with the first node, and the second end of the second switching transistor is electrically connected with the first bias voltage signal output end; the first end of the initialization unit is electrically connected with the first signal end, the second end of the initialization unit is electrically connected with the first node, and the control end of the initialization unit is electrically connected with the first control signal end; a first end of the bootstrap unit is electrically connected with the second control signal end and the control end of the second switching transistor respectively, and a second end of the bootstrap unit is electrically connected with the first node; noise in the acquired current signal can be reduced.
Description
Technical Field
The present disclosure relates to the field of optical identification technologies, and in particular, to a gating circuit and an optical sensor circuit.
Background
With the rapid development of optical identification technology, the optical identification technology can be applied to the field of optical fingerprint identification or the digital X-ray in the optical identification technology can be applied to the field of medical equipment, and the main principle is to form an identification image through the optical identification technology for fingerprint identification or medical diagnosis.
When an optical sensor circuit in an existing optical recognition device collects an image, a plurality of rows of optical elements are arranged in the optical sensor circuit and used for sensing illumination, and when the current of one row of photoelectric elements is collected under a small illumination condition, the rest rows of photoelectric elements generate signal interference when being illuminated, so that a large amount of noise exists in a finally collected current signal, and the recognition capability of the sensor on low-brightness illumination is low.
Disclosure of Invention
To solve the above technical problem or at least partially solve the above technical problem, the present disclosure provides a gating circuit and an optical sensor circuit, which can reduce noise in a collected current signal and improve the recognition capability of a sensor for low-brightness illumination.
In a first aspect, an embodiment of the present disclosure provides a gating circuit, including:
The device comprises a gating unit, an initialization unit, a compensation unit and a bootstrap unit, wherein the gating unit comprises a first switching transistor and a second switching transistor;
the first end of the first switching transistor is electrically connected with a bias voltage signal end, the second end of the first switching transistor is electrically connected with the first end of the second transistor, the control end of the first switching transistor is electrically connected with a first node, and the second end of the second switching transistor is electrically connected with a first bias voltage signal output end;
a first end of the initialization unit is electrically connected with a first signal end, a second end of the initialization unit is electrically connected with the first node, a control end of the initialization unit is electrically connected with a first control signal end, and the initialization unit is used for initializing the potential of the first node when the first control signal end outputs a first control signal;
a first end of the compensation unit is electrically connected with a second end of the first switching transistor, a second end of the compensation unit is electrically connected with a second bias voltage signal output end, a control end of the compensation unit is electrically connected with a control end of the initialization unit, and the compensation unit is used for outputting a bias voltage signal to the second bias voltage signal output end when the first control signal end outputs a first control signal;
A first end of the bootstrap unit is electrically connected to a second control signal end and a control end of the second switching transistor, respectively, a second end of the bootstrap unit is electrically connected to the first node, and the bootstrap unit is configured to pull up an electric potential of the control end of the first switching transistor when the second control signal end outputs a second control signal;
the time sequence of the first control signal output by the first control signal end is positioned before the time sequence of the second control signal output by the second control signal end.
Optionally, the apparatus further comprises a first reset unit;
the first end of the first resetting unit is electrically connected with the second signal end, the second end of the first resetting unit is electrically connected with the first node, the control end of the first resetting unit is electrically connected with the third control signal end, and the first resetting unit is used for resetting the potential of the first node when the third control signal end outputs a third control signal;
and the time sequence of the third control signal end outputting the third control signal is positioned behind the time sequence of the second control signal end outputting the second control signal.
Optionally, the apparatus further comprises a second reset unit;
The first end of the second resetting unit is electrically connected with the third signal end, the second end of the second resetting unit is electrically connected with the control end of the initialization unit, the control end of the second resetting unit is electrically connected with the fourth control signal end, and the second resetting unit is used for enabling the initialization unit and the compensation unit to be in a cut-off state when the fourth control signal end outputs a fourth control signal;
the time sequence of the fourth control signal output by the fourth control signal end is the same as the time sequence of the second control signal output by the second control signal end.
Optionally, the second control signal end is electrically connected to the fourth control signal end.
Optionally, the initialization unit includes a third switching transistor, a first end of the third switching transistor is electrically connected to the first signal end, a second end of the third switching transistor is electrically connected to the first node, and a control end of the third switching transistor is electrically connected to the first control signal end.
Optionally, the compensation unit includes a fourth switching transistor, a first end of the fourth switching transistor is electrically connected to the second end of the first switching transistor, a second end of the fourth switching transistor is electrically connected to the second bias voltage signal output end, and a control end of the fourth switching transistor is electrically connected to a control end of the third switching transistor.
Optionally, the first reset unit includes a fifth switching transistor, a first end of the fifth switching transistor is electrically connected to the second signal end, a second end of the fifth switching transistor is electrically connected to the first node, and a control end of the fifth switching transistor is electrically connected to the third control signal end;
the second reset unit comprises a sixth switching transistor, the first end of the sixth switching transistor is electrically connected with the third signal end, the second end of the sixth switching transistor is electrically connected with the control end of the third switching transistor, and the control end of the sixth switching transistor is electrically connected with the fourth control signal end.
Optionally, the bootstrap unit includes a capacitor, a first end of the capacitor is electrically connected to the second control signal end and the control end of the second switching transistor, respectively, and a second end of the capacitor is electrically connected to the first node.
In a second aspect, embodiments of the present disclosure further provide an optical sensor circuit, including a plurality of gating circuits according to any one of the first aspects, further including:
the photoelectric element array comprises photoelectric sensing units arranged in a plurality of rows;
the scanning lines are connected with the photoelectric sensing units in a corresponding row;
Each gating circuit is electrically connected with one bias voltage signal line, and each bias voltage signal line is connected with the photoelectric sensing unit in a corresponding row;
when one scanning line is gated, the gating circuit writes a bias voltage signal of a bias voltage signal end into a bias voltage signal line corresponding to the scanning line through a first bias voltage signal output end.
Optionally, each gating circuit is connected to one scan line in the same row and one bias voltage signal line corresponding to one scan line in the same row.
Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:
the gate circuit provided by the embodiment of the disclosure includes a gate unit, an initialization unit, a compensation unit and a bootstrap unit, the initialization unit initializes a first node potential at a stage T1, the compensation unit outputs a bias voltage signal to a second bias voltage signal output terminal at a stage T1, and the bootstrap unit pulls up a potential of a control terminal of the first switching transistor at a stage T2, so that the first switching transistor is in a complete conduction state at a stage T2, thereby ensuring that the bias voltage signal is completely written into the first bias voltage signal output terminal, and improving accuracy and stability of a recognition result of the photoelectric sensing unit for low-brightness illumination. In addition, at stage T1, the compensation unit outputs a bias voltage signal to the second bias voltage signal output terminal, that is, the bias voltage signal of the photo-sensing units in the previous row corresponding to the current row is enhanced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a gating circuit provided in an embodiment of the present disclosure;
FIG. 2 is a timing diagram corresponding to the gating circuit provided in FIG. 1;
FIG. 3 is a schematic diagram of another gating circuit according to an embodiment of the present disclosure;
FIG. 4 is a timing diagram corresponding to the gating circuit provided in FIG. 3;
FIG. 5 is another timing diagram corresponding to the gating circuit provided in FIG. 3;
FIG. 6 is a schematic diagram of a structure of another gating circuit provided in the embodiments of the present disclosure;
FIG. 7 is a timing diagram corresponding to the gating circuit provided in FIG. 6;
FIG. 8 is a schematic diagram of an optical sensor circuit according to an embodiment of the present disclosure;
Fig. 9 is a schematic structural diagram of another optical sensor circuit provided in an embodiment of the disclosure.
10, a gating unit; 20. an initialization unit; 30. a compensation unit; 40. a bootstrap unit; 50. a first reset unit; 60. a second reset unit; k1, a first switching transistor; k2, a second switching transistor; k3, a third switching transistor; k4, a fourth switching transistor; k5, a fifth switching transistor, K6, a sixth switching transistor; C. a capacitor; bias, Bias voltage signal terminal; n1, first node; bn, a first bias voltage signal output end; bn-1 and a second bias voltage signal output end; gn-1, a first control signal terminal; gn, a second control signal terminal; gn +1, a third control signal terminal; gn +2 and a fourth control signal terminal; CK. A first signal terminal; XCK, a second signal terminal; vgl, third signal terminal.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.
Fig. 1 is a schematic structural diagram of a gating circuit according to an embodiment of the present disclosure, and fig. 2 is a timing diagram corresponding to the gating circuit provided in fig. 1, and in conjunction with fig. 1 and fig. 2, the gating circuit includes: the gate unit 10 comprises a first switch transistor K1 and a second switch transistor K2, a first end of the first switch transistor K1 is electrically connected with a Bias voltage signal end Bias, a second end of the first switch transistor K1 is electrically connected with a first end of the second transistor, a control end of the first switch transistor K1 is electrically connected with a first node N1, and a second end of the second switch transistor K2 is electrically connected with a first Bias voltage signal output end Bn. The first terminal of the initialization unit 20 is electrically connected to the first signal terminal CK, the second terminal of the initialization unit 20 is electrically connected to the first node N1, the control terminal of the initialization unit 20 is electrically connected to the first control signal terminal Gn-1, and the initialization unit 20 is configured to initialize the potential of the first node N1 when the first control signal terminal Gn-1 outputs the first control signal. The first terminal of the compensation unit 30 is electrically connected to the second terminal of the first switching transistor K1, the second terminal of the compensation unit 30 is electrically connected to the second bias voltage signal output terminal Bn-1, the control terminal of the compensation unit 30 is electrically connected to the control terminal of the initialization unit 20, and the compensation unit 30 is configured to output a bias voltage signal to the second bias voltage signal output terminal Bn-1 when the first control signal terminal Gn-1 outputs the first control signal. The first terminal of the bootstrap unit 40 is electrically connected to the second control signal terminal Gn and the control terminal of the second switch transistor K2, the second terminal of the bootstrap unit 40 is electrically connected to the first node N1, the bootstrap unit 40 is configured to pull up the potential of the control terminal of the first switch transistor K1 when the second control signal terminal Gn outputs the second control signal, wherein a timing of the first control signal terminal Gn-1 outputting the first control signal is before a timing of the second control signal terminal Gn outputting the second control signal.
Illustratively, referring to fig. 1 and 2, the gate circuit includes a gate unit 10, an initializing unit 20, a compensating unit 30, and a bootstrap unit 40, a first terminal of the initializing unit 20 is electrically connected to a first signal terminal CK, a second terminal of the initializing unit 20 is electrically connected to a first node N1, a control terminal of the initializing unit 20 is electrically connected to a first control signal terminal Gn-1, the first control signal terminal Gn-1 is high level at a T1 stage, that is, the first control signal terminal Gn-1 outputs a first control signal, the initializing unit 20 and the compensating unit 30 are turned on by the first control signal, the initializing unit 20 writes the first signal of the first signal terminal CK to a first node N1, at which time, a first switching transistor K1 of the gate unit 10 is turned on after the first signal of the first signal terminal CK is written to a first node N1, since the control terminal of the compensating unit 30 is also electrically connected to the first control signal terminal Gn-1, therefore, the compensation unit 30 is turned on at stage T1, and the Bias voltage signal output from the Bias voltage signal terminal Bias is output to the second Bias voltage signal output terminal Bn-1 through the first switch transistor K1 and the compensation unit 30. At the stage of T1, the enhancement of the Bias voltage signal of the second Bias voltage signal line is realized by outputting the Bias voltage signal output by the Bias voltage signal terminal Bias to the second Bias voltage signal output terminal Bn-1.
It should be noted that the second bias voltage signal output end Bn-1 corresponds to an input end of the photo sensing unit connected to the previous gate circuit. Illustratively, if the current gating circuit is used to output the Bias voltage signal to the Bias voltage signal line of the sensor cell in the nth row, the Bias voltage signal at the Bias voltage signal terminal Bias is output to the second Bias voltage signal output terminal Bn-1 at stage T1, where the second Bias voltage signal output terminal Bn-1 corresponds to the input terminal of the Bias voltage signal line of the sensor cell in the nth row.
The first terminal of the bootstrap unit 40 is electrically connected to the second control signal terminal Gn and the control terminal of the second switch transistor K2, respectively, the second terminal of the bootstrap unit 40 is electrically connected to the first node N1, and in a stage T2, the first control signal terminal Gn-1 is at a low level, that is, the first control signal terminal Gn-1 does not output the first control signal, at this time, the control terminals of the initialization unit 20 and the compensation unit 30 do not receive the first control signal, and the initialization unit 20 and the compensation unit 30 are in an off state. The second control signal terminal Gn is at a high level, that is, the second control signal terminal Gn outputs a second control signal, at this time, the second switch transistor K2 of the gating unit 10 is turned on under the effect of the second control signal, and the bootstrap unit 40 writes the second control signal output by the second control signal terminal Gn into the first node N1, so that the first node N1 is bootstrapped to a higher potential, and at this time, the first switch transistor K1 of the gating unit 10 is in a fully-on state. At stage T2, the first switch transistor K1 and the second switch transistor K2 of the gating unit 10 are both in a conducting state, and at this time, the Bias voltage signal output by the Bias voltage signal terminal Bias is output to the first Bias voltage signal output terminal Bn through the first switch transistor K1 and the second switch transistor K2. At the stage T2, when the second control signal is output by the second control signal terminal Gn, the bootstrap unit 40 is coupled by the second control signal, so that the voltage of the first node N1 is raised, and further the first switch transistor K1 is in a fully open state, thereby avoiding a situation that a Bias voltage signal output by the Bias voltage signal terminal Bias cannot be completely written into the first Bias voltage signal output terminal Bn because the first switch transistor K1 is not completely turned on, and improving the accuracy and stability of the operation of the photo-electric sensing unit when receiving the illumination signal.
With continued reference to fig. 2, in the timing diagram of the gate circuit, the timing at which the first control signal terminal Gn-1 outputs the first control signal is before the timing at which the second control signal terminal Gn outputs the second control signal, i.e., the period T1, the first control signal terminal Gn-1 outputs the first control signal, and in the period T2, the second control signal terminal Gn outputs the second control signal, so that the gate circuit initializes the potential of the first node N1 in the period T1, and bootstraps the potential of the first node N1 in the period T2, thereby making the first switching transistor K1 in the full-on state in the period T2.
In fig. 2, the first signal terminal CK does not output the first signal at the stage T11, and outputs the first signal at the stage T12, that is, at the stage T11, the first control signal terminal Gn-1 outputs the first control signal to the control terminal of the initialization unit 20 to control the initialization unit 20 to be turned on, and at the stage T12, the initialization unit 20 is in a fully turned-on state under the action of the first control signal, so that at this stage, the first signal terminal CK is at a high level, that is, the first signal terminal CK outputs the first signal to the first node N1 through the turned-on initialization unit 20.
The gate circuit provided by the embodiment of the disclosure includes a gate unit, an initialization unit, a compensation unit and a bootstrap unit, the initialization unit initializes a first node potential at a stage T1, the compensation unit outputs a bias voltage signal to a second bias voltage signal output terminal at a stage T1, and the bootstrap unit pulls up a potential of a control terminal of the first switching transistor at a stage T2, so that the first switching transistor is in a complete conduction state at a stage T2, thereby ensuring that the bias voltage signal is completely written into the first bias voltage signal output terminal, and improving accuracy and stability of a recognition result of the photoelectric sensing unit for low-brightness illumination. In addition, at stage T1, the compensation unit outputs a bias voltage signal to the second bias voltage signal output terminal, that is, the bias voltage signal of the photo-sensing units in the previous row corresponding to the current row is enhanced.
Optionally, on the basis of the foregoing embodiment, fig. 3 is a schematic structural diagram of another gating circuit provided in the present disclosure, fig. 4 is a timing diagram corresponding to the gating circuit provided in fig. 3, and with reference to fig. 3 and fig. 4, the gating circuit further includes a first resetting unit 50, a first end of the first resetting unit 50 is electrically connected to the second signal terminal XCK, a second end of the first resetting unit 50 is electrically connected to the first node N1, a control end of the first resetting unit 50 is electrically connected to the third control signal terminal Gn +1, the first resetting unit 50 is configured to reset the potential of the first node N1 when the third control signal terminal Gn +1 outputs the third control signal, where a timing at which the third control signal terminal Gn +1 outputs the third control signal is after a timing at which the second control signal terminal Gn outputs the second control signal.
With reference to fig. 3 and 4, the gating circuit further includes a first reset unit 50, a first terminal of the first reset unit 50 is electrically connected to the second signal terminal XCK, a second terminal of the first reset unit 50 is electrically connected to the first node N1, a control terminal of the first reset unit 50 is electrically connected to the third control signal terminal Gn +1, in a T3 phase, the third control signal terminal Gn +1 is at a high level, that is, the third control signal terminal Gn +1 outputs a third control signal, the first reset unit 50 is turned on by the third control signal, and a second signal output by the second signal terminal XCK is output to the first node N1 through the first reset unit 50. Since the first node N1 is at a high potential at the stage T2, in order to avoid the influence of the bias voltage signal written to the photo-sensing unit in the current row on the bias voltage signal written to the photo-sensing unit in the next row, the first node N1 is reset after the bias voltage signal is written to the first bias voltage signal output terminal Bn, so that the first switching transistor K1 is completely turned off, and the second signal (the second signal may correspond to a low potential signal) is output to the first node N1 through the second signal terminal XCK, so that the first switching transistor K1 is completely turned off under the action of the second signal.
It should be noted that the low-level signal may be directly output to the first node N1 through the second signal terminal XCK, or the second signal terminal XCK may be configured to output the high-level signal at the stage T31 and output the low-level signal at the stage T32, as shown in fig. 5, the potential of the first node N1 is first pulled down to the high level at the stage T31, and then the potential of the first node N1 is pulled down to the low level at the stage T32, so that the first switching transistor K1 is completely turned off.
According to the gating circuit provided by the embodiment of the disclosure, the first reset unit is arranged in the gating circuit, and after the bias voltage signal is written into the first bias voltage signal output end, the first reset unit is adopted to reset the first node, so that the first switching transistor of the gating unit is completely turned off after the bias voltage signal is written into the first bias voltage signal output end, and the influence of the bias voltage signal written into the photoelectric sensing unit of the current row on the writing of the bias voltage signal into the photoelectric sensing unit of the next row is avoided.
Alternatively, on the basis of the above embodiment, fig. 6 is a schematic structural diagram of another gate circuit provided by the embodiment of the present disclosure, and fig. 7 is a timing diagram corresponding to the gate circuit provided by fig. 6, and with reference to fig. 6 and fig. 7, the gate circuit further includes a second reset unit 60, a first end of the second reset unit 60 is electrically connected to the third signal terminal Vgl, a second end of the second reset unit 60 is electrically connected to the control terminal of the initialization unit 20, a control terminal of the second reset unit 60 is electrically connected to the fourth control signal terminal Gn +2, the second reset unit 60 is configured to enable the initialization unit 20 and the compensation unit 30 to be in an off state when the fourth control signal terminal Gn +2 outputs the fourth control signal, wherein a timing when the fourth control signal terminal Gn +2 outputs the fourth control signal is the same as a timing when the second control signal terminal Gn outputs the second control signal.
Referring to fig. 6 and 7, the gate circuit further includes a second reset unit 60, a first terminal of the second reset unit 60 is electrically connected to the third signal terminal Vgl, a second terminal of the second reset unit 60 is electrically connected to the control terminal of the initializing unit 20, and the control terminal of the second reset unit 60 is electrically connected to the fourth control signal terminal Gn + 2. Since the first node N1 is coupled to the high potential through the bootstrap circuit at the stage T2, at this time, the initialization unit 20 electrically connected to the first node N1 may leak current when the first node N1 is at the high potential, and then the control terminal of the initialization unit 20 may rise to the high potential, after the control terminal of the initialization unit 20 is raised to the high potential, the compensation unit 30 is turned on at the stage T2, the Bias voltage signal output by the Bias voltage signal terminal Bias is output to the second Bias voltage signal output terminal Bn-1 through the first switch transistor K1 and the compensation unit 30, and the problem of error writing of the Bias voltage signal occurs. In order to avoid the erroneous writing of the offset voltage signal into the second offset voltage signal output terminal Bn-1 in the stage T2, the second reset unit 60 is provided, in the stage T2, the fourth control signal terminal Gn +2 outputs the fourth control signal to the control terminal of the second reset unit 60, the second reset unit 60 outputs the third signal (the third signal corresponds to the low-potential signal) output by the third signal terminal Vgl under the action of the fourth control signal, and the control terminals of the initialization unit 20 and the compensation unit 30 are in the complete cut-off state after receiving the third signal, thereby avoiding the erroneous writing of the offset voltage signal into the second offset voltage signal output terminal Bn-1.
Optionally, the second control signal terminal Gn is electrically connected to the fourth control signal terminal Gn + 2.
Since the fourth control signal terminal Gn +2 outputs the fourth control signal to the control terminal of the second reset unit 60 at the stage T2, that is, the timing at which the fourth control signal terminal Gn +2 outputs the fourth control signal is the same as the timing at which the second control signal terminal Gn outputs the second control signal, in order to reduce the signal lines of the gate circuit, the complexity of the gate circuit is reduced by electrically connecting the second control signal terminal Gn to the fourth control signal terminal Gn +2, that is, by transferring the control signals to the second control signal terminal Gn and the fourth control signal terminal Gn +2 through one signal line.
Alternatively, the initialization unit 20 includes a third switching transistor K3, a first terminal of the third switching transistor K3 is electrically connected to the first signal terminal CK, a second terminal of the third switching transistor K3 is electrically connected to the first node N1, and a control terminal of the third switching transistor K3 is electrically connected to the first control signal terminal Gn-1.
With reference to fig. 1 and 2, the initialization unit 20 includes a third switching transistor K3, wherein during a period T1, the first control signal terminal Gn-1 outputs a first control signal (i.e., a high-level signal), the third switching transistor K3 is turned on by the first control signal, and the first signal terminal CK outputs the first signal to the first node N1 through the third switching transistor K3, so that the potential of the first node N1 is initialized during a period T1.
Optionally, the compensation unit 30 includes a fourth switching transistor K4, a first end of the fourth switching transistor K4 is electrically connected to a second end of the first switching transistor K1, a second end of the fourth switching transistor K4 is electrically connected to the second bias voltage signal output end Bn-1, and a control end of the fourth switching transistor K4 is electrically connected to a control end of the third switching transistor K3.
With continued reference to fig. 1 and 2, the compensation unit 30 includes a fourth switching transistor K4, and during a period T1, the first control signal terminal Gn-1 outputs a first control signal (i.e., a high level signal), and the fourth switching transistor K4 is turned on by the first control signal. Since the third switching transistor K3 writes the first signal of the first signal terminal CK to the first node N1 at the stage of T1, the first switching transistor K1 is turned on at the stage of T1, and the Bias voltage signal output from the Bias voltage signal terminal Bias is output to the second Bias voltage signal output terminal Bn-1 through the first switching transistor K1 and the fourth switching transistor K4, thereby enhancing the Bias voltage signal of the second Bias voltage signal line.
Optionally, the first reset unit 50 includes a fifth switch transistor K5, a first terminal of the fifth switch transistor K5 is electrically connected to the second signal terminal XCK, a second terminal of the fifth switch transistor K5 is electrically connected to the first node N1, and a control terminal of the fifth switch transistor K5 is electrically connected to the third control signal terminal Gn + 1.
Illustratively, in conjunction with fig. 3 and 4, the first reset unit 50 includes a fifth switching transistor K5, wherein the third control signal terminal Gn +1 outputs a third control signal (i.e., a high-level signal) during a period T3, the fifth switching transistor K5 is turned on by the third control signal, and the second signal terminal XCK outputs a second signal to the first node N1 through the fifth switching transistor K5, so that the first node N1 is reset during a period T3.
The second reset unit 60 includes a sixth switching transistor K6, a first terminal of the sixth switching transistor K6 is electrically connected to the third signal terminal Vgl, a second terminal of the sixth switching transistor K6 is electrically connected to the control terminal of the third switching transistor K3, and a control terminal of the sixth switching transistor K6 is electrically connected to the fourth control signal terminal Gn + 2.
Illustratively, in conjunction with fig. 6 and 7, the second reset unit 60 includes a sixth switching transistor K6, during a period T2, the fourth control signal terminal Gn +2 outputs a fourth control signal (i.e., a high-level signal), the sixth switching transistor K6 is turned on by the fourth control signal, the third signal terminal Vgl outputs a third signal to the control terminal of the third switching transistor K3 through the sixth switching transistor K6, and it is ensured that during a period T2, the third switching transistor K3 and the fourth switching transistor K4 are in a turned-off state.
Optionally, the bootstrap unit 40 includes a capacitor C, a first end of the capacitor C is electrically connected to the second control signal terminal Gn and the control terminal of the second switch transistor K2, respectively, and a second end of the capacitor C is electrically connected to the first node N1.
Referring to fig. 1, the bootstrap unit 40 includes a capacitor C, and in a stage T2, when the second control signal terminal Gn outputs the second control signal, the second control signal charges the capacitor C, so that the potential of the first node N1 is raised after the capacitor C is charged.
Optionally, on the basis of the foregoing embodiments, fig. 8 is a schematic structural diagram of an optical sensor circuit provided in an embodiment of the present disclosure, and as shown in fig. 8, the optical sensor circuit includes a plurality of gate circuits 200 according to any one of the foregoing embodiments, and further includes: a photoelectric element array 100 including photoelectric sensing units 101 arranged in a plurality of rows; a plurality of Scan lines Scan, each Scan line Scan being connected to a corresponding row of the photoelectric sensing units 101; a plurality of bias voltage signal lines Pn, each gate circuit 200 being electrically connected to one of the bias voltage signal lines Pn, each bias voltage signal line Pn being connected to a corresponding one of the rows of the photoelectric sensing units 101; when one Scan line Scan is gated, the gate circuit 200 writes the Bias voltage signal of the Bias voltage signal terminal Bias into the Bias voltage signal line Pn corresponding to the Scan line through the first Bias voltage signal output terminal Bn.
Referring to fig. 8, the photo element array 100 includes photo sensing units 101 arranged in a plurality of rows. Optionally, the number of the photoelectric sensing units 101 in each row is multiple, that is, the photoelectric element array 100 includes the photoelectric sensing units 101 arranged in multiple rows and multiple columns, and the photoelectric sensing unit 101 in each column is correspondingly connected with a Data line Data in the same column, so as to collect the electrical signals generated by the photoelectric sensing units 101 in the corresponding column. By arranging the plurality of photoelectric sensing units 101, the number of electric signals collected by the optical sensor circuit can be increased, so that the accuracy of optical identification is improved. Wherein the row direction is a direction extending left and right as shown in the drawing, and the column direction is a direction extending up and down as shown in the drawing.
Each Scan line Scan of the plurality of Scan lines Scan is connected to the corresponding one of the photo sensing units 101, and when a Scan line Scan of a certain row is gated, the gated Scan line Scan transmits a Scan signal to the corresponding one of the photo sensing units 101, so as to turn on and off the photo sensing units 101 in the same row.
Each of the plurality of bias voltage signal lines Pn is connected to the photo-sensing unit 101 of a corresponding row. By arranging the bias voltage signal lines Pn and transmitting bias voltage signals in the bias voltage signal lines Pn, bias voltage signals can be input into each bias voltage signal line Pn and the photoelectric sensing units 101 in a corresponding row, so that the photoelectric elements 11 of the photoelectric sensing units 101 are located in a nearly linear region when working, and the accuracy and stability of the working of the photoelectric sensing units 101 when receiving illumination signals are improved.
The gate circuit 200 connects the plurality of Bias voltage signal lines Pn to the Bias voltage signal terminal Bias through the first Bias voltage signal output terminal Bn, and has a function of gating the Bias voltage signal lines Pn and the Bias voltage signal terminal Bias. Specifically, when the electrical signals collected by the photo sensor cells 101 in one row are collected, the gate circuit 200 may electrically connect the bias voltage signal line Pn in the same row as the photo sensor cells 101 to the first bias voltage signal output terminal Bn of the gate circuit, and disconnect the bias voltage signal line Pn of the photo sensor cells 101 in the other rows from the first bias voltage signal output terminal Bn. Further, when one scanning line is gated, the gating circuit 200 writes the Bias voltage signal of the Bias voltage signal end Bias into the Bias voltage signal line Pn corresponding to the scanning line Scan, so as to accurately acquire the electric signal transmitted in the photoelectric sensing units 101 in the row, and at this time, the Bias voltage signal lines Pn and the Bias voltage signal ends Bias in the other rows are in a disconnected state, thereby avoiding the influence of current generated by the photoelectric sensing units 101 in the other rows when being illuminated, effectively reducing noise in the acquired current signal, and improving the identification capability and accuracy of the sensor for low-brightness illumination.
It should be noted that, if the current gating circuit is used to output the Bias voltage signal to the Bias voltage signal line of the sensor unit in the nth row, at the stage T1, the Bias voltage signal of the Bias voltage signal terminal Bias is output to the second Bias voltage signal output terminal Bn-1, where the second Bias voltage signal output terminal Bn-1 corresponds to the input terminal of the Bias voltage signal line of the sensor unit in the nth row.
Optionally, on the basis of the above embodiment, fig. 9 is a schematic structural diagram of another optical sensor circuit provided in the embodiment of the present disclosure, and as shown in fig. 9, each gate circuit 200 is connected to one Scan line Scan in the same row and one bias voltage signal line Pn corresponding to the Scan line Scan in the same row respectively.
Each gate circuit 200 is electrically connected to one Scan line Scan in the same row and one bias voltage signal line Pn corresponding to one Scan line Scan in the same row, respectively. With the above arrangement, when a Scan signal is input to one of the Scan lines Scan, the Scan signal can make the corresponding gate circuit 200 and the Bias voltage signal line Pn conductive, so that when one Scan line Scan is gated, the gate circuit 200 makes the Bias voltage signal line Pn in the same row as the Scan line Scan and the Bias voltage signal terminal Bias conductive, so that the Bias voltage signal line Pn and the Scan line Scan are synchronously conducted row by row.
It is noted that, in this document, relational terms such as "first" and "second," and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
The previous description is only for the purpose of describing particular embodiments of the present disclosure, so as to enable those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A gating circuit, comprising: the device comprises a gating unit, an initialization unit, a compensation unit and a bootstrap unit, wherein the gating unit comprises a first switching transistor and a second switching transistor;
the first end of the first switching transistor is electrically connected with a bias voltage signal end, the second end of the first switching transistor is electrically connected with the first end of the second transistor, the control end of the first switching transistor is electrically connected with a first node, and the second end of the second switching transistor is electrically connected with a first bias voltage signal output end;
a first end of the initialization unit is electrically connected with a first signal end, a second end of the initialization unit is electrically connected with the first node, a control end of the initialization unit is electrically connected with a first control signal end, and the initialization unit is used for initializing the potential of the first node when the first control signal end outputs a first control signal;
a first end of the compensation unit is electrically connected with a second end of the first switching transistor, a second end of the compensation unit is electrically connected with a second bias voltage signal output end, a control end of the compensation unit is electrically connected with a control end of the initialization unit, and the compensation unit is used for outputting a bias voltage signal to the second bias voltage signal output end when the first control signal end outputs a first control signal;
A first end of the bootstrap unit is electrically connected to a second control signal end and a control end of the second switching transistor, respectively, a second end of the bootstrap unit is electrically connected to the first node, and the bootstrap unit is configured to pull up an electric potential of the control end of the first switching transistor when the second control signal end outputs a second control signal;
the time sequence of the first control signal output by the first control signal end is positioned before the time sequence of the second control signal output by the second control signal end.
2. The gating circuit of claim 1, further comprising a first reset unit;
the first end of the first resetting unit is electrically connected with the second signal end, the second end of the first resetting unit is electrically connected with the first node, the control end of the first resetting unit is electrically connected with the third control signal end, and the first resetting unit is used for resetting the potential of the first node when the third control signal end outputs a third control signal;
and the time sequence of the third control signal end outputting the third control signal is positioned behind the time sequence of the second control signal end outputting the second control signal.
3. The gating circuit of claim 2, further comprising a second reset unit;
the first end of the second resetting unit is electrically connected with the third signal end, the second end of the second resetting unit is electrically connected with the control end of the initialization unit, the control end of the second resetting unit is electrically connected with the fourth control signal end, and the second resetting unit is used for enabling the initialization unit and the compensation unit to be in a cut-off state when the fourth control signal end outputs a fourth control signal;
the time sequence of the fourth control signal output by the fourth control signal end is the same as the time sequence of the second control signal output by the second control signal end.
4. The gate circuit of claim 3, wherein the second control signal terminal is electrically connected to the fourth control signal terminal.
5. The gate circuit according to claim 4, wherein the initialization unit comprises a third switching transistor, a first terminal of the third switching transistor is electrically connected to a first signal terminal, a second terminal of the third switching transistor is electrically connected to the first node, and a control terminal of the third switching transistor is electrically connected to the first control signal terminal.
6. The gate circuit of claim 5, wherein the compensation unit comprises a fourth switching transistor, a first terminal of the fourth switching transistor is electrically connected to the second terminal of the first switching transistor, a second terminal of the fourth switching transistor is electrically connected to the second bias voltage signal output terminal, and a control terminal of the fourth switching transistor is electrically connected to the control terminal of the third switching transistor.
7. The gate circuit according to claim 6, wherein the first reset unit comprises a fifth switching transistor, a first terminal of the fifth switching transistor is electrically connected to a second signal terminal, a second terminal of the fifth switching transistor is electrically connected to the first node, and a control terminal of the fifth switching transistor is electrically connected to the third control signal terminal;
the second reset unit comprises a sixth switching transistor, the first end of the sixth switching transistor is electrically connected with the third signal end, the second end of the sixth switching transistor is electrically connected with the control end of the third switching transistor, and the control end of the sixth switching transistor is electrically connected with the fourth control signal end.
8. The gate circuit according to claim 1, wherein the bootstrap unit includes a capacitor, a first end of the capacitor is electrically connected to the second control signal terminal and the control terminal of the second switching transistor, respectively, and a second end of the capacitor is electrically connected to the first node.
9. An optical sensor circuit comprising a plurality of gating circuits according to any one of claims 1 to 8, further comprising:
the photoelectric element array comprises photoelectric sensing units arranged in a plurality of rows;
each scanning line is connected with the photoelectric sensing units in a corresponding row;
each gating circuit is electrically connected with one bias voltage signal line, and each bias voltage signal line is connected with the photoelectric sensing unit in a corresponding row;
when one scanning line is gated, the gating circuit writes a bias voltage signal at a bias voltage signal end into a bias voltage signal line corresponding to the scanning line through the first bias voltage signal output end.
10. The circuit according to claim 9, wherein each gate circuit is connected to one of the scan lines in the same row and one of the bias voltage signal lines corresponding to the one of the scan lines in the same row, respectively.
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| CN202110640262.4A CN113505645B (en) | 2021-06-09 | 2021-06-09 | Gating circuit and optical sensor circuit |
| PCT/CN2021/116260 WO2022257284A1 (en) | 2021-06-09 | 2021-09-02 | Gate circuit and optical sensor circuit |
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| CN202110640262.4A CN113505645B (en) | 2021-06-09 | 2021-06-09 | Gating circuit and optical sensor circuit |
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