CN111428697B - Optical sensor circuit, detector, imaging system, sensor, and display panel - Google Patents
Optical sensor circuit, detector, imaging system, sensor, and display panel Download PDFInfo
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- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/13—Sensors therefor
- G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
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Abstract
The application provides an optical sensor circuit, a detector, a camera system, a sensor and a display panel, wherein the optical sensor circuit comprises a photoelectric element array and photoelectric sensing units which are arranged in multiple rows; the scanning lines are connected with the photoelectric sensing units in a corresponding row; the scanning circuit is connected with the plurality of scanning lines and is used for gating the plurality of scanning lines in a time-sharing manner; a plurality of bias voltage lines, each of which is connected to the photoelectric sensing units of a corresponding row; and a gate circuit connecting the plurality of bias voltage lines with the bias voltage signal terminal, the gate circuit being configured to turn on the bias voltage lines in the same row with the bias voltage signal terminal when the scan circuit gates one scan line. By the aid of the technical scheme, noise in the collected current signals can be reduced, and the recognition capability of the sensor for low-brightness illumination is improved.
Description
Technical Field
The application belongs to the technical field of optical identification, and particularly relates to an optical sensor circuit, a flat panel detector, a camera system, an optical fingerprint sensor and a display panel.
Background
With the rapid development of optical identification technology, the optical identification technology can be applied to the field of optical fingerprint identification or the digital X-ray in the optical identification technology can be applied to the field of medical equipment, and the main principle is to form an identification image through the optical identification technology for fingerprint identification or medical diagnosis.
When an optical sensor circuit in an existing optical recognition device collects an image, a plurality of rows of optical elements are arranged in the optical sensor circuit and used for sensing illumination, and when the current of one row of photoelectric elements is collected under a small illumination condition, the rest rows of photoelectric elements generate signal interference when being illuminated, so that a large amount of noise exists in a finally collected current signal, and the recognition capability of the sensor on low-brightness illumination is low.
Disclosure of Invention
The embodiment of the application provides an optical sensor circuit, flat panel detector, camera system, optical fingerprint sensor and display panel, can reduce the noise in the current signal of gathering, improves the sensor to low-luminance irradiant discernment ability.
In a first aspect, an embodiment of the present invention provides an optical sensor circuit, including: the photoelectric element array comprises photoelectric sensing units arranged in a plurality of rows; the scanning lines are connected with the photoelectric sensing units in a corresponding row; the scanning circuit is connected with the plurality of scanning lines and is used for gating the plurality of scanning lines in a time-sharing manner; a plurality of bias voltage lines, each bias voltage line being connected to a corresponding row of the photo-sensing units; and a gate circuit connecting the plurality of bias voltage lines with the bias voltage signal terminal, the gate circuit being configured to turn on the bias voltage lines in the same row with the bias voltage signal terminal when the scan circuit gates one scan line.
In a second aspect, an embodiment of the present invention provides a flat panel detector, including the optical sensor circuit of any one of the above embodiments.
In a third aspect, an embodiment of the present invention provides an imaging system, which includes the optical sensor circuit of any one of the foregoing embodiments or the foregoing flat panel detector.
In a fourth aspect, an embodiment of the present invention provides an optical fingerprint sensor, including the optical sensor circuit of any one of the above embodiments.
In a fifth aspect, an embodiment of the present invention provides a display panel, which includes the optical fingerprint sensor or the optical fingerprint sensor.
According to the optical sensor circuit, the flat panel detector, the camera system, the optical fingerprint sensor and the display panel, the optical sensor circuit comprises the photoelectric element array, the plurality of scanning lines, the scanning circuit, the plurality of bias voltage lines and the gating circuit, the scanning lines are gated in a time-sharing mode through the scanning circuit, scanning signals are transmitted to the photoelectric sensing units corresponding to one line in a time-sharing mode through the scanning lines, the plurality of scanning lines are conducted line by line, and current generated when the photoelectric sensing units are irradiated by light can be collected line by line conveniently.
When the current generated by one row of the photoelectric sensing units under the condition of weak illumination is collected, the current value at the moment is smaller, and the photoelectric sensing units of other rows generate parallel current signals under the condition of illumination when receiving bias voltage signals, so that the current signals generated in the detected photoelectric sensing units are interfered.
Drawings
The present application will be better understood from the following description of specific embodiments of the invention taken in conjunction with the accompanying drawings. Wherein like or similar reference numerals refer to like or similar features.
FIG. 1 is a schematic diagram of an optical sensor circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an optical sensor circuit according to another embodiment of the present invention;
FIG. 3 is a schematic diagram of an optical sensor circuit according to yet another embodiment of the present invention;
FIG. 4 is a schematic diagram of an optical sensor circuit according to another embodiment of the present invention;
FIG. 5 is a schematic diagram of an optical sensor circuit according to yet another embodiment of the present invention;
FIG. 6 is a schematic diagram of a gating cell according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating a structure of a gating cell according to another embodiment of the present invention;
FIG. 8 is a timing diagram of the gating cell shown in FIG. 7;
FIG. 9 is a schematic diagram of a gating cell according to still another embodiment of the present invention;
fig. 10 is a schematic structural diagram of a gating cell according to still another embodiment of the present invention.
Detailed Description
Features of various aspects and exemplary embodiments of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising 8230; \8230;" comprises 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
Features of various aspects and exemplary embodiments of the present invention will be described in detail below. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In some optical sensor circuits, a plurality of rows and columns of photoelectric sensing units are generally included, and the photoelectric sensing units are configured to convert collected optical signals into electrical signals to be received by data lines connected to the photoelectric sensing units, so that the optical sensor generates corresponding images according to the received electrical signals. Generally, the control ends of multiple rows of photoelectric sensing units are scanned and conducted line by line through scanning lines, and one ends of the multiple rows of photoelectric sensing units all supply bias voltage signals, when an optical sensor collects an electric signal of a first photoelectric sensing unit connected with one of the scanning lines, the first photoelectric sensing unit does not have illumination or has low illumination brightness, the current collected by the optical sensor is small, the photoelectric sensing units of the rest rows all receive the bias voltage signals, and if the photoelectric sensing units of the rest rows are illuminated, a part of parallel current signals can be generated.
In order to solve the above problem, embodiments of the present invention provide an optical sensor circuit. Referring to fig. 1, fig. 1 is a schematic structural diagram of an optical sensor circuit according to an embodiment of the present invention. The optical sensor circuit may include a photo cell array 100, a plurality of Scan lines Scan, a Scan circuit, a plurality of bias voltage lines Bn, and a gating circuit 20.
The photo cell array 100 includes photo sensor units 10 arranged in a plurality of rows. Optionally, the number of the photoelectric sensing units 10 in each row is multiple, that is, the photoelectric element array 100 includes the photoelectric sensing units 10 arranged in multiple rows and multiple columns, and the photoelectric sensing unit 10 in each column is correspondingly connected with a Data line Data in the same column, so as to collect the electrical signal generated by the photoelectric sensing unit 10 in the corresponding column. By arranging the plurality of photoelectric sensing units 10, the number of electric signals collected by the optical sensor circuit can be increased, so that the accuracy of optical identification is improved. Wherein the row direction is a direction extending to the left and right as shown in the drawing, and the column direction is a direction extending up and down as shown in the drawing.
The scanning circuit comprises a clock signal line and a plurality of scanning line signal ends corresponding to the plurality of scanning lines Scan, and the plurality of scanning line signal ends are controlled by the clock signal line to transmit scanning signals to the corresponding plurality of scanning lines Scan so as to realize the progressive scanning of the plurality of scanning lines Scan. As shown in fig. 1, the scanning line signal terminal G2, and the scanning line signal terminal G3 are shown in the drawing, it can be understood that the number of the scanning signal terminals can be set according to the requirement of the user, for example, the number of the scanning line signal terminals can be multiple, and the number of the scanning line signal terminals can include the scanning line signal terminals G3, \8230, the scanning line signal terminals Gn-1, the scanning line signal terminals Gn, and the scanning line signal terminals Gn +1.
Each scanning line Scan of the plurality of scanning lines Scan is connected to the corresponding row of the photoelectric sensing units 10, and one scanning line signal terminal of the scanning circuit is connected to one scanning line Scan of the plurality of scanning lines Scan for time-sharing gating the plurality of scanning lines Scan. By arranging the scanning circuit and the scanning lines Scan connected with the scanning circuit, the scanning circuit can gate a plurality of scanning lines Scan in a time-sharing manner, and the scanning signals are transmitted to the photoelectric sensing units 10 corresponding to one row through the scanning lines Scan, so that the photoelectric sensing units 10 in the same row are turned on and off.
Each of the plurality of bias voltage lines Bn is connected to the photo-sensing units 10 of a corresponding row. By setting the bias voltage lines Bn and transmitting the bias voltage signals in the bias voltage lines Bn, the bias voltage signals can be input to each of the bias voltage lines Bn and the corresponding row of the photo-sensing units 10, so that the photo-sensing units 11 of the photo-sensing units 10 are located in a nearly linear region when operating, and the accuracy and stability of the operation of the photo-sensing units 10 when receiving the illumination signals are improved.
The gate circuit 20 connects the plurality of Bias voltage lines Bn to the Bias voltage signal terminal Bias, and has a function of gating the Bias voltage lines Bn and the Bias voltage signal terminal Bias. Specifically, when acquiring the electrical signal acquired by the photo sensing units 10 in one row, the gate circuit 20 may connect the Bias voltage line Bn of the same row as the photo sensing units 10 to the Bias voltage signal terminal Bias, and disconnect the Bias voltage lines Bn of the photo sensing units 10 in the other rows from the Bias voltage signal terminal Bias. Further, the gate circuit 20 is configured to turn on the Bias voltage line Bn of the same row with the Bias voltage signal terminal Bias when the Scan circuit gates one Scan line Scan. By arranging the gating circuit 20, when the scanning circuit gates one scanning line Scan, the gating circuit 20 connects the Bias voltage line Bn of the same row with the Bias voltage signal end Bias, so that the electrical signals transmitted in the photoelectric sensing units 10 of the row can be accurately collected, and at this time, the Bias voltage lines Bn of the other rows and the Bias voltage signal ends Bias are in a disconnected state, thereby avoiding the influence of current generated by the photoelectric sensing units 10 of the other rows when being illuminated, effectively reducing noise in the collected current signals, and improving the identification capability and accuracy of the sensor for low-brightness illumination.
Referring further to fig. 1, in order to implement the gating function of the gating circuit 20, in some embodiments, the gating circuit 20 includes a plurality of gating units 21, and each gating unit 21 is respectively connected to one Scan line Scan in the same row and one bias voltage line Bn corresponding to the one Scan line Scan in the same row. With the above arrangement, when the scanning circuit inputs a scanning signal to one of the scanning lines Scan, the scanning signal can turn on the corresponding gate unit 21 and the Bias voltage line Bn, so that when the scanning circuit gates one of the scanning lines Scan, the gate unit 21 turns on the Bias voltage line Bn in the same row as the scanning line Scan and the Bias voltage signal terminal Bias, so that the Bias voltage line Bn and the scanning line Scan are turned on line by line in synchronization.
It should be noted that, herein, one Scan line Scan, one bias voltage line Bn and one gating unit 21 are respectively connected to the photo-sensing units 10 in a corresponding row, and at this time, the Scan line Scan, the bias voltage line Bn and the gating unit 21 connected to the photo-sensing units 10 in the same row are in the same row relationship, that is, each row of the photo-sensing units 10 corresponds to one gating unit 21 in the same row, one Scan line Scan in the same row and one bias voltage line Bn in the same row.
In some embodiments, the gating circuit 20 is located at one side or both sides of the array of photoelectric elements 100 in the row direction of the photoelectric sensing units 10. Referring to fig. 2, fig. 2 is a schematic structural diagram of an optical sensor circuit according to another embodiment of the present invention, in order to improve the gating efficiency of the gating circuit 20, the gating circuit 20 may be disposed on the two sides of the photo element array 100 along the photo sensing unit 10. Of course, as shown in fig. 1, the gate circuit 20 may be disposed on one side of the row direction of the photo sensing units 10, as long as the bias voltage line Bn can be turned on line by line in synchronization with the Scan line Scan.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an optical sensor circuit according to still another embodiment of the invention. In order to implement the gating function of the gating unit 21, in some embodiments, the gating unit 21 includes a first switching transistor T1, a control terminal of the first switching transistor T1 is connected to the Scan line Scan in the same row, a first terminal of the first switching transistor T1 is connected to the Bias voltage signal terminal Bias, and a second terminal of the first switching transistor is connected to the Bias voltage line Bn in the same row. With the above arrangement, when the Scan line Scan is gated, the Scan signal is transmitted to the control terminal of the first switching transistor T1, and the first switching transistor T1 is turned on, so that the first terminal of the first switching transistor T1 transmits the bias voltage signal to the second terminal, so that the bias voltage signal is transmitted in the bias voltage line Bn.
Specifically, in fig. 3, one Scan line Scan and one first switching transistor T1 are arranged in the row direction, and are respectively used for controlling the transmission of the electrical signals of the photo-sensing units 10 in the same row, and each first switching transistor T1 is in the same row relationship with a corresponding one Scan line Scan and one bias voltage line Bn. At this time, the control terminal of the first switching transistor T1 positioned in the first row in fig. 3 is connected to the Scan line Scan connected to the Scan signal terminal G1, and the second terminal of the first switching transistor T1 is connected to the bias voltage line Bn of the first row; a control terminal of the first switching transistor T1 positioned in the second row in fig. 3 is connected to the Scan line Scan connected to the Scan signal terminal G2, and a second terminal of the first switching transistor T1 is connected to the bias voltage line Bn of the second row; the control terminal of the first switching transistor T1 positioned in the third row in fig. 3 is connected to the Scan line Scan to which the Scan signal terminal G3 is connected, and the second terminal of the first switching transistor T1 is connected to the bias voltage line Bn of the third row. The first terminals of the three first switching transistors T1 are all connected to the Bias voltage signal terminal Bias.
Referring to fig. 4, fig. 4 is a schematic structural diagram of an optical sensor circuit according to yet another embodiment of the present invention. When the gating circuit 20 is located on the photo sensor array 100 along both sides of the photo sensor unit 10, the first switching transistors T1 may be respectively disposed on the photo sensor array 100 along both sides of the photo sensor unit 10, two first switching transistors T1 located in the same row are respectively connected to the same Scan line Scan and the same Bias voltage line Bn, and meanwhile, the Bias voltage signal terminals Bias may be respectively disposed along both sides of the photo sensor unit 10 to supply the Bias voltage signals to the first switching transistors T1 on both sides.
Referring to fig. 5 and fig. 6 together, fig. 5 is a schematic structural diagram of an optical sensor circuit according to still another embodiment of the present invention, and fig. 6 is a schematic structural diagram of a gating unit according to an embodiment of the present invention. When the turn-on voltage VGH in the Scan signal transmitted in the Scan line Scan is not enough to fully turn on the first switching transistor T1 in the gate unit 21, the first switching transistor T1 at this time may be in a half-on state, affecting the transmission of the bias voltage signal in the gate unit 21. In order to solve the above problem, in some embodiments, the gating unit 21 includes a second switching transistor T2 and a bootstrap circuit 210. A first terminal of the second switching transistor T2 is connected to the Bias voltage signal terminal Bias, and a second terminal of the second switching transistor T2 is connected to the Bias voltage line Bn in the same row. The bootstrap circuit 210 is connected to the control terminal of the second switch transistor T2 and the Scan line Scan in the same row, and is used for pulling up the potential of the control terminal of the second switch transistor T2. With the above arrangement, the bootstrap circuit 210 is used to pull up the potential of the control terminal of the second switching transistor T2, so that the second switching transistor T2 can be completely turned on, and a stable bias voltage signal is transmitted in the bias voltage line Bn.
In specific implementation, when a Scan signal is input into the Scan line Scan in the same row as the gate unit 21, the turn-on voltage VGH in the Scan signal acts on the control end of the second switch transistor T2 and the bootstrap circuit 210, and the bootstrap circuit 210 is acted by the turn-on voltage VGH to pull up the potential of the control end of the second switch transistor T2, so that the second switch transistor T2 can be completely turned on, which is favorable for transmission of a bias voltage signal.
In order to implement the bootstrap function of the bootstrap circuit 210, in some embodiments, the bootstrap circuit 210 includes a bootstrap capacitor C and a third switching transistor T3. One end of the bootstrap capacitor C is connected to the Scan line Scan in the same row, the other end of the bootstrap capacitor C is connected to the first node P1, and the first node P1 is connected to the control end of the second switch transistor T2. A control terminal of the third switching transistor T3 is connected to the first signal terminal S1, a first terminal of the third switching transistor T3 is connected to the Bias voltage signal terminal Bias, and a second terminal of the third switching transistor T3 is connected to the first node P1.
To explain the principle of the embodiment of the present invention, the Data line Data is used to collect the current signal in the photoelectric sensing unit 10 in the 2 nd row connected to the scanning signal terminal G2, and the control terminals of the third switching transistor T3 and the second switching transistor T2 can be turned on by inputting the high-level signal. Specifically, referring to fig. 5 and 6, when a current signal in the photoelectric sensing unit 10 in the row 2 needs to be collected, a high level signal may be transmitted to the control terminal of the third switching transistor T3 through the first signal terminal S1, so that the third switching transistor T3 is in a conducting state, because the first terminal of the third switching transistor T3 is connected to the Bias voltage signal terminal Bias, when the third switching transistor T3 is conducting, the first terminal of the third switching transistor T3 is enabled to transmit a Bias voltage signal to the second terminal, and because the second terminal of the third switching transistor T3 is connected to the first node P1 and the other terminal of the bootstrap capacitor C, the Bias voltage signal transmitted by the third switching transistor T3 may charge the bootstrap capacitor C. Then, when a Scan signal is transmitted in the Scan line Scan of the same row (row 2), that is, the Scan signal terminal G2 transmits a high level, the bootstrap capacitor C discharges, so that the first node P1 is bootstrapped, at this time, the voltage at the first node P1 includes the discharge voltage of the bootstrap capacitor C and the turn-on voltage VGH in the Scan line Scan, and the voltage of the first node P1 is the same as that of the second switching transistor T2, which effectively increases the voltage of the control terminal of the second switching transistor T2, so that the second switching transistor T2 is fully turned on, so that the Bias voltage signal transmitted by the Bias voltage signal terminal Bias can be stably transmitted from the first terminal of the second switching transistor T2 to the second terminal of the second switching transistor T2, and further transmitted to the Bias voltage signal line Bn to be supplied to the corresponding photo-sensing unit 10 in the same row.
Since the photo sensor circuit includes the photo sensing units 10 arranged in a plurality of rows and a plurality of Scan lines Scan, which are turned on by scanning line by line, in order to properly arrange the wirings in the photo sensor circuit and reduce the number of wirings in the photo sensor circuit, in some embodiments, the first signal terminal S1 is connected to the Scan line Scan in the previous row in the scanning order. Through the arrangement, the bootstrap capacitor C can be charged reasonably by using the Scan line Scan of the previous row in the Scan order, and the bootstrap of the first node P1 is further realized.
Referring to fig. 6 and 7, fig. 7 is a schematic structural diagram of a gating unit according to another embodiment of the present invention. In order to improve the control accuracy of the gating unit 21, in some embodiments, the gating unit 21 further includes an initialization module 212, and the initialization module 212 is connected to the first node P1 and is configured to initialize the potential of the first node P1. Through the above arrangement, the initialization module 212 clears the residual voltage of the first node P1, and the second switching transistor T2 is prevented from being turned on due to the residual voltage.
In some embodiments, the initialization module 212 includes a fourth switching transistor T4, a control terminal of the fourth switching transistor T4 is connected to the second signal terminal S2, a first terminal of the fourth switching transistor T4 is connected to the reset signal terminal VX or the Scan line Scan of the previous row in the Scan order, and a second terminal of the fourth switching transistor T4 is connected to the first node P1. When a high-level Scan signal is transmitted through the Scan line Scan of the current row, the Scan line Scan of the previous row in the scanning sequence is in a low-level state, and at this time, the first terminal of the fourth switching transistor T4 is connected to the reset signal terminal VX or the Scan line Scan of the previous row in the scanning sequence, and a voltage signal of a fixed potential or a low-level signal output by the Scan line Scan of the previous row is output through the reset signal terminal VX, so that the first node P1 and the second switching transistor T2 are initialized. Further, since the control terminal of the fourth switching transistor T4 is connected to the second signal terminal S2, the first node P1 may be initialized by the electrical signal transmitted in the second signal terminal S2.
In order to properly arrange the wirings in the photosensor circuit and reduce the number of wirings in the photosensor, in some embodiments, the second signal terminal S2 connects the Scan lines Scan of the next row in the Scan order. Through the arrangement, the fourth switching transistor T4 can be switched on by reasonably utilizing the electric signal output by the Scan line Scan in the next row in the scanning sequence, so that the first node P1 is initialized.
The operation of the circuit according to an embodiment of the present invention will be described with reference to fig. 8, in which the operation of the circuits shown in fig. 6 and 7 is similar, and fig. 8 is a timing diagram of the gating unit shown in fig. 7. As shown in fig. 7 and 8, taking the example of collecting the current in the photoelectric sensing units in the same row as the scanning signal terminal Gn, the scanning signal terminal connected to the scanning line Scan in the previous row in the scanning order is Gn-1, and the scanning signal terminal connected to the scanning line Scan in the next row in the scanning order is Gn +1.
In the progressive scanning process of the Scan lines Scan, at time N1, the Scan line Scan in the previous row in the scanning sequence connected to the Scan signal terminal Gn-1 is turned on, at this time, the Scan signal terminal Gn-1 outputs a high level, the Scan signal terminal Gn +1, and the Bias voltage signal terminal Bias output a low level, and the high level signal turns on the third switching transistor T3, so that the voltage signal output from the Bias voltage signal terminal Bias is transmitted to the first node P1, so that the bootstrap capacitor C connected to the first node P1 is charged, and the potential of the first node P1 is raised.
At the moment of N2, the Scan line Scan connected to the Scan signal terminal Gn is turned on, at this moment, the Scan signal terminal Gn outputs a high level, the Scan signal terminal Gn-1 and the Scan signal terminal Gn +1 output a low level, at this moment, the third switching transistor T3 is turned off, the bootstrap capacitor C discharges, at this moment, the potential of the first node P1 is the superposition of the potential signal output by the Scan signal terminal Gn and the potential signal discharged by the bootstrap capacitor C, so that the potential bootstrap of the first node P1 is realized, the potential of the first node P1 is effectively increased, the complete turn-on of the second switching transistor T2 is realized, and at this moment, the Bias voltage signal terminal Bias transmits a high-level signal to the Bias voltage signal line Bn. By providing the bootstrap circuit 210, the situation that the gate unit 21 is turned on when the turn-on voltage VGH in the Scan signal transmitted in the Scan line Scan is not enough to be turned on completely is improved.
At time N3, the Scan line Scan in the next row in the Scan sequence connected to the Scan signal terminal Gn +1 is turned on, at this time, the Scan signal terminal Gn +1 outputs a high level, the Scan signal terminal Gn-1, and the Bias voltage signal terminal Bias output a low level, and the high level signal turns on the fourth switching transistor T4, so that the fixed potential signal output by the reset signal terminal VX or the low level signal output by the Scan line Scan in the previous row is transmitted to the first node P1 to initialize the potential of the first node P1, and further initialize the potential of the control terminal of the second switching transistor T2. By providing the above-mentioned 3T1C circuit, the gating function of the gating unit 21 can be better realized, and the "3T1C circuit" refers to a circuit including 3 thin film transistors (T) and 1 capacitor (C) in the gating unit 21, and the rest of the "4T1C circuit" and the like are analogized in turn.
When the current generated in the n-th row of the photo-sensing units needs to be collected, a high-level signal needs to be input into the bias voltage signal line Bn in the same row, in order to reset the bias voltage signal line Bn in the same row to a low-level signal in other time, and prevent interference from being generated when the photo-sensing units 10 in other rows collect signals, please refer to fig. 9 and 10, fig. 9 is a schematic structural diagram of a gate unit provided in yet another embodiment of the present invention, and fig. 10 is a schematic structural diagram of a gate unit provided in yet another embodiment of the present invention, if the turn-off voltage VGL provided in the Scan line Scan can meet the turn-off requirement of the second switch transistor T2, in some embodiments, the initialization module 212 further includes a fifth switch transistor T5, a control end of the fifth switch transistor T5 is connected to the second signal end S2, a first end of the fifth switch transistor T5 is connected to the reset signal end VX or the Scan line in the previous row in the scanning sequence, and a second end of the fifth switch transistor T5 is connected to the bias voltage line Bn in the same row. With the 4T1C circuit set as described above, not only the potential of the first node P1 but also the potential of the bias voltage signal line Bn is initialized.
In order to properly arrange the wiring in the photosensor circuit and reduce the number of wirings in the photosensor, in some embodiments, the second signal terminal S2 may connect the Scan lines Scan of the next row in the Scan order. Through the arrangement, the electric signal output by the Scan line Scan in the next row in the Scan sequence can be reasonably utilized to turn on the fourth switching transistor T4 and the fifth switching transistor T5, so that the potential of the first node P1 is initialized, and the potential of the bias voltage signal line Bn is initialized.
Specifically, in fig. 9, the first terminal of the fourth switching transistor T4 and the first terminal of the fifth switching transistor T5 are connected to a reset signal terminal VX, the reset signal terminal VX can output a fixed potential, for example, a voltage signal of a negative potential, when a high level signal is input to the Scan line Scan in the next row in the scanning sequence, and the fourth switching transistor T4 and the fifth switching transistor T5 are turned on, the fixed potential output by the reset signal terminal VX is transmitted to the first node P1 through the fourth switching transistor T4 and transmitted to the second node P2 through the fifth switching transistor T5, so as to initialize the first node P1 and the second node P2, respectively, and further initialize the control terminal potential of the second switching transistor T2 and the potential in the bias voltage signal line Bn.
In a specific implementation, for example, in fig. 10, the first terminal of the fourth switching transistor T4 and the first terminal of the fifth switching transistor T5 are connected to a Scan line Scan in a previous row in the scanning sequence, during a period that the initialization is required, the Scan signal terminal Gn +1 outputs a high level, the Scan signal terminal Gn-1 outputs a low level of a fixed potential, at this time, the high level output by the Scan signal terminal Gn +1 turns on the fourth switching transistor T4 and the fifth switching transistor T5, the fixed potential output by the Scan signal terminal Gn-1 is respectively transmitted to the first node P1 through the fourth switching transistor T4, and transmitted to the second node P2 through the fifth switching transistor T5, so as to respectively initialize the first node P1 and the second node P2, and further initialize the control terminal potential of the second switching transistor T2 and the potential in the bias voltage signal line Bn.
Referring to fig. 1 to 5, since the photo-sensing unit 10 needs to sense light to generate current, a specific structure of the photo-sensing unit 10 will be described. In some embodiments, the photo sensing unit 10 includes a photo element 11 and a sixth switching transistor T6, the photo element 11 is configured to collect an optical signal and convert the optical signal into an electrical signal, and one end of the photo element 11 is connected to the bias voltage signal line Bn in the same row. A control end of the sixth switching transistor T6 is connected to the Scan line Scan in the same row, a first end of the sixth switching transistor T6 is connected to the other end of the photoelectric element 11, and a second end of the sixth switching transistor T6 is connected to the Data line Data.
In this embodiment, the photoelectric element 11 has a unidirectional conductive characteristic, and the photoelectric element 11 can convert the collected optical signal into an electrical signal, that is: when light is irradiated, the photoelectric element 11 generates hole-electron pairs, and under the action of an external bias voltage electric field, the electron-hole pairs move in opposite directions to form a current, and the current forms a stored charge in a storage capacitor carried by the photoelectric element 11. When the sixth switching transistor T6 is turned on by a scanning signal written on the scanning line Scan, a bias voltage signal is input to one end of the photoelectric element 11, so that the photoelectric element 11 can transmit an electrical signal to the Data line Data, which is convenient for collecting the electrical signal generated by the photoelectric element 11 when being illuminated.
In some alternative embodiments, the photocell 11 may be a PIN photodiode. The PIN type photodiode has the advantages of small junction capacitance, short transit time, high sensitivity and the like, is low in noise, is beneficial to reducing the noise in the acquired current signal, and improves the identification capability of the sensor on low-brightness illumination.
Each Transistor in the above embodiments may be specifically a Thin Film Transistor (TFT). The control end of the transistor is a grid electrode, the first end of the transistor is a source electrode, and the second end of the transistor is a drain electrode. Alternatively, the control terminal of the transistor is a gate, the first terminal of the transistor is a drain, and the second terminal of the transistor is a source, which is not limited herein. In the above embodiments, the control terminal of the transistor is taken as the gate, the first terminal of the transistor is taken as the source, and the second terminal of the transistor is taken as the drain for example. Further, each transistor in the above embodiments may be a P-type transistor or an N-type transistor, and the description herein takes the case where each transistor is an N-type transistor as an example.
To sum up, the optical sensor circuit provided in the embodiment of the present invention includes a photoelectric element array 100, a plurality of Scan lines Scan, a Scan circuit, a plurality of bias voltage lines Bn, and a gating circuit 20, where the Scan lines Scan are gated in a time-sharing manner by the Scan circuit, so that the Scan lines Scan transmit Scan signals to the photoelectric sensing units 10 in a corresponding row in a time-sharing manner, and the Scan lines Scan are conducted row by row, thereby facilitating to collect current generated when the photoelectric sensing units 10 are illuminated row by row.
When the current generated by the photoelectric sensing units 10 in one row is collected under the condition of weak illumination, the current value at this time is small, and the photoelectric sensing units 10 in other rows generate parallel current signals when being illuminated under the condition that the photoelectric sensing units receive the Bias voltage signal, so as to interfere with the detected current signal generated in the photoelectric sensing unit 10, therefore, in the embodiment of the present invention, by providing the gating circuit 20, the gating circuit 20 is configured to conduct the Bias voltage line Bn in the same row with the Bias voltage signal end Bias when the scanning circuit gates one Scan line Scan, so that the photoelectric sensing unit 10 conducted by the Scan line Scan corresponds to the photoelectric sensing unit 10 gated by the gating circuit 20, that is, the same row, at this time, the photoelectric sensing unit 10 in the row can generate the current when receiving the Bias voltage signal, and the photoelectric sensing units 10 in the other rows cannot transmit the current even if being illuminated but not receiving the Bias voltage signal, so as to reduce the noise in the collected current signal, and improve the capability of the sensor for identifying low-brightness illumination.
In another aspect, an embodiment of the present invention further provides a flat panel detector including the optical sensor circuit of any one of claims 1 to 12. The flat panel detector provided by the embodiment of the invention can improve signal interference generated by photoelectric sensing units in other rows, reduce noise in the acquired current signals and improve the recognition capability of the sensor on low-brightness illumination.
Specifically, the flat panel detector can convert an optical signal of the X-ray image into an electric signal when the X-ray image is received and acquire the electric signal by the flat panel detector, so that the flat panel detector obtains bone and soft tissue information through reverse image processing, and further obtains patient information.
An embodiment of the present application further provides an image capturing system, which may include the optical sensor circuit of any of the foregoing embodiments or the foregoing flat panel detector. The camera system can be a CCD camera system or a CMOS camera system. The camera system can be applied to medical examination, and the flat panel detector can transmit the detected electric signals to a corresponding terminal (such as a computer), and the terminal can convert the electric signals into image signals and display corresponding images so as to be watched.
An embodiment of the present invention further provides an optical fingerprint sensor, including the optical sensor circuit of any one of the above embodiments.
In particular, the optical fingerprint sensor operates on the principle that light rays emitted from a light source are reflected at the surface of the finger and received again by the optical fingerprint sensor. The optical fingerprint sensor can generate different identification information according to the difference of the valleys and ridges of the finger lines on light reflection, so that different finger line information can be identified. The optical fingerprint sensor provided by the embodiment of the invention can improve the signal interference generated by the photoelectric sensing units in the other rows, reduce the noise in the acquired current signal, improve the identification capability of the sensor on low-brightness illumination and improve the accuracy of user fingerprint identification.
In another aspect, an embodiment of the present invention further provides a display panel, including the optical sensor circuit in any of the above embodiments or the above optical fingerprint sensor.
By integrating the optical fingerprint sensor in the display panel, the light emitted from the display panel is reflected by the surface of the finger and enters the display panel again to be received by the fingerprint identification unit. The fingerprint identification unit can produce different identification information according to the grain of finger line and the difference of line ridge to light reflex to can discern different finger line information, through the aforesaid setting, can improve optical fingerprint sensor in the display panel to user's fingerprint identification accuracy, be convenient for popularize and apply.
It should be clear that the embodiments in this specification are described in a progressive manner, and the same or similar parts in the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. For the display panel embodiment and the display device embodiment, the related matters can be referred to the description parts of the pixel driving circuit embodiment and the array substrate embodiment. The present application is not limited to the particular structures described above and shown in the figures. Those skilled in the art may make various changes, modifications and additions after comprehending the spirit of the present application. Also, a detailed description of known techniques is omitted herein for the sake of brevity.
It will be appreciated by persons skilled in the art that the above embodiments are illustrative and not restrictive. Different features which are present in different embodiments may be combined to advantage. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art upon studying the drawings, the specification, and the claims. In the claims, the term "comprising" does not exclude other structures; the quantities relate to "a" and "an" but do not exclude a plurality; the terms "first", "second" are used to denote a name and not to denote any particular order. Any reference signs in the claims shall not be construed as limiting the scope. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Claims (13)
1. An optical sensor circuit, comprising:
the photoelectric element array comprises photoelectric sensing units arranged in a plurality of rows;
the scanning lines are connected with the photoelectric sensing units in a corresponding row;
the scanning circuit is connected with the plurality of scanning lines and is used for gating the plurality of scanning lines in a time-sharing manner;
a plurality of bias voltage lines, each of the bias voltage lines being connected to the photo-sensing units of a corresponding row; and
a gate circuit connecting the plurality of bias voltage lines with a bias voltage signal terminal, the gate circuit being configured to turn on the bias voltage lines in the same row with the bias voltage signal terminal when the scan circuit gates one of the scan lines; the gating circuit comprises a plurality of gating units, and each gating unit is respectively connected with one scanning line in the same row and one bias voltage line corresponding to one scanning line in the same row;
the gating unit includes:
a second switching transistor, a first end of the second switching transistor being connected to a bias voltage signal terminal, and a second end of the second switching transistor being connected to the bias voltage line in the same row;
and the bootstrap circuit is connected with the control end of the second switch transistor and the scanning line in the same row and is used for pulling up the electric potential of the control end of the second switch transistor.
2. The optical sensor circuit of claim 1, wherein the bootstrap circuit comprises:
one end of the bootstrap capacitor is connected with the scanning line in the same row, the other end of the bootstrap capacitor is connected with a first node, and the first node is connected with the control end of the second switch transistor;
and a control end of the third switching transistor is connected with a first signal end, a first end of the third switching transistor is connected with a bias voltage signal end, and a second end of the third switching transistor is connected with the first node.
3. The optical sensor circuit of claim 2, wherein the first signal terminal connects the scan lines of a previous row in a scan order.
4. The optical sensor circuit of claim 2, wherein the gating cell further comprises:
and the initialization module is connected with the first node and used for initializing the potential of the first node.
5. The optical sensor circuit of claim 4, wherein the initialization module comprises:
and the control end of the fourth switching transistor is connected with the second signal end, the first end of the fourth switching transistor is connected with the reset signal end or the scanning line in the previous row in the scanning sequence, and the second end of the fourth switching transistor is connected with the first node.
6. The optical sensor circuit of claim 5, wherein the initialization module further comprises:
a control terminal of the fifth switching transistor is connected to the second signal terminal, a first terminal of the fifth switching transistor is connected to a reset signal terminal or a scanning line in a previous row in a scanning sequence, and a second terminal of the fifth switching transistor is connected to the bias voltage line in the same row.
7. The optical sensor circuit according to claim 5 or 6, wherein the second signal terminal is connected to the scanning line of the next row in the scanning order.
8. The optical sensor circuit of claim 1, wherein the photo-sensing unit comprises:
the photoelectric element is used for collecting optical signals and converting the optical signals into electric signals, and one end of the photoelectric element is connected with the bias voltage signal line in the same row; and
and the control end of the sixth switching transistor is connected with the scanning line in the same row, the first end of the sixth switching transistor is connected with the other end of the photoelectric element, and the second end of the sixth switching transistor is connected with the data line.
9. The optical sensor circuit of claim 1, wherein the gating circuit is located at one or both sides of the array of photo elements along the row direction of the photo sensing units.
10. A flat panel detector comprising an optical sensor circuit according to any of claims 1 to 9.
11. A camera system, characterized in that it comprises an optical sensor circuit according to any one of claims 1 to 9 or a flat panel detector according to claim 10.
12. An optical fingerprint sensor comprising an optical sensor circuit according to any one of claims 1 to 9.
13. A display panel comprising the optical sensor circuit of any one of claims 1 to 9 or the optical fingerprint sensor of claim 12.
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| CN113505645B (en) * | 2021-06-09 | 2022-07-19 | 上海闻泰信息技术有限公司 | Gating circuit and optical sensor circuit |
| CN113920915B (en) * | 2021-10-19 | 2024-05-28 | 上海闻泰信息技术有限公司 | Light sensation driving circuit, driving method and display panel |
| CN114486954A (en) * | 2022-04-13 | 2022-05-13 | 江苏康众数字医疗科技股份有限公司 | Flat-panel optical sensor, flat-panel detector and imaging system |
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| CN110728265B (en) * | 2019-10-29 | 2022-05-31 | 厦门天马微电子有限公司 | Fingerprint identification display panel and fingerprint identification display device |
| CN110909661B (en) * | 2019-11-19 | 2023-01-13 | 厦门天马微电子有限公司 | Fingerprint identification display panel and fingerprint identification display device |
| CN110796124B (en) * | 2019-11-27 | 2022-07-01 | 厦门天马微电子有限公司 | Display panel driving method and display device |
| CN110933335B (en) * | 2020-01-21 | 2020-05-12 | 南京迪钛飞光电科技有限公司 | Drive circuit and time sequence drive method of flat panel detector |
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