CN113497604A

CN113497604A - Filter device and control method

Info

Publication number: CN113497604A
Application number: CN202110347826.5A
Authority: CN
Inventors: J·维特; D·斯特雷尤斯尼格
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2020-04-01
Filing date: 2021-03-31
Publication date: 2021-10-12
Also published as: US11115041B1; EP3890191A1

Abstract

Embodiments of the present disclosure relate to a filter apparatus and a control method. A system, comprising: an analog-to-digital converter configured to convert an analog signal generated by the digital sensor into a digital signal; and a test arrangement configured to be enabled after the analog to digital converter operates in a test mode, wherein the test arrangement comprises: a filter configured to receive the digital signal from the analog-to-digital converter and apply a filtering process to the digital signal; a control circuit configured to terminate the filtering process after an output of the control circuit reaches a predetermined reference value; and a result register configured to receive a result generated by the filter after the control circuit terminates the filtering process.

Description

Filter device and control method

Technical Field

The present invention relates generally to an apparatus for testing a digital micro-electro-mechanical system (MEMS) sensor, such as a digital MEMS microphone, that includes an analog-to-digital converter.

Background

A digital sensor (e.g., a digital MEMS microphone) is an acoustic sensor that converts a sound pressure signal into an analog signal. The digital MEMS microphone includes a MEMS sensor and an Application Specific Integrated Circuit (ASIC). The MEMS sensor and the ASIC are arranged in a single package. The MEMS sensor and ASIC are connected together by suitable electrical connections.

The MEMS sensor functions as a variable capacitor having a first plate and a second plate. One of the two plates is a movable plate. The movable plate is also referred to as a diaphragm. When the acoustic pressure signal is applied to the MEMS sensor, the diaphragm is able to move in response to the acoustic pressure signal. The deflection of the diaphragm relative to the other plate results in a change in the capacitance of the diaphragm. The change in capacitance is determined by various parameters of the acoustic pressure signal, such as the sound pressure level. The change in capacitance of the MEMS sensor in turn results in a voltage change that is fed as an analog signal to the ASIC for further processing.

The ASIC may include analog-to-digital converter (ADC) circuitry for converting analog signals generated by the MEMS sensor to suitable digital signals for use in various systems and applications, such as mobile phones, laptops, other digital mobile devices, and the like. The digital signal may be generated based on Pulse Density Modulation (PDM), which produces a highly oversampled unit data stream. PDM uses constant pulse width and encodes the signal in the time between pulses. In other words, under PDM, the density of pulses on the output of a digital MEMS microphone is proportional to the sound pressure level applied to the digital microphone.

The sensitivity of a digital MEMS microphone is defined as the electrical response at the output of the digital microphone in response to a given input sound pressure signal. In other words, the sensitivity is the ratio of the analog output voltage or the digital output value to the input sound pressure. The sensitivity specifications of digital microphones may vary greatly depending on different applications and design requirements. Therefore, it is desirable to perform sensitivity measurements under predetermined acoustic conditions, especially for advanced digital MEMS microphones where high sensitivity is a key parameter.

Disclosure of Invention

According to one embodiment, a system comprises: an analog-to-digital converter configured to convert an analog signal generated by the digital sensor into a digital signal; and a test arrangement configured to be enabled after the analog to digital converter operates in a test mode, wherein the test arrangement comprises: a filter configured to receive the digital signal from the analog-to-digital converter and apply a filtering process to the digital signal; a control circuit configured to terminate the filtering process after an output of the control circuit reaches a predetermined reference value; and a result register configured to receive a result generated by the filter after the control circuit terminates the filtering process.

According to another embodiment, a method comprises: configuring the analog-to-digital converter to operate in a test mode; configuring a filter to receive a bit stream generated by an analog-to-digital converter and accumulate values of the bit stream until the number of clock cycles reaches a predetermined reference value; and transmitting the output signal of the filter to the result register.

According to yet another embodiment, a system comprises: a delta-sigma analog-to-digital converter having an input coupled to the digital sensor; a digital logic circuit having an input connected to the delta-sigma analog-to-digital converter, the digital logic circuit configured to process an output signal of the delta-sigma analog-to-digital converter during a normal mode of operation; and a test circuit comprising a filter configured to receive the first digital bit stream from the output of the delta-sigma analog-to-digital converter and to apply a filtering process to the first digital bit stream to generate a second digital bit stream, wherein a sampling rate of the second digital bit stream is a fraction of a sampling rate of the first digital bit stream.

According to yet another embodiment, a method of operating an integrated circuit comprises: operating an oversampled data converter disposed on an integrated circuit in a normal operating mode comprises: receiving an input signal at an input terminal of an integrated circuit; converting the received input signal into an oversampled signal represented by an oversampled data stream; and outputting the oversampled data stream to an output terminal of the integrated circuit; and operating the oversampled data converter in the test mode comprises: receiving a test signal at an input terminal of an integrated circuit; converting the received test signal into an oversampled test signal represented by an oversampled data stream; and decimating the oversampled test signal to form a decimated test signal represented by a multi-bit output, the decimating comprising: integrating the oversampled data streams for a first predetermined number of test data streams using a single integrator to form an integrated value; and transmitting the integration value to a result register and resetting the single integrator after a first predetermined number of symbols of the test data stream.

The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 shows a block diagram of an interface circuit according to various embodiments of the present disclosure;

fig. 2 illustrates a simplified block diagram of the filter arrangement shown in fig. 1, in accordance with various embodiments of the present disclosure;

fig. 3 illustrates a detailed block diagram of the filter arrangement shown in fig. 1 according to various embodiments of the present disclosure;

FIG. 4 illustrates a flow chart of a control method for the filter arrangement shown in FIG. 1, in accordance with various embodiments of the present disclosure;

FIG. 5 illustrates a block diagram of another implementation of an interface circuit, according to various embodiments of the present disclosure; and is

Fig. 6 illustrates a block diagram of a processing system according to various embodiments of the present disclosure.

Corresponding numerals and symbols in the various drawings generally refer to corresponding parts unless otherwise indicated. The accompanying drawings are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.

Detailed Description

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.

The present disclosure, an apparatus and method for testing an analog-to-digital converter of a digital microphone, will be described in a particular context with respect to preferred embodiments. However, the present disclosure may also be applied to various systems and applications that convert analog signals generated by any sensor into digital signals. Hereinafter, various embodiments will be explained in detail with reference to the drawings.

Fig. 1 shows a block diagram of an interface circuit according to various embodiments of the present disclosure. The interface circuit is part of a digital sensor. In some embodiments, the digital sensor is a digital microphone. Throughout the description, the interface circuit may alternatively be referred to as a digital microphone interface circuit.

As shown in fig. 1, the digital microphone interface circuit includes a delta-sigma analog-to-digital converter (ADC)102, a logic circuit 104, a filter arrangement 114, a multiplexer 115, and an interface unit 116. The digital microphone may comprise other suitable elements, such as an acoustic sensor for detecting sound pressure waves.

Delta-sigma ADC102 is configured to receive an analog signal from a pressure sensitive diaphragm of a digital microphone. In some embodiments, the digital microphone is implemented as a microelectromechanical system (MEMS) microphone. Delta-sigma ADC102 is configured to operate at a predetermined first sampling frequency. Throughout the description, the sampling frequency of delta-sigma ADC102 may alternatively be referred to as the sampling rate of delta-sigma ADC 102.

In some embodiments, the analog input signal to delta-sigma ADC102 may come from a microphone sensor having a transducer that converts the sound pressure level of the sound wave into an analog signal. The analog signal is converted to a digital bit stream containing information for the analog signal using a suitable technique, such as oversampling.

As shown in fig. 1, the digital bit stream may be fed into two different processing paths. The first path includes logic circuitry 104. The second path comprises a filter arrangement 114. The output signal of the logic circuit 104 and the output signal of the filter means 114 are fed to a multiplexer 115. One of the received output signals is fed into an interface unit 116 through a multiplexer 115. As shown in fig. 1, the multiplexer 115 and the interface unit 116 are cascade-connected. In normal operation, the second path is disabled. A digital bit stream is fed into the first path. The second path is enabled when delta-sigma ADC102 is configured to operate in a test mode. The digital bit stream is fed into a second path comprising filter means 114.

Depending on different applications and design requirements, the logic circuit 104 may vary accordingly. In some embodiments, logic circuit 104 may include a low pass filter, a digital decimation filter, and an Active Noise Control (ANC) filter. The low pass filter is configured to attenuate high frequency components in the signal generated by delta-sigma ADC 102. In some embodiments, delta-sigma ADC102 may operate at a higher sampling frequency in order to meet particular performance specifications. The digital decimation filter is configured to convert a digital signal having a higher sampling rate to a digital signal having a lower sampling rate. The digital decimation filter may be implemented by a standard comb filter or a cascaded integrator-comb (CIC) filter as known in the art. The ANC filter may be implemented using a Finite Impulse Response (FIR) filter. FIR filters are well known in the art and therefore will not be discussed here.

In some embodiments, the filter arrangement 114 is implemented as a single integrator. The single integrator is configured to receive the digital signal from the output of delta-sigma ADC102 and apply a filtering process to the digital signal in order to reduce the sampling rate of the digital signal to a suitable level. The detailed structure of the filter arrangement 114 will be described below with reference to fig. 2-3.

In some embodiments, filter device 114 is used as a test device for testing delta-sigma ADC 102. The test apparatus (e.g., filter apparatus 114) and delta-sigma ADC102 are disposed on a single semiconductor substrate. Alternatively, the test apparatus and delta-sigma ADC102 are packaged in a single semiconductor package.

In operation, the digital microphone interface circuit shown in fig. 1 may be configured to operate in a normal operating mode or in a test mode. In the normal operation mode, the first control method is applied to the digital microphone interface circuit shown in fig. 1. In some embodiments, the first control method comprises: receiving an input signal at an input terminal of an integrated circuit (e.g., an input terminal of delta-sigma ADC 102); the received input signal is converted to an oversampled signal represented by an oversampled data stream and the oversampled data stream is output to an output terminal of the integrated circuit (e.g., an output terminal of the logic circuit 104).

In the test mode, the second control method is applied to the digital microphone interface circuit shown in fig. 1. In some embodiments, the second control method comprises: receiving a test signal at an input terminal of an integrated circuit (e.g., an input terminal of delta-sigma ADC 102); converting the received test signal into an oversampled test signal represented by an oversampled data stream; and decimating the oversampled test signal to form a decimated test signal represented by the multi-bit output. The step of decimating the oversampled test signal to form an oversampled test signal comprises: integrating the oversampled data streams for a first predetermined number of test data streams using a single integrator (e.g., the integrator of filter arrangement 114) to form an integrated value; and transmitting the integration value to a result register and resetting the single integrator after a first predetermined number of symbols of the test data stream. The test signal comprises a signal of a first amplitude. The second control method further includes: measuring the amplitude of the extracted test signal; and determining the sensitivity of the digital microphone based on the measured amplitude of the extracted test signal.

Fig. 2 illustrates a simplified block diagram of the filter arrangement shown in fig. 1, in accordance with various embodiments of the present disclosure. The filter arrangement 114 comprises a filter 202, a sample rate converter 203 and an intermediate stage 204. In some embodiments, the filter 202 is implemented as an integrator. The intermediate stage 204 is implemented as a synchronization Stage (SYNC). Throughout the description, the filter 202 may alternatively be referred to as an integrator. The intermediate stage 204 may alternatively be referred to as a sync stage.

As shown in fig. 2, the integrator 202 is configured to receive a digital bit stream having a first sample rate (fs). The digital bits are accumulated in the integrator 202 under control of the sample rate converter 203. The sample rate converter 203 is controlled such that the output signal of the integrator 202 is at a second sample rate (fs/R), where R is a predetermined integer. In some embodiments, R is equal to the oversampling rate of delta-sigma ADC 102. The output signal of the integrator 202 is transferred to the result register under the control of the synchronization stage 204.

Fig. 3 illustrates a detailed block diagram of the filter arrangement shown in fig. 1 according to various embodiments of the present disclosure. As shown in fig. 3, filter arrangement 114 is coupled between delta-sigma ADC102 and interface unit 116. An input of filter arrangement 114 is configured to receive an output signal of delta-sigma ADC 102. As indicated by the double-headed arrow shown in fig. 3, the output of the filter device 114 and the input of the interface unit 116 exchange information. It should be noted that a multiplexer may be coupled between the filter arrangement 114 and the interface unit 116.

The input of the filter means 114 is configured to receive a first digital signal having a first sample rate. The first digital signal is generated by delta-sigma ADC 102. The output of the filter means 114 generates a second digital signal having a second sampling rate. The first sampling rate is higher than the second sampling rate. The ratio of the first sample rate of delta-sigma ADC102 to the second sample rate of the output signal of integrator 302 is equal to a predetermined reference value. In some embodiments, the ratio of the first sample rate to the second sample rate is equal to the oversampling rate of delta-sigma ADC 102.

As shown in fig. 3, filter arrangement 114 includes a filter 302, a control circuit 304, a first synchronization stage 306, a setting register 308, a result register 310, a second synchronization stage 312, an output register 314, an oversampling ratio (OSR) register 316, and a Power Mode Detector (PMD) 318. In some embodiments, control circuit 304 is implemented as a counter. Throughout the description, control circuit 304 may alternatively be referred to as a counter. In some embodiments, the filter 302 may be implemented as an integrator. Throughout the description, the filter 302 may alternatively be referred to as an integrator.

The bit widths (NoBits) of the integrators, counters and registers shown in fig. 3 are selected based on the following equation:

where R is the oversampling ratio of delta-sigma ADC102, N is the number of integrators in filter arrangement 114, and N_INIs the number of bits of the Pulse Density Modulated (PDM) data stream. According to one embodiment, R is equal to 76. N equals 1 (a separate integrator in the filter arrangement 114). N is a radical of_INEqual to 1(1 bit PDM data stream). The bit width of the integrator, counter and register shown in fig. 3 is equal to 7.

It should be noted that the bit widths used in the previous examples were selected merely for illustration purposes and are not intended to limit the various embodiments of the present disclosure to any particular bit width.

As shown in fig. 3, integrator 302 is configured to receive a digital signal from delta-sigma ADC102, a control signal from counter 304, and an enable signal from a set register 308. A set register 308 is employed to control the operation of the integrator 302. In some embodiments, one bit of the set register 308 is used to store a control signal for controlling the operation of the integrator 302. The setting register 308 may be accessed via a suitable communication channel, such as a standard communication interface of a digital microphone. In operation, when delta-sigma ADC102 is configured to operate in a test mode, set register 308 sends an enable signal to integrator 302. In response to the enable signal, integrator 302 applies a filtering process to the digital signal generated by delta-sigma ADC 102. On the other hand, when delta-sigma ADC102 is configured to operate in the normal operating mode, setting register 308 disables operation of integrator 302.

In some embodiments, the integrator 302, the counter 304, the result register 310, the synchronization stages 306 and 312, and the output register 314 form a test circuit configured to perform sensitivity measurements on a digital microphone. More specifically, the test circuit includes a single integrator configured as a filter arrangement for converting an output signal of an analog-to-digital converter (e.g., delta-sigma ADC 102) having a first sample rate to an output signal of the test circuit having a second sample rate. In some embodiments, the first sampling rate is higher than the second sampling rate.

PMD 318 is employed to provide a reference value for counter 304. In some embodiments, the reference value from PMD 318 represents the actual clock rate of delta-sigma ADC 102. The reference value from PMD 318 is fed into OSR register 316. PMD 318 and OSR register 316 are controlled so that the reference values are updated based on the various operating modes. In other words, delta-sigma ADC102 may have different oversampling rates in different operating modes. The reference value may be modified accordingly based on the actual over-sampling rate. In some embodiments, the reference value is equal to the oversampling rate of delta-sigma ADC 102. For example, delta-sigma ADC102 has an oversampling rate of 76. The reference value is equal to 76.

In a test operation, the integrator 302 and the counter 304 have been reset prior to the filtering process. During the filtering process, the digital bit stream is fed into an integrator 302. In each clock cycle, the output of integrator 302 is incremented by 1 in response to a digital bit of 1 from the bit stream. On the other hand, in response to a digital bit of 0 from the bit stream, the output of integrator 302 is decremented by 1. In each clock cycle, the counter 304 is incremented by 1. After the counter 304 has been incremented by 1, the value of the counter 304 is compared to a reference value. If the value of the counter 304 is less than the reference value, the integrator 302 and the counter 304 continue for the next clock cycle in which the filtering process described above is repeated. If the value of the counter 304 is equal to the reference value, the counter 304 terminates the filtering process. After the counter 304 terminates the filtering process, the integrator 302 sends the current value of the integrator 302 to the result register 310 under the control of the first synchronization stage 306.

As shown in fig. 3, the first synchronization stage 306 is configured to communicate with the counter 304. Once the integration process has been terminated, the first synchronization stage 306 is ready for data transfer between the integrator 302 and the result register 310. After sending the current value of integrator 302 to result register 310, both integrator 302 and counter 304 are reset. The integrator 302 and the counter 304 proceed to the next clock cycle. In addition, the value stored in the result register 310 is transferred to the output register 314 under the control of the second synchronization stage 312. The above control scheme will be discussed again below with reference to the flowchart shown in fig. 4.

It should be noted that both the first synchronization stage 306 and the second synchronization stage 312 are necessary for processing the results generated by the integrator 302. When processing data, there may be a delay before the results are available. It is necessary to have a synchronization stage to align and latch the result data into the output register.

Fig. 4 illustrates a flow chart of a control method for the filter arrangement shown in fig. 1, in accordance with various embodiments of the present disclosure. The flow chart shown in fig. 4 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps shown in FIG. 4 may be added, removed, replaced, rearranged, and repeated.

Referring back to fig. 1, the delta-sigma ADC is configured to receive an analog signal generated by an acoustic sensor of the digital microphone. The delta-sigma ADC is an oversampling ADC. In operation, the delta-sigma ADC converts an analog signal to a digital signal when the delta-sigma ADC is configured to operate in a normal mode. The digital signal is fed into a logic circuit for further processing of the digital signal. On the other hand, when the delta-sigma ADC is configured to operate in a test mode, a test analog signal is fed into the delta-sigma ADC, wherein the test analog signal is converted into a test digital signal. The test digital signal has a first sampling rate (sampling frequency). The test digital signal is fed into the filter arrangement, wherein the test digital signal is converted into a digital signal having a second sampling rate. The first sampling rate is higher than the second sampling rate.

Referring back to fig. 2, the filter arrangement comprises a single integrator. The input signal applied to the single integrator has a first sampling frequency. By means of a sample rate converter an input signal having a first sampling frequency is converted into an output signal having a second sampling frequency. In particular, a single integrator is employed to integrate the input signal (oversampled data stream) for a first predetermined number of symbols of the test data stream to form an integrated value. The integration value is the result generated by the integrator. The result is transmitted to the output of the filter means through the synchronization stage.

Referring back to fig. 3, the sample rate converter in fig. 2 may be implemented as a counter that is used to convert a digital signal having a higher sampling frequency to a digital signal having a lower sampling frequency. In operation, the integrator is configured to receive a bit stream generated by the delta-sigma ADC. In each clock cycle, the integrator receives a bit. The counter is incremented by 1. The value of the counter represents the number of clock cycles. The integrator holds the value of the accumulated bit stream until the number of clock cycles reaches a predetermined reference value. After reaching the predetermined reference value, the value of the integrator is transferred to the result register, and then both the integrator and the counter are reset. The detailed operating principle of the integrator and the counter is shown in the flow chart shown in fig. 4.

In the test mode, the control method 400 includes: the method comprises the steps of providing a test signal to an analog-to-digital converter (e.g., a delta-sigma ADC as shown in fig. 1), converting the test signal to a first digital signal having a first sample rate, decimating the first digital signal by a factor equal to a predetermined reference value using an integrator, and determining a sensitivity of the analog-to-digital converter based on a result from the step of decimating the first digital signal by a factor equal to the predetermined reference value using the integrator.

The oversampling rate of the delta-sigma ADC is retrieved and saved as a reference value before the control method 400 begins at step 402. The clock signal is sent to the filter means. In response to the clock signal, the filter arrangement is reset at step 402. More particularly, the output of the integrator is set to zero. Further, the value of the counter is set to zero.

The bit stream generated by the delta-sigma ADC is a binary bit having two levels (i.e., a logic high and a logic low). At step 404, if the input bit is logic high (equal to 1), the control method 400 proceeds to step 406. Otherwise, control method 400 proceeds to step 408.

At step 406, the output signal of the integrator is incremented by 1 in response to a digital bit 1 from the bit stream. The counter is incremented by 1. As shown in FIG. 4, after completing step 406, control method 400 proceeds to step 410.

At step 408, the output signal of the integrator is decremented by 1 in response to a digital bit of 0 from the bit stream. The counter is incremented by 1. As shown in FIG. 4, after completing step 408, control method 400 proceeds to step 410.

At step 410, the value of the counter is compared to a predetermined reference value. In some embodiments, the predetermined reference value is an oversampling ratio (OSR) of the delta-sigma ADC. According to one embodiment, the OSR is equal to 76. In other words, the sampling frequency of the delta-sigma ADC is 76 times the sampling frequency of the output signal of the filter arrangement. Also at step 410, if the value of the counter is equal to the OSR, the control method 400 proceeds to

steps

402 and 412. Otherwise, the control method 400 proceeds to step 404 where the integrator processes another input bit in step 404.

At step 412, the result of the integrator is latched into the result register. At step 402, the counter is reset and the counter is ready to begin counting the number of clock cycles from step 404. Also at step 402, the integrator is set to zero after the result of the integrator has been latched into the result integrator at step 412.

At step 414, the data in the result register is latched into the output register by the appropriate synchronization process. For example, after receiving the synchronization signal, the data in the result register is latched into the output register.

Fig. 5 illustrates a block diagram of another implementation of an interface circuit, according to various embodiments of the present disclosure. The system configuration of the interface circuit shown in fig. 5 is similar to the system configuration of the interface circuit shown in fig. 1, except that the input of the filter device 114 is connected to the output of the logic circuit 104. The operating principle of the interface circuit shown in fig. 5 is similar to that of the interface circuit shown in fig. 1 and will therefore not be discussed again to avoid unnecessary repetition.

Fig. 6 illustrates a block diagram of a processing system according to various embodiments of the present disclosure. Processing system 500 depicts a general purpose platform and general components and functionality that may be used to implement portions of and/or external computers or processing devices that interface with an embodiment charge pump converter. For example, the processing system 500 may be used to control the circuits shown in fig. 1-3. In some embodiments, the processing system 500 may be used to determine various control signals, such as the enable signal shown in fig. 3.

For example, the processing system 500 may include a Central Processing Unit (CPU)502, a memory 504 connected to a bus 508, and may be configured to perform the processes described above. The processing system 1100 may also include, if desired or needed: a display adapter 510 to provide connectivity to a local display 512; and an input-output (I/O) adapter 514 to provide an input/output interface for one or more input/output devices 516, such as a mouse, keyboard, flash drive, etc.

The processing system 500 may also include a network interface 518, which may be implemented using a network adapter configured to couple to a wired link (such as a network cable, USB interface, etc.) and/or a wireless/cellular link for communication with the network 520. Network interface 518 may also include suitable receivers and transmitters for wireless communications. It should be noted that the processing system 500 may include other components. For example, if implemented externally, the processing system 500 may include hardware component power supplies, cables, motherboards, removable storage media, housings, and the like. Although not shown, these other components are considered part of the processing system 500. In some embodiments, the processing system 500 may be implemented on a single monolithic semiconductor integrated circuit and/or on the same monolithic semiconductor integrated circuit as the other disclosed system components.

Embodiments of the invention are summarized herein. Other embodiments are also understood from the entire description and claims herein.

Example 1. a system, comprising: an analog-to-digital converter configured to convert an analog signal generated by the digital sensor into a digital signal; and a test arrangement configured to be enabled after the analog to digital converter operates in a test mode, wherein the test arrangement comprises: a filter configured to receive the digital signal from the analog-to-digital converter and apply a filtering process to the digital signal; a control circuit configured to terminate the filtering process after an output of the control circuit reaches a predetermined reference value; and a result register configured to receive a result generated by the filter after the control circuit terminates the filtering process.

Example 2. the system of example 1, wherein the analog-to-digital converter is a delta-sigma analog-to-digital converter.

Example 3. the system according to example 1 or example 2, further comprising: an intermediate stage configured to control data transfer from the result register to the output register.

In some embodiments, the intermediate stage is configured to control data transfer. More particularly, the intermediate stage is configured to send data successively to the output port of the analog-to-digital converter. In operation, at the beginning of a data transmission, the intermediate stage is configured to send a data packet that includes a fixed, known pattern. The fixed known pattern is used to indicate that the data packet is the first data packet of a data transmission. After receiving the first data packet, the output port receives data from the intermediate stage in succession.

Example 4. the system of example 3, wherein the digital sensor is a digital silicon microphone, the filter is an integrator, the control circuit is a counter, and the intermediate stage is a synchronous stage, and wherein the integrator, the counter, the result register, the synchronous stage, and the output register form a test circuit configured to perform sensitivity measurements on the digital silicon microphone.

Example 5. the system of example 4, wherein the test circuit comprises a single integrator configured as a filter arrangement for converting an output signal of the analog-to-digital converter having the first sampling rate to an output signal of the test circuit having the second sampling rate.

Example 6. the system of example 5, wherein a ratio of the first sampling rate of the output signal of the analog-to-digital converter to the second sampling rate of the output signal of the test circuit is equal to a predetermined reference value.

Example 7. the system of one of examples 1 to 6, wherein the test device and the analog-to-digital converter are disposed on a single semiconductor substrate.

Example 8. the system of one of examples 1 to 7, wherein the predetermined reference value is determined based on an oversampling rate of an analog-to-digital converter.

Example 9. a method, comprising: configuring the analog-to-digital converter to operate in a test mode; configuring a filter to receive a bit stream generated by an analog-to-digital converter and accumulate values of the bit stream until the number of clock cycles reaches a predetermined reference value; and transmitting the output signal of the filter to the result register.

Example 10. the method according to example 9, further comprising: increasing the output signal of the filter by 1 in response to a digital bit 1 from the bit stream; and decrementing the output signal of the filter by 1 in response to a digital bit of 0 from the bit stream.

Example 11. the method according to one of example 9 or example 10, further comprising: the filter is reset prior to the step of configuring the filter to receive the bit stream generated by the analog-to-digital converter and accumulating the values of the bit stream.

Example 12. the method according to one of examples 9 to 11, further comprising: resetting the counter; in each clock cycle, increasing the output signal of the filter by 1 in response to a digital bit 1 from the bit stream; in response to a digital bit 0 from the bit stream, decrementing the output signal of the filter by 1 and incrementing the counter by 1; and transmitting an output signal of the filter to the result register after the counter reaches a predetermined reference value.

Example 13. the method according to one of examples 9 to 12, further comprising: in response to the synchronization signal, the output signal is transferred to the result register and then to the output register.

Example 14. the method of one of examples 9 to 13, wherein the analog-to-digital converter is a delta-sigma analog-to-digital converter having a first sampling rate, and a ratio of the first sampling rate of the delta-sigma analog-to-digital converter to a second sampling rate of the output signal of the filter is equal to a predetermined reference value.

Example 15. the method according to one of examples 9 to 14, further comprising: providing the test signal to an analog-to-digital converter; converting the test signal into a first digital signal having a first sampling rate; decimating the first digital signal by a factor equal to a predetermined reference value using a filter; and determining the sensitivity of the analog-to-digital converter based on the result from the step of decimating the first digital signal by a factor equal to a predetermined reference value using a filter.

Example 16. a system, comprising: a delta-sigma analog-to-digital converter having an input coupled to the digital sensor; a digital logic circuit having an input connected to the delta-sigma analog-to-digital converter, the digital logic circuit configured to process an output signal of the delta-sigma analog-to-digital converter during a normal mode of operation; and a test circuit comprising a filter configured to receive the first digital bit stream from the output of the delta-sigma analog-to-digital converter and to apply a filtering process to the first digital bit stream to generate a second digital bit stream, wherein a sampling rate of the second digital bit stream is a fraction of a sampling rate of the first digital bit stream.

Example 17. the system of example 16, wherein the test circuitry comprises: a filter configured to receive a first digital bit stream; a control circuit configured to terminate the filtering process after an input of the control circuit reaches a predetermined reference value; a result register configured to receive a result generated by the filter after the control circuit terminates the filtering process; an output register configured to receive a result from the result register; and an intermediate stage configured to control data transfer from the result register to the output register.

Example 18 the system of example 17, wherein the control circuit is a counter, and wherein the counter is configured as a sample rate converter to reduce a sample rate of the first digital bit stream.

Example 19. the system of one of examples 16 to 18, wherein a ratio of a sampling rate of the first digital bit stream to a sampling rate of the second digital bit stream is equal to an oversampling rate of the delta-sigma converter.

Example 20 the system of one of examples 16 to 19, wherein the delta-sigma analog-to-digital converter, the digital logic circuit, and the test circuit are disposed on a single semiconductor substrate.

Example 21 a method of operating an integrated circuit, the method comprising: operating an oversampled data converter disposed on an integrated circuit in a normal operating mode, comprising: receiving an input signal at an input terminal of an integrated circuit; converting the received input signal into an oversampled signal represented by an oversampled data stream; and outputting the oversampled data stream to an output terminal of the integrated circuit; and operating the oversampled data converter in the test mode comprises: receiving a test signal at an input terminal of an integrated circuit; converting the received test signal into an oversampled test signal represented by an oversampled data stream; and decimating the oversampled test signal to form a decimated test signal represented by a multi-bit output, the decimating comprising integrating the oversampled data streams for a first predetermined number of test data stream symbols using a single integrator to form an integrated value; and after a first predetermined number of test data stream symbols, transmitting the integration value to a result register and resetting the single integrator.

Example 22 the method of example 21, wherein the test signal comprises a signal of a first amplitude, and the method further comprises measuring the amplitude of the extracted test signal.

Example 23. the method according to one of example 21 or example 22, further comprising: the sensitivity is determined based on the measured amplitude of the extracted test signal.

Although embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. A system, comprising:

an analog-to-digital converter configured to convert an analog signal generated by the digital sensor into a digital signal; and

a test device configured to be enabled after the analog-to-digital converter operates in a test mode, wherein the test device comprises:

a filter configured to receive the digital signal from the analog-to-digital converter and apply a filtering process to the digital signal;

a control circuit configured to terminate the filtering process after an output of the control circuit reaches a predetermined reference value; and

a result register configured to receive a result generated by the filter after the control circuit terminates the filtering process.

2. The system of claim 1, wherein:

the analog-to-digital converter is a delta-sigma analog-to-digital converter.

3. The system of claim 1, further comprising:

an intermediate stage configured to control data transfer from the result register to an output register.

4. The system of claim 3, wherein:

the digital sensor is a digital silicon microphone;

the filter is an integrator;

the control circuit is a counter; and

the intermediate stage is a synchronous stage and wherein the integrator, the counter, the result register, the synchronous stage and the output register form a test circuit configured to perform sensitivity measurements on the digital silicon microphone.

5. The system of claim 4, wherein:

the test circuit comprises a single integrator configured as a filter arrangement for converting an output signal of the analog-to-digital converter having a first sampling rate into an output signal of the test circuit having a second sampling rate.

6. The system of claim 5, wherein:

the ratio of the first sampling rate of the output signal of the analog-to-digital converter to the second sampling rate of the output signal of the test circuit is equal to the predetermined reference value.

7. The system of claim 1, wherein:

the test apparatus and the analog-to-digital converter are arranged on a single semiconductor substrate.

8. The system of claim 1, wherein:

the predetermined reference value is determined based on an oversampling rate of the analog-to-digital converter.

9. A method, comprising:

configuring the analog-to-digital converter to operate in a test mode;

configuring a filter to receive a bit stream generated by the analog-to-digital converter and accumulate values of the bit stream until a number of clock cycles reaches a predetermined reference value; and

the output signal of the filter is transmitted into a result register.

10. The method of claim 9, further comprising:

incrementing said output signal of said filter by 1 in response to a digital bit 1 from said bit stream; and

reducing the output signal of the filter by 1 in response to a digital bit of 0 from the bitstream.

11. The method of claim 9, further comprising:

resetting the filter prior to the step of configuring the filter to receive the bitstream generated by the analog-to-digital converter and accumulating the values of the bitstream.

12. The method of claim 9, further comprising:

resetting the counter;

in each clock cycle, incrementing said output signal of said filter by 1 in response to a digital bit 1 from said bit stream, decrementing said output signal of said filter by 1 in response to a digital bit 0 from said bit stream, and incrementing said counter by 1; and

transmitting the output signal of the filter into the result register after the counter reaches the predetermined reference value.

13. The method of claim 9, further comprising:

in response to a synchronization signal, the output signal is transferred into the result register and then to an output register.

14. The method of claim 9, wherein:

the analog-to-digital converter is a delta-sigma analog-to-digital converter having a first sampling rate; and

a ratio of the first sample rate of the delta-sigma analog-to-digital converter to a second sample rate of the output signal of the filter is equal to the predetermined reference value.

15. The method of claim 9, further comprising:

providing a test signal to the analog-to-digital converter;

converting the test signal to a first digital signal having a first sampling rate;

decimating the first digital signal by a factor equal to the predetermined reference value using the filter; and

determining the sensitivity of the analog-to-digital converter based on a result from the step of decimating the first digital signal by a factor equal to the predetermined reference value using the filter.

16. A system, comprising:

a delta-sigma analog-to-digital converter having an input coupled to the digital sensor;

a digital logic circuit having an input connected to the delta-sigma analog-to-digital converter, the digital logic circuit configured to process an output signal of the delta-sigma analog-to-digital converter during a normal mode of operation; and

a test circuit comprising a filter configured to receive a first digital bit stream from an output of the delta-sigma analog-to-digital converter and to apply a filtering process to the first digital bit stream to generate a second digital bit stream, wherein a sampling rate of the second digital bit stream is a fraction of a sampling rate of the first digital bit stream.

17. The system of claim 16, wherein the test circuit comprises:

the filter configured to receive the first digital bit stream;

a control circuit configured to terminate the filtering process after an output of the control circuit reaches a predetermined reference value;

a result register configured to receive a result generated by the filter after the control circuit terminates the filtering process;

an output register configured to receive the result from the result register; and

an intermediate stage configured to control data transfer from the result register to the output register.

18. The system of claim 17, wherein the control circuit is a counter, and wherein:

the counter is configured as a sample rate converter to reduce the sample rate of the first digital bit stream.

19. The system of claim 16, wherein:

a ratio of the sample rate of the first digital bit stream to the sample rate of the second digital bit stream is equal to an oversampling rate of the delta-sigma analog-to-digital converter.

20. The system of claim 16, wherein:

the delta-sigma analog-to-digital converter, the digital logic circuit, and the test circuit are disposed on a single semiconductor substrate.

21. A method of operating an integrated circuit, the method comprising:

operating an oversampled data converter disposed on the integrated circuit in a normal operating mode, comprising:

receiving an input signal at an input terminal of the integrated circuit;

converting the received input signal into an oversampled signal represented by an oversampled data stream; and

outputting the oversampled data stream to an output terminal of the integrated circuit; and

operating the oversampled data converter in a test mode, comprising:

receiving a test signal at the input terminal of the integrated circuit;

converting the received test signal into an oversampled test signal represented by the oversampled data stream; and

decimating the oversampled test signal to form a decimated test signal represented by a multi-bit output, the decimating comprising:

integrating the oversampled data streams for a first predetermined number of test data stream symbols using a single integrator to form an integrated value; and

after the first predetermined number of test data stream symbols, transmitting the integration value to a result register and resetting the single integrator.

22. The method of claim 21, wherein:

the test signal comprises a signal of a first amplitude; and

the method also includes measuring an amplitude of the extracted test signal.

23. The method of claim 22, further comprising:

the sensitivity is determined based on the measured amplitude of the extracted test signal.